Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA.doc

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Design and implementation of truncated multipliers for precision improvement AIM: The main aim of the project is to design “Design and implementation of truncated multipliers for precision improvement”. ABSTRACT: Trunc ated multiplie rs offer significa nt impro vemen ts in area, delay, and  power. The proposed method finally reduces the number of full adders and half adders during the tre e re duction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and SB. !inally the LSB part is compressed by using operations such as deletion, reduction, truncation, rounding and final addition. "n previous related papers, to reduce the truncation error by adding error compensation circuits. "n this project truncation error is not more than # ulp $unit of least position%. So there is no need of error compensation circuits, and the final output will be pr&cised. B!C" DIA#RAM: V.Mallikarjun a (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY  Branch!: "#$ra%a$ & Na'()r

Transcript of Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA.doc

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Design and implementation of truncated multipliers for precision

improvement

AIM:

The main aim of the project is to design “Design and implementation of

truncated multipliers for precision improvement”.

ABSTRACT:

Truncated multipliers offer significant improvements in area, delay, and

 power. The proposed method finally reduces the number of full adders and half

adders during the tree reduction. While using this proposed method

experimentally, area can be saved. The output is in the form of LSB and SB.

!inally the LSB part is compressed by using operations such as deletion, reduction,

truncation, rounding and final addition. "n previous related papers, to reduce the

truncation error by adding error compensation circuits. "n this project truncationerror is not more than # ulp $unit of least position%. So there is no need of error

compensation circuits, and the final output will be pr&cised.

B!C" DIA#RAM:

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY   Branch!: "#$ra%a$ &Na'()r

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• The proposed multiplier consumes low power of 00mW when compared to

scheme # and scheme +.

R'('R'%C'S:

• 1. . 1ou, S. 2. 3uang, and 2. 4. 5hen, 64esign of lowerror fixed7 width

multipliers for 4S( applications,8 " Trans. 5ircuits Syst. "", s 9nalog

4igit. Signal (rocess. vol. -, no. -, pp. 0:-;0+.

• L.74. <an and 5.75. =ang, 6>enerali?ed low7error areaefficient fixed width

multipliers,8 " Trans. 5ircuits Syst. ", 2eg. (apers, vol. @+, no. 0, pp.

#-A0;#-#*.

• . 1. Schulte and . . Swart?lander, 1r., 6Truncated multiplication with

correction constant,8 in <LS" Signal (rocessing <". (iscataway, 1'"

(ress, #**:, pp. :00;:*-.

• . 1. 3ing and . . Swart?lander, 1r., 64ata7dependent truncation scheme

for parallel multipliers,8 in (roc. :#st 9silomar 5onf. Signals, Syst.

5omput., #**C, pp. ##C0;##0+.

• . 1. Schulte, 1. >. Dansen, and 1. . Stine, 62educed power dissipation

through truncated multiplication,8 in (roc. " 9lessandro <olta emorial

"nt. Wor/shop Low (ower 4es., pp. -#;-*.

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY   Branch!: "#$ra%a$ &Na'()r