Depleted CMOS Detectors - HKUST Jockey Club Institute...

1/25/2017

D. Bortoletto

University of Oxford

D. Bortoletto IAS-HKUST 1

Depleted CMOS Detectors

1/25/2017

Outline

• Impossible to cover all activities ongoing on depleted CMOS in 20 min.− Many technologies − Many new ideas− A lot of enthusiasm− Clearly they are the future

• I will mainly cover activities aimed at HL-LHC (support also from AIDA2020)


HV CMOS• AMS 350 nm • AMS 180 nm

SOI – CMOS Pixel

• XFAB 180 nm

HR CMOS

(sometime with HV

adds on)

• LFOUNDRY

AMS 150 nm

• Global Foundry

130 nm

• ESPROS 150

nm

• Toshiba 130 nm

• TowerJazz 180

nm

• IBM T3 130 nm• STM 180 nm

1/25/2017 D. Bortoletto IAS-HKUST 3

1/25/2017

HYBRID PIXEL DETECTORS


The ATLAS pixel

ATLAS IBL pixel

Layer

The CMS pixel

• PROS:− complex signal processing already in pixel cell

possible• Zero suppression

• Temporary storage of hits during L1 latency

− radiation hard to >1015 neq/cm2

− high rate capability (~MHz/mm2)−Good spatial resolution ~ 10 – 15 μm

• CONS−Relatively large material budget: 3.5-1.5% X0 /layer in

ATLAS/CMS• Sensor + chip + flex kapton + passive components

• Support, cooling (-10oC operation), services

−Complex module production

−Bump-bonding / flip-chip ⇒expensive

1/25/2017

From hybrid to monolithic pixels

• Cheaper & better performance?

• Better resolution

• Easier module production

• No bump-bonding

• Lower material budget


FESensor

Bump bonding

• Can we combine detection and readout in one ROC ?

STAR MAPS 2014 0.16 m2Technology of choice for ILC

1/25/2017

Monolithic Active Pixels (MAPS)


IPHC Strasbourg (PICSEL group))

• Lightly doped p-type epitaxial layer (~14-20 μm,

active volume)

− MIPs produce ~80 e-/h+ pairs per μm (~1000

e- )

− Not fully depleted ⇒ Charge collection mainly

by diffusion (~100 ns)

− 100% fill-factor

• N-well implantation used for collecting electrode

• Only nMOS transistors (in p-well) are possible in

the pixel area

− Limited in-pixel electronics

− More complex electronics at the periphery of

the sensing matrix

• Fabricated in commercial CMOS technologies

(leading edge performance, low-cost)

Applications: STAR-detector (RHIC Brookhaven) and Eudet beam-telescope

Ionizing Particle

1/25/2017

MAPS in STAR• Data taking since 2014 (Au-Au, p-p, p-Au-

collisions)


carbon fiber sector tubes

(~ 200 μm thick)

Topological reconstruction of charm hadrons

such as D0 which a lifetime ∼ 120 μm

356 M

pixels

in 2

layers

~0.16 m2

Ladder with10 MAPS

1/25/2017

INMAPS • TowerJazz and Rutherford Appleton Laboratory

− Deep P-Well to shield the PMOS transistors from

epi layer

• No charge loss occurs

• Full CMOS ➠ Smart pixels possible

− Disadvantages

• Not a standard process ➠ limited number of

producers


• INMAPS on High Resistivity resistivity (> 1kΩ cm) p-

type epi-layer 18-40 µm thick

• Moderate reverse bias to increase depletion

zone around NWELL diode ➠ some charge

collection by drift

• Small n-well collecting diodes small ➠ Cin• Radiation tolerance (TID) to 700 krad

(= 1/1500 of HL-LHC-pp)

Application in HEP: ALICE

ALICE ITS, SEM picture of prototype chip

epitaxial layer ~ 24 µm

standard low res. substrate

R. Turchetta, W. Snoeys

1/25/2017

ALPIDE

D. Bortoletto IAS-HKUST12

• Pixel size: 29 x 27 µm2 with low power

front-end ~40 nW/pixel

• Extensive tests before and after irradiation

30 mm

15

mm

0.5 x 106 pixels

(pA)THR

Threshold Current I200 400 600 800 1000 1200 1400 1600 1800

Dete

ctio

n E

ffic

ien

cy

0.95

0.955

0.96

0.965

0.97

0.975

0.98

0.985

0.99

0.995

1

sensitivity limit

0.015% pixels masked

Fake-Hit Rate Efficiency

Non-irradiated

2/cmeq 1MeV n1310´ 1.7 Fake

-Hit R

ate

/Pix

el/E

ven

t

11-10

10-10

9-10

8-10

7-10

6-10

5-10

4-10

3-10

2-10

1-10

(pA)THR


m)

mR

esolu

tion

(

0

1

2

3

4

5

6

7

Cluster Size Resolution

Non-irradiated

2/cmeq 1MeV n1310´ 1.7

Clu

ste

r S

ize (

Pix

el)

0

1

2

3

4

5

6

7

8

9

10

(pA)THR


Dete

ctio

n E

ffic

ien

cy

0.95

0.955

0.96

0.965

0.97

0.975

0.98

0.985

0.99

0.995

1

sensitivity limit

0.015% pixels masked

Fake-Hit Rate Efficiency

Non-irradiated

2/cmeq 1MeV n1310´ 1.0 Fake

-Hit R

ate

/Pix

el/E

ven

t

11-10

10-10

9-10

8-10

7-10

6-10

5-10

4-10

3-10

2-10

1-10

• Efficiency > 99.5% and fake hit rate << 10-5 over wide threshold range

• Excellent performance also after irradiation to 1013 (1MeV neq)/cm2

25 µm epitaxial layer, -6V back bias

1/25/2017

HL-LHC Specifications• Outer layers

−Occupancy 1-2 MHz/mm2

−NIEL ~ 1015 neq/cm2

− TID ~ 50 Mrad

− Larger area O(10m2 )

• Inner layers−Occupancy 10-30

MHz/mm2

−NIEL ~ 1016 neq/cm2

− TID ~ 1 Grad

−Smaller area O(1 m2)


1/25/2017

Depleted CMOS HL-LHC• The rate/radiation environment of the HL-LHC is challenging but CMOS could:

− Lower cost large area detectors using commercial fabs

− More pixel layers in trackers

− A reduction of material and power

• R&D is ongoing with the goal of:

− Achieve a depletion depth of 40 – 80 μm

− Fast charge collection (for < 25ns “in-time” collection)

− Reasonably large signal ~4000 e-

− Small collection distance to avoid trapping and increase rad hardness


10 Ω cm

NW: 1V

PW: 0V

low resistivity

& Low Voltage

𝑑 ∝ 𝜌𝑉

2 kΩ cmHigh resistivity &

higher voltages

1/25/2017

Enabling technologies


• “High” Voltage

• “High” resisitivity

• “Technology features”

• Backside processing

Special processing for automotive and power management

application to allow the HV necessary to create a depletion

layer in a well’s pn-junction of o(10-15 μm).

Radiation hard processes with multiple wells.

Foundry must accept some process/DRC changes to

optimize the design for HEP.

Wafer thinning from backside and backside implant

to fabricate a backside contact aner CMOS processing

Hi/mid resistivity silicon wafers accepted/qualified by the

foundry to facilitate the needed depletion layer

1/25/2017

Design choices toward DMAPS


Electronics inside charge collection well

• Full CMOS with additional deep-p implant

• Small collection node

• Smaller capacitance ➠ less power

• Long drift path

Electronics outside collection well

• Deep n and p wells

• Large collection node

• Large sensors capacitance sensor

capacitance (DNW/PW junction!) ➠

X-talk, noise & speed (power) penalties

• Short drift path

p-substrate

Deep n-well

P+ p-well

Charge signal

Electronics (full CMOS)

P+nw

-

p-substrate

n+ p-well

Charge signal

Electronics (full CMOS)

n+nw

deep p-well

-

1/25/2017

Capacitive Coupled Pixel Detector (CCPD)


Ivan Peric proof-of-concept HV-

AMS 0.35 μm (2006)

• Hybrid Pixels with Smart Diodes

• Preamplifier very close to the collection

node ⇒ large signal output

• Cheaper:

− Capacitive coupling could yield cost

reduction

− Large scale production offered by HV-

CMOS foundries

• Concept could be used also for strip

detector (HVstrip1, CHESS, CHESS2)

DMAPS

chip

FEI4

1/25/2017

CCPD


S33 μm x 125 μm

50 μm x 250 μm

• CCPD with sub-pixel address encoding• CCPD with one-to-one

pixels

• AMS H18: KIT, Geneve, Heidelberg, IFAE, Liverpool, Brookhaven, CERN, Tsukuba

1/25/2017

HV-CMOS stripo Pseudo strips made up of pixels

(~40 mm x 800 mm )

o Amplifiers and comparators

could be on sensor but the rest

of processing into a readout

ASIC

o Can yield :o 2D coordinates

o Cost savings

o Faster construction

o Less material in the tracker

o Max reticle sizes are ~2x2 cm2.

Therefore rows of 4-5 chips

could be the basic units (yield

performance is critical here)


CHESS 1 - CHip for CMOS

Evaluation of Strip Sensors

H 350 nm AMS, 20 Ωcm

CHESS 2: full reticle size of 20mm x 24 mm AMS-H35 technology with different resistivity: 20, 50-100, 200-300, 600-2000 Ω -cm.(SLAC & UCSC)

1/25/2017

CCPD sensor family (HV-AMS 180 nm)


• CCPDV1 and 2

− Chip size: 2.2mm x 4.4mm

− Pixel matrix: 60x24 (sub-pixels

of 33 μm x 125μm)

− Pixels contain charge sensitive

amplifier, comparator and

Tune DAC

− 3 operation modes;

Standalone, strip-like, and

pixel (with FEi4)

• CCPDv3 (shared with

CLIC)

− 25x25μm pixels

containing only amplifier

− Matching the

CLICPix65nm ASIC

• CCPDv4 (AMS H18)

With 4 types of pixels

“NewPixels” with

Separated electronic and electrode

1/25/2017

CCPD-LF• LFoundry 150 nm CMOS technology:

− 2kΩcm p-type bulk

− Bonn, CPPM (Marseille), IRFU

(Saclay) collaboration

− R&D includes passive CMOS sensors

as a potential sensor alternative


CCPD_LF (A/B) subm. Sep 2014

fast R/O coupled to FE-I4

also stand-alone testable

33 x 125 μm2

5 mm x 5 mm

LF-CPIX Demonstratorsubm. March 2016

fast R/O coupled to FE-I4

also stand alone testable

50 x 250 μm2 pixels

LF-Monopix01subm. Aug. 2016

LF_CPIX Demo +

stand-alone fast R/O

column drain type R/O

variants

1/25/2017

E-TCT results• Reactor neutron: 2e14, 5e14, 1e15, 2e15, 5e15,

1e16n/cm2


Scan along the sensor depth

Chip surface

• laser pulse injected into different regions of the pixel

• IR laser 1 mm absorp. length• Beam size ≲10 µm• Charge= time integral of

induced current

E-TCT

Bojan Hiti (Ljubljana)

AMS H350

(20 𝝮∙cm)

CHARGE

• Charge collection width:

• Increases with fluence up to ≈ 2e15 n/cm2 due to initial acceptor removal

• Decreases with fluences above ≈ 2e15 n/cm2 but larger than before irradiation even at 1e16 n/cm2

2E15

1E16

1/25/2017

E-TCT results• Reactor neutrons, steps: 1e14, 5e14, 1e15, 2e15, 5e15,

8e15n/cm2


Scan along the sensor depth

Chip surface

• laser pulse injected into different regions of the pixel

• IR laser 1 mm absorp. length• Beamsize ≲10 µm• charge= time integral of

induced current

E-TCT

Bojan Hiti (Ljubljana)

LF (2 K𝝮∙cm)

A Charge Collection width of 35 µm (2,800 e-) can be achieved after

8e15 n/cm2

1/25/2017

CCPDv4 2016 beam test after irradiation


CERN SPS test beam, 180 GeV pions

Two n-irradiated AMS CCPDv4 samples: 1e15 n/cm2, 5e15 n/cm2, glued to FEI4 readout chip

DUT matrix 8 x 12 pixels (pitch of 100 µm x 125 µm) –edge pixels excluded

5e15 n/cm2–average efficiency 92.9 %1e15 n/cm2–average efficiency 99.6 %

1/25/2017

CCPD_LF prototypes• Signal spectra (sources and 3.2 GeV e- beam)

− 160μm depletion width @ 110V bias− Noise ~150 (100)e- for version A (B, low cap.)

• Time walk− Fraction of “in-time (25ns)” hits

• Low threshold : 79%• High threshold : 91%


55Fe

ENC=149e

Base line

ENC=136e

20V

10V

5V

Passive

sensors

DMAPS

Test

structures

CCPD_A

CCPD_B

6.2 ke i.e. ~86 μm

depl. depth

1/25/2017

CCPD_LF prototype• CCPD_LF_vA irradiated with neutrons to 1e15 n/cm2

• Spectrum of 55Fe and 241Am

• HV bias100 V (125 V) for irradiated (unirradiated) sample

• Monitor output of charge sensitive amplifier (CSA) in a single active pixel


55Fe

1015neq/cm2

Unirradiated

55Fe

1015neq/cm2

Unirradiated

241Am

1/25/2017

Tower Jazz 180nm Investigator


• Technology

− Deep P-well allows full CMOS in pixel

− Gate oxide 3 nm good for TID

− Epitaxial layer

• Thickness: 18 – 40 μm

• High resistivity: 1 – 8 kΩ.cm

• Reverse substrate bias

• Small collection NW in p-type epi to

minimize capacitance (2-5fF)

• Modified process to improve lateral

depletion and in particular charge collection

after irradiation

•

• Measurements on 25um EPI:− 50x50um pixel size

− 20x20um pixel size

1/25/2017

Tower Jazz 180nm Investigator• Neutron fluences: 1e14, 1e15, 1e16 (ongoing)

• 90Sr spectrum Monitor output of CSA


Clear signals observed after 1e15 irradiation with only a small reduction of amplitude.

Initial test beam results indicate no efficiency loss on pixel boundaries after 1e15 n/cm2.

H. Pernegger, C. Riegelet al.

1/25/2017

Monolithic DMAPS


• Many readout under consideration:− Column-drain

R/O logic (FE-I3 like)

− MU3E

1/25/2017

Scaling• The main issue is scaling

• How do we scale up from 0.25 mm2 sensors (Industry) to 1 hectare (HL-LHC, ILC Calorimetry, FCC) and meet all the requirements?


1/25/2017

Conclusion


PROMISING RESULTS:

ARE WE ON THE VERGE

OF A DCMOS

REVOLUTION?

1/25/2017

Available foundries


1/25/2017

Total Ionizing Dose


• Largest Noise increase after

few Mrad dose range

• AMS H180 irradiated to 60 MRad

LFoundry after 50 Mrad(X-ray, ≈ 60 keV)• 3 flavors of CSA

− Normal (L=0.9µm), Long (L=1.5µm) and Enclosed Layout Transistor

• Gain change about 20% for lower doses

• Noise Increase minimal for enclosed layout

Gain

Noise

1/25/2017

Passive CMOS• C4 bumps: come with chip fabrication at

low cost (saving x3)

• LFoundry 150 nm CMOS


AC- CoupledBias resistor

DC-Coupled Punch through bias

Bean test ELSA

1/25/2017

• TJ Investigator (similar technology to ALICE)− High resistivity: 1 – 8

kΩ·cm− Emphasis on small fill-

factor and small capacitance (< 5fF )

HV-CMOS radiation hardness

55Fe

FE-I4 telescope – SpS data 2016 (π+, 180 GeV) CCPDv4 irradiatedto 1015 neq/cm2

• AMS 180 nm− ρ = 10 Ωcm – 1 kΩcm

−Capacitive coupled to FEI4 (glue bonding)

• LFoundry 150 nm− 2kΩcm p-type bulk

CCPD_A

CCPD_B

passivesensor


1/25/2017

• TJ Investigator (similar technology to ALICE)− High resistivity: 1 – 8

kΩ·cm− Emphasis on small fill-

factor and small capacitance (< 5fF )

HV-CMOS radiation hardness

55Fe

FE-I4 telescope – SpS data 2016 (π+, 180 GeV) CCPDv4 irradiatedto 1015 neq/cm2

• AMS 180 nm− ρ = 10 Ωcm – 1 kΩcm

−Capacitive coupled to FEI4 (glue bonding)

• LFoundry 150 nm− 2kΩcm p-type bulk

CCPD_A

CCPD_B

passivesensor

PROMISING RESULTS

ARE WE ON THE VERGE OF A

CMOS REVOLUTION?


1/25/2017

MU3e• Main technological Challenges

− Large area O(1m2) monolithic pixel detectors with X/X0= 0.1% per layer

− Novel helium gas cooling concept− Thin scintillating fiber detector with ≤1mm thickness− Timing resolution 100-500 ps− Filter farm reconstructing and processing 108-109 tracks per

second

Comparator and readout in the periphery:• less digital

crosstalk• more space at

periphery needed• complex routing

of (analog) signals

MuPix7 Prototype (AMS 180)

Andre’ SchÖningD. Bortoletto IAS-HKUST 44

CSA

TH CMP READOUT

data

pixel

periphery

1/25/2017

SOI Monolithic Pixels• Transistors does not work with Detector High

Voltage (Back-Gate Effect)

• Circuit signal and sense node couples (Signal Cross Talk)

• Oxide trapped hole induced by radiation will shift transistor threshold voltage. (Radiation Tolerance)

• Single SOI Detector− Buried-Well shield back-gate potential

− Good for Integration-type sensor

− Relatively Low radiation applications

D. Bortoletto IAS-HKUST

Yasuo Arai

45

1/25/2017

SOI Monolithic Pixels• Transistors does not work with Detector High

Voltage (Back-Gate Effect)

• Circuit signal and sense node couples (Signal Cross Talk)

• Oxide trapped hole induced by radiation will shift transistor threshold voltage. (Radiation Tolerance)


Yasuo Arai

• Double SOI Detector− Middle Si layer shields coupling

between sensor and circuit.

− It also compensate E-field generated by radiation trapped hole.

− Good for Complex function and Counting-type sensor.

− Can be used in High radiation environment.

SOI Photon-Imaging Array Sensor (SOPHIAS)for X-ray Free Electron Laser (XFEL) SACLA XRPIX5: Event

Driven X-ray Astronomy Detector

SOFIST: SOI sensor for Fine measurement of Space and Time at ILC

46

1/25/2017

Double SOI

• With increasing Implantation dose of P lightly doped drain region 6 times higher than present value, the degradation is reduced from 80% to 20% at 112 kGy(Si).

• In the SOI process, it is possible to merge NMOS & PMOS Active region and share contacts.


SOI Photon-Imaging Array Sensor (SOPHIAS)for X-ray Free Electron Laser (XFEL) SACLA XRPIX5: Event

Driven X-ray Astronomy Detector

SOFIST: SOI sensor for Fine measurement of Space and Time at ILC

47

1/25/2017

CMOS


• CMOS complementary metal oxide semiconductor transistor (a type of field effect transistor, F. Wanlass

1963)

• First MOSFET was realized in 1959 Dawon Kahng and Martin M. Atalla.

48

Reza Mirhosseini

1/25/2017

Full CMOS MAPS• If PMOS transistors are introduced, signal loss can happen


1/25/2017

Charge Profile versus depletion voltage


AMS H350 (20 𝝮∙cm) FL (2 K𝝮∙cm)

• Measurements can be used to extract Neff

Acceptor

removalRadiation induced

acceptor

1/25/2017

AMS CHESS1 (20𝝮∙cm)


• 90Sr measurements

•Largest charge collection at 1-2e15n/cm2

1/25/2017

CCPDv4 2016 beam test• Timing performance on par with IBL modules in the telescope


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