Delays Models

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Verilog Day

Delay Models

Path Delays

VCD Files FSM Coding Styles

Synthesis Issues


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Types of delay models

Distributed delays:Assigning delay values to individual

elements

Lumped delays:single delay on the output gate of module

Pin to Pin delays:Assigned individually to paths i.e .,each

input to each output


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Distributed and lumped delays

Distributed delay

assign #2 x=a & b;

assign #5 y=c & d;

assign #10 z=x & y;

Lumped delays

assign x=a & b;

assign y=c & d;

assign #17 z=x & y;


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Pin to Pin delay

Specify block:Block in which path delay

are assigned

syntax

specify

assignments

.

endspecify


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Specify block

Within specify block path delays can be assigned in either

of the two statements

Parallel connection

( => )=Example : (a=> out)=5;

Full connection

(*> )=Example (a*> out) =5;


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Specify block

Parallel connection

Each bit in source field

connects tocorresponding bit indestination field

Full connection

Each bit in source field

connects to every bit indestination field


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Pin to Pin Delays


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Full connections


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Specparam

To declare parameters inside the specifyblockKeyword-specparam

Examplespecifyspecparam a=15;specparam b=10;(in1=>out)=a; (in2=>out)=b;

endspecify


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TimingChecks


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$setup Task

Setup checks can be specified with the systemtask $setup.

Syntax:

$setup(data_event, reference_event, limit) data_event: signal that is monitored for

violations.

reference_event: signal that establishes a

reference for monitoring the data_event signal. limit: minimum time required for setup of data

event.


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Violation is reported if(Treference_event-Tdata_event)< limit.

E.g. //setup check is set.

// clock is the reference.//data is begin checked for violations

// violation reported if Tposedge_clk-Tdata


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module set(d,q,clk);

input d,clk;

output q;reg q;

always@(posedge clk)

begin

q=d;end

specify

$setup(d,posedge clk,5);endspecify

endmodule


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Hold checks can be specified with the systemtask $hold.

Syntax:

$hold(reference_event, data_event,limit) data_event: signal that is monitored for

violations.

reference_event: signal that establishes a

reference for monitoring the data_event signal. limit: minimum time required for hold of data

event.


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Violation is reported if(Tdata_event-Treference_event)< limit.

E.g. //hold check is set.

// clock is the reference.//data is begin checked for violations

// violation reported if Tdata-Tposedge_clk


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module hold(d,q,clk);

input d,clk;

output q;

reg q;

always@(posedge clk)

begin

q=d;end

specify

$hold(posedge clk,d,5);endspecify

endmodule


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$pulse Width

The system task $width is used to checkthat the width of a pulse meets theminimum width requirement.

Syntax:

$width(reference_event,limit);

reference_event: edge trigger event(edgetransistion of a signal).

limit: minimum width of the pulse.


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The data event is not specified explicitlyfor width but is defined as the nextopposite edge of the reference_event

signal.

Thus, the width task checks the time b/wthe transition of a signal value to the next

opposite transition in the signal value.


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Violation is reported if(Tdata_event-Treference_event)< limit.

E.g. //width check is set.

// posedge of clear is the reference_event.// the next negedge of clear is the data_event.

// violation reported if Tdata-Tclk


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module width(d,q,clk);

input d,clk;

output q;

reg q;

specify

$width(posedge d,9);

endspecify

endmodule


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Delay BackAnnotation


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RTL LevelDescription

LogicSynthesis

Gate-LevelNetlist

Implementation

InitialPre-Layout

Delay Estimate

Delayvalue

Layout

Place andRoute

DelayCalculation

Back-annotation ofPost-layoutdelay

Post-layout

information


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Delay back annotation is an importantand vast topic in timing simulation

The various steps In the flow that use

back annotation are as follows1. The designer writes the RTL description

and then performs functional simulation.

2. The RTL description is converted to agate-level netlist by a logic synthesistool.


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3. The designer obtains pre-layout estimatorof delays in the chip by using a delaycalculator and information about the IC

fabrication process. Then the designerdoes timing simulation or static timingverification of the gate level netlist, using

these preliminary values to check thatthe gate level netlist meets timingconstraints.


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4. The gate level netlist is then converted to layoutby a place and route tool. The post-layout delayvalues are computed from the resistance and

capacitance information in the layout. The R andC information is extracted from factors such asgeometry and IC fabrication process.

5. The post-layout delay values are back

annotated to modify the delay estimates from thegate level netlist.


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Timing simulation or static timing.verification is run again on the gate levelnetlist to check if timing constraints are still

satisfied.6. If design changes are required to meet

the timing constraints, the designer has togo back to the RTL level, optimize thedesign for timing, and then repeat step2through step 5.

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