del Alamo AVS 2010 v4 · 2013. 4. 16. · InAs HEMTs (V CC GATE DEL = 0.5V) Si NMOSFETs iedm08 10...
Transcript of del Alamo AVS 2010 v4 · 2013. 4. 16. · InAs HEMTs (V CC GATE DEL = 0.5V) Si NMOSFETs iedm08 10...
III V CMOS:III-V CMOS: A sub-10 nm Electronics Technology?gy
J A del AlamoJ. A. del Alamo
Microsystems Technology Laboratories, MIT
AVS 57th International Symposium & ExhibitionOctober 17-22, 2010
Sponsors: Intel, FCRP-MSD
Acknowledgements:
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Dae-Hyun Kim, Donghyun Jin, Tae-Woo Kim, Niamh Waldron, Ling Xia, Dimitri Antoniadis, Robert Chau
MTL, NSL, SEBL
Outline
• Why III-Vs for CMOS?
• Lessons from III-V HEMTs
• The challenges for III-V CMOS
• The prospects of 10 nm III-V CMOS
• Conclusions
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The Si CMOS Revolution: Smaller is Better!• Virtuous cycle of CMOS scaling exponential improvements in:– Transistor density (“Moore’s law”)– Performance – Power efficiencyPower efficiency
Intel microprocessors Intel microprocessors
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Recent trend in CMOS scaling
• Si CMOS has entered era of “power-constrained scaling”:– CPU power density saturated at ~100 W/cm2
– CPU clock speed saturated at ~ 4 GHz
Pop, Nano Res 2010 http://www.chem.utoronto.ca/~nlipkowi/pictures/clockspeeds.gif
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Consequences of Power Constrained Scalingo e Co st a ed Sca g
P ti + iPower = active power + passive power
PA~ f CVDD2N N ↑ VDD ↓
#1 goal!clock frequency
transistor capacitance
operating voltageoperating voltage
transistor count
Transistor scaling requires reduction in supply voltage5
CMOS power supply scaling
Recently, VDD scaling very weakly:
Because Si performance degrades as VDD↓:weakly: degrades as VDD↓:
40 nm strained-Si MOSFET (Intel)
Dewey, IEDM 2009
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Need scaling approach that allows VDD reduction while enhancing performance
How III-Vs allow further VDD reduction?
• Goals of scaling: – Reduce transistor footprint – extract maximum ION
for given IOFF
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How III-Vs allow further VDD reduction?
• Goals of scaling: – Reduce transistor footprint – extract maximum ION
for given IOFF
• III-Vs:
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– higher electron velocity than Si ION ↑ – very tight carrier confinement S ↓ sharp turn on
III-V High Electron Mobility Transistors ob ty a s sto s• State-of-the-art: InAs-channel HEMT
- QW channel (tch = 10 nm) :- InAs core (t = 5 nm)- InAs core (tInAs = 5 nm)
- InGaAs cladding
- n Hall = 13,200 cm2/V-secn,Hall 13,200 cm /V sec
- InAlAs barrier (tins = 4 nm)
- Pt/Ti/Mo/Au Schottky gate
9999
Pt/Ti/Mo/Au Schottky gate- Lg=30 nm
Kim, IEDM 2008
III-V HEMTs
0.8
• Lg=30 nm InAs-channel HEMT Kim, IEDM 2008
2.0
0.6
V 0 4 Vm]
VGS = 0.5 V1.5
0.4
VGS = 0.4 V
I D [m
A/
m
1.0
g m [m
S/m
]0 0 0 2 0 4 0 6 0 8
0.0
0.2
-0 2 0 0 0 2 0 40.0
0.5
VDS = 0.5 V
0.0 0.2 0.4 0.6 0.8VDS [V]
• Large current drive: ION=0.4 mA/µm at VDD=0.5 V
0.2 0.0 0.2 0.4
VGS - VT [V]
101010
• Enhancement-mode FET: VT = 0.08 V• High transconductance: gmpk= 1.8 mS/um at VDD=0.5 V
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III-V HEMTs
• Lg=30 nm InAs-channel HEMT
Kim, IEDM 2008
10-4
10-3
ID 40
50
dB] H21
10-6
10-5
IG
V = 0 5 VI G [A
/m
]
20
30
Ug,
MA
G [d
Ug
MAG
fT=601 GHzfmax=609 GHz
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10-8
10-7 VDS = 0.5 V
I D, I
VDS = 0.05 V10
H21
, MAG
VDS = 0.5 V, VGS = 0.3 V
-0.50 -0.25 0.00 0.25 0.5010-9
VGS [V]109 1010 1011 1012
0
Frequency [GHz]
DS , GS
111111
• S = 73 mV/dec, Ion/Ioff=~104
• First transistor with both fT and fmax > 600 GHz11
Scaling of III-V HEMTs: Benchmarking with Si
180Si FETs (IEDM)T i l IEDM 07
180Si FETs (IEDM)T i l IEDM 07
180Si FETs (IEDM)*
180Si FETs (IEDM)*
e c a g t S10
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ng [m
V/de
c.] Triple recess: IEDM 07
Pt sinking
140
160
ng [m
V/de
c.] Triple recess: IEDM 07
Pt sinking
140
160
ng [m
V/de
c.] Pt sinking: IEDM 08
140
160
ng [m
V/de
c.] Pt sinking: IEDM 08
1iedm07
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[pse
c]
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shol
dsw
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InAs HEMTs(VCC = 0.5V)
GA
TE D
ELA
Si NMOSFETsiedm08
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Subt
Gate Length [nm]10 100
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Gate Length [nm]10 100
60
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Gate Length [nm]10 100
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Subt
Gate Length [nm]
iedm07iedm08100 101 102
0.1
Gate Length, Lg [nm]
Si NMOSFETs(VCC = 1.1~1.3V) VDD=0.5 V
• Superior short-channel effects as compared to Si MOSFETs
g
MOSFETs• Lower gate delay than Si MOSFETs at lower VDD
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Scaling of III-V HEMTs: Benchmarking with Si
• FOM that integrates short-channel effects and drive current: ION @ IOFF=100 nA/µm, VDD=0.5 V
e c a g t S
(scaled to VDD=0.5 V)
III-V HEMTs: higher ION for same IOFF than Si13
Lessons from III-V HEMTs
1. Very high electron injection velocity at the virtual source
Evinj
Kim, IEDM 2009
EC
njL0 x
vinj ≡ electron injection
v inj
j
velocity at virtual source
(I G A ) i ith I A f ti i h l• vinj(InGaAs) increases with InAs fraction in channel• vinj(InGaAs) > 2vinj(Si) at less than half VDD
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Lessons from III-V HEMTs2. Quantum-well channel key to outstanding short-channel
effectsKim IPRM 2010Kim, IPRM 2010
D ti i t i h t h l ff t i thi• Dramatic improvement in short-channel effects in thin channel devices
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Lessons from III-V HEMTs3. Quantum capacitance less of a bottleneck than
commonly believedInAs channel: t = 10 nmInAs channel: tch = 10 nm
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Experiment (CG)
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30
nce
[fF/
m2 ] Cins ( tins = 4 nm)
CQ1 (m||* = 0.026me )
10Cap
acita
n Ccent1
CG (m||* = 0.026me )
CG ( 0.07 ) CG ( 0.05 )
-0.4 -0.2 0 0.2 0.40
VG [V]
G ( || e )
Biaxial strain + non-parabolicity + strong quantization increase m||
* CG↑ Jin, IEDM 2009 16
Limit to III-V HEMT Scaling: Gate Leakage Current
10-3
tins
= 10 nmt = 7 nm
Gate ea age Cu e t
InAs HEMTL = 30 nm
10-5
10-4
]
tins = 7 nm t
ins = 4 nm ID
Lg = 30 nmtch = 10 nm
4
10-7
10-6
D, I G
[A/
m]
IG
tins=4 nm
tins=7 nm
10-9
10-8
VDS
= 0.5 V
I D tins 7 nm
tins=10 nm
-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.5010-10
DS
VGS [V]
t ↓ I ↑
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tins ↓ IG↑ Further scaling requires high-K gate dielectric
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The Challenges for III-V CMOS: III-V HEMT vs Si CMOSIII-V HEMT vs. Si CMOS
Intel’s 45 nm CMOSIII-V HEMT
• Schottky gate MOS gate Critical issues:• Footprint scaling [1000x too big!] • Need self-aligned contacts
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• Need p-channel device• Need III-V on Si
III-V’s on Si
• The challenge: – III-V heterostructures on large-area Si wafers– Thin buffer layer– Low defectivity
• Some notable work:Some notable work:
GXOI InAs MOSFET
Si
SiO2
InAsG
S D
Aspect Ratio Trapping InAs Nanoribbon MOSFETs
Si
Direct III-V MBE on Si Aspect Ratio Trapping (Amberwave)
Wu, APL 200819
InAs Nanoribbon MOSFETs on Insulator (UCB)
Ko, Nature 2010
Direct III V MBE on Si (Intel)
Hudait, IEDM 2007
The gate stack• Challenge: metal/high-K oxide gate stack
– Fabricated through ex-situ processThin EOT (<1 nm)– Thin EOT (<1 nm)
– Low leakage (<10 A/cm2)– Low Dit (<1011 eV-1.cm-2 in top ~0.3 eV of bandgap)– Reliable
• Some notable work:
Al O by ALDAl O /GGO on InGaAs by TaSiO on InGaAs by ALDAl2O3 by ALD (Purdue)
Wu, EDL 2009
Al2O3 /GGO on InGaAs by MBE/ALD (Tsinghua)
Hong, MRS Bull 200920
TaSiOx on InGaAs by ALD (Intel)
Radosavljevic, IEDM 2009
In0.7Ga0.3As Quantum-Well MOSFET (Intel)
• Direct MBE on Si substrate (1.5 µm buffer thickness)• InGaAs buried-channel MOSFET (under 2 nm InP etch stop)
S O / /• 4 nm TaSiOx gate dielectric by ALD, TiN/Pt/Au gate• Lg=75 nm
21Radosavljevic, IEDM 2009
In0.7Ga0.3As Quantum-Well MOSFET
2009 Intel InGaAs MOSFET(scaled to
VDD=0.5 V)
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Self-aligned device architecture
• The challenge: – MOSFET structures with scalability to 10 nm– Self-aligned gate design
• Some notable work:
G
In-situ Doped S/D for RSReduction
In0.53Ga0.47As
InP
In0.4Ga0.6Asx
y Channel Strain Engineeringfor Mobility
60 nm
Ion-implanted self-aligned Regrown ohmic contact Quantum-well FET with self-
Enhancement
p gInGaAs MOSFET (NUS)
Lin, IEDM 2008
gMOSFET (NUS)
Chin, EDL 2009
aligned W contacts (MIT)
Waldron, TED 201023
P-channel MOSFETs
• The challenge: – Performance >1/3 that of n-MOSFETs– Capable of scaling to <10 nm gate length regime– Co-integration with III-V NMOSFET on Si
• Some notable work:
Al O /InGaSb QWGa O /AlGaAs/GaAs Al O by ALD on InGaAsAl2O3/InGaSb QW-MOSFET (Stanford)
Nainani, IEDM 2010 24
Ga2O3/AlGaAs/GaAsMOSFET (Motorola)
Passlack, EDL 2002
Al2O3 by ALD on InGaAs and Ge MOSFETs (IMEC)
Lin, IEDM 2009
What can we expect from10 nm III V NMOS at 0 5 V?~10 nm III-V NMOS at 0.5 V?
With thin InAs channel:
Assume RS as in Si (~80 Ω.µm):
K i tThree greatest worries!
S
ID=1.5 mA/µm
Key requirements:• High-K/III-V interface, thin channel do not degrade vinj
• Obtaining R =80 Ω µm at required footprint
worries!
• Obtaining Rs=80 Ω.µm at required footprint• Acceptable short-channel effects
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Conclusions• III-Vs attractive for CMOS: key for low VDD operation
– Electron injection velocity in InAs > 2X that of Si at 1/2X VDD
Quantum well channel yields outstanding short channel effects– Quantum well channel yields outstanding short-channel effects– Quantum capacitance less of a limitation than previously believed
• Impressive recent progress on III-V CMOS – Ex-situ ALD and MOCVD on InGaAs yield interfaces with unpinned
Fermi level and low defect densityFermi level and low defect density– Sub-100 nm InGaAs MOSFETs with ION > than Si at 0.5 V
demonstrated
• Lots of work ahead:– Demonstrate 10 nm III-V MOSFET that is better than Si
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– P-channel MOSFET– Manufacturability, reliability