ELAN Microelectronics Corp. ELAN Microelectronics Corporation
Defense MicroElectronics Activity
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Defense MicroElectronics Activity VE00.06.01 The Impact of System Level Design on the DMS World Keith Bergevin Senior Design Engineer 4234 54th St., Bldg. 620 Sacramento, CA. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231- 2818 email: [email protected]
description
Defense MicroElectronics Activity. The Impact of System Level Design on the DMS World. Keith Bergevin Senior Design Engineer 4234 54th St., Bldg. 620 Sacramento, CA. 95652-1521 Phone: (916) 231-1652, Fax: (916) 231- 2818 email: [email protected]. VE00.06.01. - PowerPoint PPT Presentation
Transcript of Defense MicroElectronics Activity
DefenseMicroElectronics
Activity
DefenseMicroElectronics
Activity
VE00.06.01VE00.06.01
The Impact of System Level Design on the DMS
World
The Impact of System Level Design on the DMS
World
Keith BergevinSenior Design Engineer4234 54th St., Bldg. 620Sacramento, CA. 95652-1521Phone: (916) 231-1652, Fax: (916) 231- 2818email: [email protected]
Keith BergevinSenior Design Engineer4234 54th St., Bldg. 620Sacramento, CA. 95652-1521Phone: (916) 231-1652, Fax: (916) 231- 2818email: [email protected]
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Background: DesignMethodologies – What’s Next?
Background: DesignMethodologies – What’s Next?
Pencil, Paper, Drafting Table
Quest for Computer Entry of Schematics
Schematic Capture
Quest for Faster, More Efficient Hardware Design Methods
Hardware Description Languages
Quest for Faster, More Efficient Design of Entire Systems
Pencil, Paper, Drafting Table
Quest for Computer Entry of Schematics
Schematic Capture
Quest for Faster, More Efficient Hardware Design Methods
Hardware Description Languages
Quest for Faster, More Efficient Design of Entire Systems
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Briefing RoadmapBriefing Roadmap
What is System Level Design?
Benefits of System Level Design
Overview of Evolving System Level Design Languages
Impact of SLD on the DMS Community
DMEA’s Role in SLD
What is System Level Design?
Benefits of System Level Design
Overview of Evolving System Level Design Languages
Impact of SLD on the DMS Community
DMEA’s Role in SLD
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What is System Level Design?What is System Level Design?
Today’s Systems Comprised of Multiple High-Density Components Processors, RAM, ROM, I/O, ASICs, etc. Each Component Separately Modeled, Simulated, & Designed Various Methods used to Integrate Components into a System
System Level Design One Specification to Model, Simulate, Synthesize all Functions All Functions Integrated onto a Single Device called System-on-a-Chip (SoC)
Today’s Systems Comprised of Multiple High-Density Components Processors, RAM, ROM, I/O, ASICs, etc. Each Component Separately Modeled, Simulated, & Designed Various Methods used to Integrate Components into a System
System Level Design One Specification to Model, Simulate, Synthesize all Functions All Functions Integrated onto a Single Device called System-on-a-Chip (SoC)
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The Benefits of System Level Design (SLD)
The Benefits of System Level Design (SLD)
Modeling of Entire System on a Chip (SoC) with a Single,
Executable Specification
Hardware/Software Verification at an Earlier Stage
Concurrent H/W & S/W Design & Verification
Eliminate Intercommunication Translation Process
Traditionally, H/W Designed with VHDL or Verilog
S/W Designed with C/C++, Java, etc.
Large Overhead Incurred in Passing Data
Modeling of Entire System on a Chip (SoC) with a Single,
Executable Specification
Hardware/Software Verification at an Earlier Stage
Concurrent H/W & S/W Design & Verification
Eliminate Intercommunication Translation Process
Traditionally, H/W Designed with VHDL or Verilog
S/W Designed with C/C++, Java, etc.
Large Overhead Incurred in Passing Data
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Leading System Level Design Languages
Leading System Level Design Languages
SystemC
Started with Technical Agreement and Development by Synopsys
Inc., CoWare Inc., and Frontier Design Inc.
Extends C/C++ Language to Hardware and System Design
Freely Available through Open Source Licensing
Administered by Open SystemC Initiative (OSCI) Steering Group
SystemC
Started with Technical Agreement and Development by Synopsys
Inc., CoWare Inc., and Frontier Design Inc.
Extends C/C++ Language to Hardware and System Design
Freely Available through Open Source Licensing
Administered by Open SystemC Initiative (OSCI) Steering Group
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Leading System Level Design Languages
Leading System Level Design Languages
SystemC Primary Advantages:
Large Base of C/C++ Programmers
C/C++ Widely used to Model & Simulate Hardware
SystemC Primary Disadvantages:
Minimal Tools for Synthesis at this Time
C Language does not Support Notion of Time, Concurrency,
Hardware Data Types, etc.
SystemC Primary Advantages:
Large Base of C/C++ Programmers
C/C++ Widely used to Model & Simulate Hardware
SystemC Primary Disadvantages:
Minimal Tools for Synthesis at this Time
C Language does not Support Notion of Time, Concurrency,
Hardware Data Types, etc.
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Leading System Level Design Languages
Leading System Level Design Languages
Superlog
Superset of Verilog, with Addition of C Programming, System,
& Verification Capabilities
Superlog Advantages
Large Base of Verilog Hardware Designers
Mature Synthesis Tools Available
Superlog Disadvantages
Requires Extensions to Achieve System Level Capabilities
Superlog
Superset of Verilog, with Addition of C Programming, System,
& Verification Capabilities
Superlog Advantages
Large Base of Verilog Hardware Designers
Mature Synthesis Tools Available
Superlog Disadvantages
Requires Extensions to Achieve System Level Capabilities
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Leading System Level Design Languages
Leading System Level Design Languages
CynApps
Developed by CynApps Inc. Founded 1998
C++ with Addition of Hardware Concurrency and Bit
Accurate Data Types
CynApps Advantages
C++ Based
Models Hardware at All Levels of Abstraction
CynApps Disadvantages
Requires Translation to Verilog For Synthesis
CynApps
Developed by CynApps Inc. Founded 1998
C++ with Addition of Hardware Concurrency and Bit
Accurate Data Types
CynApps Advantages
C++ Based
Models Hardware at All Levels of Abstraction
CynApps Disadvantages
Requires Translation to Verilog For Synthesis
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Impact of SLD from a DMS Standpoint
Impact of SLD from a DMS Standpoint
System-on-a-Chip (SoC) Design Magnifies Many DMS-Type Problems Currently Associated with ASIC Devices:
Replace with Alternate Source? No. Custom Designs Virtually Ensure No Second Source Available
Re-Target? Difficult. The First Generation of SoCs May Contain Combination of
VHDL, Verilog, and one or more of the SLD Languages.
Reverse Engineer? Extremely Difficult.
System-on-a-Chip (SoC) Design Magnifies Many DMS-Type Problems Currently Associated with ASIC Devices:
Replace with Alternate Source? No. Custom Designs Virtually Ensure No Second Source Available
Re-Target? Difficult. The First Generation of SoCs May Contain Combination of
VHDL, Verilog, and one or more of the SLD Languages.
Reverse Engineer? Extremely Difficult.
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DMEA’s Role in System Level Design and SoC Technology
DMEA’s Role in System Level Design and SoC Technology
Retain Step-for-Step Expertise in SoC with Industry Imperative to Understand the Technology in Order to Develop DMS
Solutions Necessary to Understand SoC Technology in Order to Develop
Guidelines for SoC Contractual Specifications Continue to Strengthen Expertise in IP Core Design
Virtually all SoCs are Built via Integration of IP Cores IP Core Re-Targeting is one of the few Cost-Effective Techniques
Available DMEA Flexible Foundry Provides Long-Term Support
Ensures Future Component Availability
Retain Step-for-Step Expertise in SoC with Industry Imperative to Understand the Technology in Order to Develop DMS
Solutions Necessary to Understand SoC Technology in Order to Develop
Guidelines for SoC Contractual Specifications Continue to Strengthen Expertise in IP Core Design
Virtually all SoCs are Built via Integration of IP Cores IP Core Re-Targeting is one of the few Cost-Effective Techniques
Available DMEA Flexible Foundry Provides Long-Term Support
Ensures Future Component Availability
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SummarySummary
Technology Trends Higher Density Custom Designs (SoCs) New Generation of Hardware Description Languages
From a DMS Standpoint: No Easy Solutions Sole Source Components Difficult to Reverse Engineer May be Difficult to Re-Target (Multiple Data Formats)
DMEA’s Approach to Mitigate Next Generation DMS Problems Maintain State-of-the-Art Technical Skills Continue Development of Cost-Effective Core Retargeting Target Flexible Foundry Devices
Technology Trends Higher Density Custom Designs (SoCs) New Generation of Hardware Description Languages
From a DMS Standpoint: No Easy Solutions Sole Source Components Difficult to Reverse Engineer May be Difficult to Re-Target (Multiple Data Formats)
DMEA’s Approach to Mitigate Next Generation DMS Problems Maintain State-of-the-Art Technical Skills Continue Development of Cost-Effective Core Retargeting Target Flexible Foundry Devices
