Decoupling capacitor placement

Covered in this topic: • Which locations need decoupling caps? • IC decoupling • Capacitor lumped model • How to maximize the effectiveness of a decoupling cap • Parallel resonance in adjacent capacitors • Sample decoupling capacitor placements • Global decoupling benefits

Introduction

Which circuit locations need decoupling caps?

Decoupling can be used in several ways such as: 1. A process of separating one circuit from affecting the other circuit 2. A method of filtering power supply and digital noise 3. A way of providing a local energy bank that is large enough to maintain the supply

level within the operating voltage level of any ICs or circuits during transient scenarios

From the above definitions, it is now easy to determine which circuits need decoupling

capacitors!

Power supply decoupling

o The purpose of C1 in below circuit is to make the current loop area small so that the radiated and conducted emissions are minimized.

Q1 and D1 are noisy devices with high di/dt. C1 decouples the harmonic content from other circuits and at the same time minimizes the radiation loop

area that can cause EMI issues.

High di/dt

High di/dt

Decouple noise to ground

GND

VCC

LDO

Single event decoupling

• In this circuit, C1 is a decoupling capacitor who’s purpose it is to prevent the IC over voltage protection from false trigger during surge testing.

• In the earlier version of the design, this IC triggers due to transient on the OVP feature during common mode surge test.

• Surge testing is part of immunity test for power supplies. A voltage as high as 2kV-4kV is injected in the AC line for a short duration of time (in the order of microseconds).

• During this testing, sensitive devices can be affected and there is a need for decoupling capacitors.

• After installing C1 and a series resistor, the false trigger issue was cured.

Every IC Power and ground pin needs a decap

• It is good practice to provide at least one decoupling capacitor for every power and ground pin of an IC.

• MCU, DSC, DSP or any ICs require supply

rails to be stable within operating voltage range.

• Decoupling capacitors will also bypass any unwanted high frequency noise riding on the supply lines to the ground.

GND

VCC

VCC

GND VCC

GND

VCC

GND

VCC

VCC

GND

GND

Which circuit locations need decoupling caps?

To limit noise propagation and minimize current loops: √ Power supply inputs √ Power supply outputs √ Every IC PWR/GND pin pair √ Sprinkled over PCB with on X*Y grid √ Signals just before they go onto external cabling √ Power rails just before they go onto external cabling √ Signals and power rails that are connected to other PCBs via cabling √ Anywhere that you need to decouple noise

This is a real decoupling

network

ESR

ESL

Ideal cap

PCB trace resistance

Comparing Ideal and Real Decoupling Network

This is an ideal decoupling

network

PCB trace inductance

Ideal Decoupling Real Decoupling

Impe

danc

e

Frequency

Resonant frequency

Below resonance Above resonance

Widen the low impedance band

• Based from the impedance plot on the left, at frequencies below the series resonance the dominating factor is the capacitance. The impedance is inversely proportional to the capacitance. At frequencies above resonance, the dominating factor is the inductance wherein the impedance is directly proportional to it. The lowest impedance is obtain at the resonance frequency wherein it is only dictated by the ESR.

Effect of parasitic inductance on decoupling effecitveness

Data properties • 30pF load • 2ns rise time • 3v3

I = C (dV/dt) Current: • 49.5mA per data line • 792mA for 16 bit bus (max)

Capacitance: • 3v3 tolerance = 10% = 0.33V • Select max droop = 50mV • C = 32nF

C = I (dt/dV)

V = L (dI/dt)

Voltage glitch • 1.5 nH series parasitic inductance • 792 mA peak • 2ns rise time • = 594 mV

Impe

danc

e

Frequency

Resonant frequency

Below resonance Above resonance

Parallel capacitor effect on resonance

Total inductance decreases with parallel

caps. Impedance decreases

Total capacitance increase with parallel

caps. Impedance decreases

Total ESR decrease with parallel caps

Two capacitors in parallel

Widen the low impedance band

Zeff (Ω)

Freq (MHz) 0.

1

0.3 1 3 10

30

300

1000

Decoupling caps in parallel (Same value)

Zeff (Ω)

Freq (MHz) 0.

1

0.3 1 3 10

30

300

1000

Decoupling caps in parallel (Different values)

1 x 100nF

10 x 100nF

1 x 1nF

1 x 10nF

1 x 100nF

Overall Impedance

Optimal bypass routing

GND

VCC

(1)

GND

VCC

(2)

GND

VCC

(3)

GND

VCC

(4)

GND

VCC

Optional Ferrite

GND

GND

VCC

(6)

GND

VCC

(7)

GND

VCC

(5)

Decaps placement below high pin count ICs

• Often no room on top layer • Sometimes the minimum parasitic inductance is to place the decoupling caps directly below the IC • Caps are placed between breakout vias • Track inductance replaced with via inductance (use Saturn PCB calculator to figure out via inductance)

d

h

Top Layer

Ground Plane

Power Plane

Capacitor

Parallel bypass routing

VCC

GND

Option 2

~5nH ~0.5nH

GND

VCC 10

0nF

Option 1

100n

F

100n

F

Power supply decoupling for minimium emissions

Decoupling capacitors

Wrong placement. Large

current loop!

Much better placement. Smaller

current loop!

Global decoupling

• Global decoupling differs with the local decoupling because it is not intended to decouple a particular IC pin.

1. Helps to keep PDN impedance low over large area due to parallel ESL (effective <400 MHz)

2. Add distributed capactiance to decouple stray currents (accidental loops) 3. Keep same values recommended to avoid resonances

EMSCAN - detect current distribution on a PCB

Summary

What we’ve covered: • Which locations need decoupling caps? • How to maximize the effectiveness of a decoupling cap • Parallel resonance in adjacent capacitors • Sample decoupling capacitor placements • Optimal via locations • Decoupling for high density BGA devices • Global decoupling benefits