i

DECLARATION OF ORIGINALITY

NAME OF STUDENT MIINGI ANDREW MWENJA

REGISTRATION NUMBER F17/7859/2001

COLLEGE ARCHITECTURE AND ENGINEERING

DEPARTMENT ELECTRICAL AND INFORMATION

ENGINEERING

COURSE NAME BACHELOR OF SCIENCE IN ELECTRICAL

AND ELECTRONIC ENGINEERING

TITLE OF WORK DESIGN OF A TWO STAGE CMOS OP AMP

1. I understand what plagiarism is and I am aware of the University policy in this

regard

2. I declare that this final year project report is my original work and has not been

submitted elsewhere for examination, award of degree or publication where other

people’s work, or my own work has been used, this has properly been

acknowledged and referenced in accordance to the University of Nairobi

requirements

3. I have not sought or used the services of any professional agencies to produce this

work

4. I have not allowed, and shall not allow anyone to copy my work with the intention

of passing his/her work.

5. I understand that any false claim in respect of this work shall result in

disciplinary action; in accordance with university anti-plagiarism policy.

Signature:……………………….. Date:………………………..

ii

CERTIFICATION

This project report has been submitted for examination to the Department of Electrical

and Information Engineering, University of Nairobi with my approval as the supervisor

Professor Elijah Mwangi

Department of Electrical and Information Engineering

Signature:……………………….. Date:………………………..

iii

DEDICATION

I would like to dedicate this project to my family who have been very caring and

supportive. I also dedicate this to all those who have encouraged and supported me while

undertaking this course.

iv

ACKNOWLEDGEMENT

I express my gratitude to my supervisor, Prof. Elijah Mwangi for guiding me especially

on text book research.

I also take this opportunity to thank my classmates and friends for all their academic and

moral support.

I finally thank my parents, Dr. John Stephen Miingi and Mrs. Magdalene Muchoki

Miingi for constant financial support throughout my education.

v

ABSTRACT

A two stage CMOS OP AMP has been designed with 0.5m technology using p-mos

and n-mos transistors. The op amp has a loop gain of 85.02 dB and gain bandwidth

product of IMHZ.

The project is made up of hand calculations for width to length ratios.

vi

LIST OF ABBREVIATIONS

1. OP AMP – Operational amplifier

2. CMOS- Complementary metal oxide semiconductor

3. dB- D

4. G- Gate

5. D- Drain

6. S-Source

7. K’ – process transconductance parameter

8. W- Transistor width

9. L- Transistor length

10. Cox- Capacitance per unit gate area

11. U- election or hole mobility

1

CHAPTER ONE: INTRODUCTION

1.1. BACKGROUND

Op amps have been in use for a long time primarily on analog computation and

sophisticated instrumentation. It may contain large number of transistors on the same

silicon chip. They have high input impedance, do not amplify noise, are cheap. It is quite

easy to design circuits using the IC opamp.

It may contain one or more differential stages. The topology of the cmos opam is

discussed using 0.5μm technology.

Figure 1.1 a,b,c show various ways of using an op amp

Figure 1.1a : The non-inverting configuration

2

Figure 1.b: The inverting configuration

Figure 1.1c: The unity gain buffer or voltage follower

1.2 OBJECTIVES

1.2.1 OVERALL OBJECTIVE

To design a two stage cmos opamp with gain bandwith product of 1MHZ, a view rate of

IV/μsec and CMRR of at least 60 . It should operate at low voltage of the ±3V range.

1.2.2 SPECIFIC OBJECTIVES

Design consists of mathematical calculations

1.3 PROJECT SCOPE

The project aims at coming up with a design of a two stage cmos opam such that

mathematical calculations followed by a simulation using pspice lead us to check if we

meet specifications.

3

1.4 JUSTIFICATION OF STUDY

Op amp circuits are used in computation, instrumentation and other application, they are

popular due to cheap cost as a building block of modern electronic circuits.

1.5 ORGANIZATION OF REPORT

Chapters in the report are as follows: Chapter 1 is the introduction of the project and

general organization. Chapter 2 contains the literate review. Chapter 3 contains design

and analysis.

4

CHAPTER TWO: LITERATURE REVIEW

2.0 ENHANCEMENT TYPE MOSFET

The enhancement type MOSFET (Metal-Oxide-Semiconductor-field Effect transistor is a

type of Field Effect Transistor (FET) where current is cut off until the input voltage

between its input terminals reaches a specific magnitude. The input voltage is actually

reverse biased with no direct contact between the input gate and the conducting channel,

with only the charge accumulated controlling the current flow. This is due to insulation at

its input. Current is conducted by only type of carrier – elections or holes. The fact that

an input voltage can control its output current without direct contact makes Field Effect

Transistors very popular. In fact the E-MOSFET (Enhancement type MOSFET) is the

most widely used FET.

Figure 2.1: nmos

The construction of the n-channel enhancement – type MOSFET is provided in figure

2.1/ a slab of p-type material is formed from a silicon base. This slab is at times called the

substance or body. The substrate at times can be connected to the source. The drain and

5

source are two heavily doped regions created in the substrate. A thin layer of silicon

dioxide – an insulator is grown on the body. Finally metal is deposited on the SiO2

(silicon dioxide) layer to form the gate metallic platform from the region between the

drain and source. Between the metallic contacts and the body is the p-type substrate.

2.1.1 OPERATION WITH VGS = OV

With no bias voltage applied to the gate, two back to back diodes exist in series between

the drain and source. One diode is formed by the pn junction between the n+ (heavily

doped) drain region and the p-type substrate, and the other diode is formed by the pn

function between the p-type substrate and the n+ source region (also heavily doped).

They prevent current conduction from the drain to source when a voltage VDS is applied.

A very high resistance in the order of 1012Ω exists between both drain and source.

2.1.2 OPERATION WITH VGS>OV

Grounding the source and the drain and applying positive VGS causes free holes to be

repelled from the substance under the gate. These holes are pushed downwards into the

substrate leaving behind a camer-depletion region. The positive gate voltage attracts

electrons from the n+ source and drain regions into the channel region. This effectively is

connecting the drain and source region. This is shown in figure 2.2.

6

Figure 2.2 : VGS> 0, VGS = 0

2.1.3 OPERATION WITH VDS>OV, VGS>OV (Small VDs)

With VDs at a small value (say 50mv), the voltage VDs causes current in to flow through

the induced n channel from drain to source.

For a VG = Vt the channel is just induced and the current conducted is still negligibly

small. As VGS is increased beyond Vt (thresholds) more electrons are attracted into the

channel. The conductance of the channel is proportional to the “excess gate voltage” VGS

– Vt, or “effective voltage” or “overdrive voltage.”

2.1.4 OPERATION WITH VDS INCREASED

As VDS increased we note that as we travel along the channel from source to drain the

voltage increases from 0 to VDs. Hence it is tapered and is narrowest at drain end

implying varying resistance.

7

Figure 2.3 : VDS varied

When VDs is increased to the value that reduces the voltage between the gate and drain

end to Vt; that is VGD=Vt or VGS-VDS=Vt, or VDS=VGS – Vt the channel depth at the drain

end decreases to almost zero, and the channel is said to be “pinched off” and increasing

VDS beyond this value has little effect on channel width. Current remains constant at the

value reached for VDS = VGS – Vt. And the drain current ‘saturates’ at this value – the

saturation region has been reached. The voltage at which this occurs is

VDssat=VDs – Vt (2.1.4)

The region of the iD – VDs characteristics obtained for VDs<VDSsat is called the triode

region.

8

Figure 2.4 : Saturation and triode regions

2.1.5 THE iD – VDSCHARACTERISTICS

The device is cut off when VGS<Vt. To operate the MOSFET in the trade region we

must first induce a channel.

VGS≥Vt (induced channel)

Then we keep VDS small enough so that the channel remain continuous. This is achieved

by ensuring that the gate-to drain voltage is

VGD>Vt (continuous channel)

Since

VGD = VGS + VSD = VGS – VDS, thus

VGS – VDS> Vt

9

Or

VDS< VGS – Vt (continuous channel)

Thus the enhancement type MOSFET operates in the triode region when VGS is greater

than Vt and the drain voltage is lower than the gate voltage by atleast Vt volts.

In the triode region

= ( − ) − (2.1.5)

Where

= ′and K’ is the process transconductance parameter

=== ℎ== ℎ ℎ , = ℎ ℎ

To operate the transistor in the saturation region, a channel must be induced.

≥ ( ℎ )and pinched off at the drain end by raising VPS to a value that results in the gate-to-drain

voltage galling below Vt.

10

≤ ( ℎ ℎOr

≥ − ( ℎ ℎThus the n channel enhancement type MOSFET operates in the saturation region when

VGS is greater than Vt and the drain voltage does not fall below the gate voltage by more

than Vt volts. Therefore

= 12With the depletion layer widening the channel length is in effect reduced, a phenomenon

known as channel length modulation

= ( − ) (1 +Where

== ℎ ℎ

ℎ ℎThe channel length modulation makes the output resistance in saturation finite.

ɤ =

11

Or

ɤ = 2 ( − )Thus

ɤ = 1Or

ɤ =Where VA is the early voltage

2.1.6 N-CHANNEL MOSFET CIRCUIT SYMBOL

Fig. 2.5(a) Fig. 2.5(b) Fig. 2.5(c)

N-CHANNEL CIRCUIT SYMBOLS

Figure 2.5

a) Circuit symbol for the n-channel enhancement type MOSFET

12

b) Modified circuit symbol with an arrowhead on the source terminal to distinguish

it from the drain and to indicate device polarity (n-channel)

c) Simplified circuit symbol to be used when the source is connected to the body or

when the effect of the body on device operation is unimportant.

2.2. P-CHANNEL MOSFET (P-MOS)

The circuit symbol for the p-channel enhancement type MOSFET is shown in figure 2.6

(a), (b), (c). For the PMOS, Vt is negative, to induce a channel we apply a fate voltage

that is more negative than Vt, also VDS is negative. The current ID enters the source

terminal and leaves through the drain terminal.

Fig. 2.6(a) Fig. 2.6(b) Fig. 2.6(c)

P-channel circuit symbols

13

Fig. 2.7: Current flow directions for PMOS

Figure 2.6 (a) shows the circuit symbol for the p channel enhancement type MOSFET

Figure 2.6 (b) modified symbol with an arrowhead on the source lead

(c) simplified circuit symbol for the case where the source is connected to the

body.

2.3 COMPLEMENTARY MOS OR CMOS

This technology employs MOS transistors of both polarities. Figure 2.8 shows a cross-

section of a CMOS chip illustrating how the PMOS and NMOS transistors are fabricated.

While the PMOS transistor is implemented directly in the p-type substrate, the P-MOS

transistor is implemented directly in the p-type substrate, the PMOS transistor is

fabricated in a specially created n region called the n well.

The two devices are isolated from each other by a thick region of oxide that functions as

a insulator.

14

Fig. 2.8: Cross-section of CMOS integrated circuit

2.4 DC PARAMETERS OF THE OPAMP

2.4.1 OFFSET VOLTAGE AND CURRENTS

According to the ideal gain model of an opomp the dc output voltage should be zero

when the dc input voltage is zero. However in practice a dc offset is measured at the

output terminal even when the dc input voltage is zero.

The total output offset voltage is a function of two separate effects

(a) Input offset voltage

(b) Input bias currents

The input offset is as a result of a phenomenon arising from dc balance of the two points

The input bias currents are the actual current that must flow into or out of the two

terminals to ensure proper operation of the solid state circuitry.

=

15

===

| | = ℎ=

| ( ) = | | + | |

= = | − |+2

2.4.2 INPUT COMMON MODE RANGE ICMR

It is the average voltage of inverting and non inverting terminal

2.4.5 OUTPUT IMPEDANCE

Let Rout be output impedance of OPAMP, that include connected resistances

= ɤ1 +Where ɤ is output impedance of opamp itself and is feedback factor.

16

2.4.6 INPUT IMPEDANCE

Let the input impedance be Rin of the opamp including other connected resistance, rd be

input of impedance of opamp itself

= ɤ (! + )2.4.7 COMMON MODE REJECTION RATIO (CMRR)

CMRR gives the value by which the opamp suppresses common mode inputs.

= 20 logWhere Ad is differential gain (gain when differential input is applied).

Acm is the common mode gain (gain when common – mode inputs are applied)

2.4.8 SLEW RATE

The process which the output voltage of an opamp can change only at a finite range is

slew rate limitation. This effect is described quantitatively by specifying slew rate SR for

a give op amp.

The maximum rate of change of output voltage is SR

=

17

2.4.9 GAIN – BANDWIDTH RELATIONSHIP

See figure 2.9 below. As the gain reaches IA|=1 . This frequency at which this condition

is met is called unity gain frequency and is denoted on the curve as B

Fig. 2.9: Form of the magnitude of open loop gain for many op amp as a function of

frequency. Both f and A are logarithmic

= 1The unit gain frequency is the product of the dc or low frequency gain and the 3db

frequency. For this reason, the “unity gain frequency” is also called the “gain bandwidth

product.” Both terms unity gain frequency and gain bandwidth product are used in

specifications.

18

CHAPTER 3: DESIGN

3.1 CMOS OP AM design steps

1. Showing OP AMP SCHEMATICS

A schematic is created of all the eight transistors and connections.

Transistor ratios and ac currents selection

2. Poles and zeros obtained as well as dc gains

3.2 Design inputs

Requirements

1. Slew rate

2. Common mate rejection ratio

3. Gain bandwidth product

4. DC gain

5. Common mode input range

6. Output impedance

7. Input resistance

3.3 Design procedure for a 2 stage CMOS OP AMP

The first stage is a differential amplifier pair that is actively loaded with the current

mirror.

The second stage is a common source amplifier actively loaded with the current source

transistor.

The two stage CMOS OP AMP configuration is drawn in figure 3.1

19

Figure 3.1: Two stage OPAMP configuration

3.4 A summary of design relationships for the two stage OP AMP

1) Slew rate =CC

I5

2) Gain bandwidth =C

t C

GMIW

3) Transmission zero =C

Z C

GMW 2

4) Dominant pole =221

1

1

RGMCRWP

C

5) Second non-dominant pole =2

22 C

GMWP

20

6) Stage 1 gain )//( 040211 rrgA m

7) Stage 2 gain )//( 070662 rrgA m

3.5 OP AMP design procedure

1. Estimate the compensation capacitance CC by choosing or selecting a moderately

large load capacitance CL using the second non-dominant pole WP2 and transmission

zero Wz using similar triangles.

2. Determine I5 using slew rate relation; SR=I5|CC obtain tCWCGMguGM 11 sin

obtain (W/L) ratios of all transistors (note level 1 mo** parameters of 0.5 m

technology used.

3. Find overdrive voltage of Q1 Q2 Q6

Find r02, r04, r06, r07 using IDVr Ao ||

4. Find the voltage gains A1 and A2 and overall gain A obtain overall gain A in dB/

5. verify that ft is indeed lower than fz and fp2

3.4 Calculations

Step 1

2

2

2121

22 )( C

G

CCCCC

CGw m

C

Cmp

Where Lgddbdb CCCCC 7762

CC = Compensation capacitate

2211

1

RGCRwp

mC

C

mZ C

HW 2

21

Since Zpz WW

Say

wzWp 22

Since LCC 2 generally

L

mp C

GW 2

2

ThusC

m

L

m

C

G

C

G 22 2

CL CC

21

CC = 2CL

Given a load capacitated CL = 12pf

CC = 2x12pf = 24pf

Choose CC = 20pf

Step 2

AAI

SVSNrateslewSR

SRCI C

201020101020

/101|

)(

66125

6

5

ft = 1MHZ (unity gain bandwidth/gain bandwidth product)

sradftwt /1028.62 6

Since tCt

worCw

Gm1

22

11

1

6

6121

/1256.0

/106.125

1028.61020

mm

m

tCm

Ggbut

VmAG

VA

wCG

Thus VAgm /1256.01

4

6

4

6

L

WL

W

I

Ior

46

4

6I

L

WL

W

I

But AII 665 1020

Choose (W/L)5 = (W/L)6 = 200

446

/

2001020

LW

I

And since 64 10102/16 I

1001020

1010200/

6

6

4

LW

Since Q3 and Q4 are matched:

34 // LWLW

To obtain (W/L)7

5

7

4

6

/

/2

/

/

LW

LW

LW

LW

23

200200

200200/

200

/2

100

200

7

7

LW

LW

Since Q1 and Q2 are matched choose (W/L)1 = (W/L)2 = 200

Step 3

Find overdrive voltage |VOV| at which Q1, Q2, Q6 are operating, find overdrive voltage.

L

WvovpKI nP

21,2

1

Or 1,/

2

pKLW

IDvov

n

To find |vov| of Q1 i.e. |vov, 1|

Given oxpCKp 1

But using level – 1 MOSFET model parameter cancel

]5./[100

115./115

105.9

]5./[1001155./115{

22

2

9

222

vmsvcmp

mtox

vmvcmp

ox the permittivity of 112 1045.3 SiO f/m

911 105.9/1045.3/ oxoxox tC

265

5

9

92

11'

/75.411075.4110175.4

105.9

10967.3

105.9100

1045.3115

VAK

CKp

p

oxp

24

V

I

KLW

IVov

p

D

0489.0

1039.2

103.8

1020

)1075.41)(200(

10102

)1075.41)(200(

2/2

)/(

2|1,|

3

3

6

6

6

6

11

1

Since Q1 and Q2 are matched

|Vov, 1| = |Vov, 2| = 0.0489V

To find |Vov| of Q6 i.e |Vov, 6)

Using level 1 mosfet model parameters since 460onu

That is pn u4 , in similar triangles

V

KLW

IVov

VAK

VAkk

n

D

n

np

034.0197.10334.0

1040

10167)200(

10202

')/(

26,

/167'

]/[1075.4144

6

6

6

6

6

2

26''

8m1 was already obtained as 8m1 = Gm1 = 8m2 = 0.1256MA/V

25

Find 8m for Q6

VMA

or

VA

VovL

Wk

m

m

nm

/36.18

/10136.1034.0200101678

6,,8

6

366

6

'6

Find r02, r04, r06, r07, using level 1 parameter 1.0,2.0 np

To find r02 = (r01)

Given VV pPA 202.0/1/1||

m

I

Vr

p

AP 11021021010

20|| 666

202

To find r04 = (r03)

MII

Vr

D

n

D

An 11011010

10|/1||| 66

4404

To find r06

kr

or

II

Ar

D

n

D

AN

500

105.01020

10|/1|||

06

66

6606

To find r07

kr

or

I

Vr

D

n

d

An

500

105.01020

10|/1|

7

||

07

66

7707

Step 4

26

Find the voltage gains A1 and A2 and the overall gain A

The voltage gain of the first stage is determined from

The voltage gain of the second stage is determined from;

VV

k

kk

rrgA m

|284

25010136.1

)500||500(10136.1

)||(

3

3

070662

The overall dc open loop gain is

2.835,17

)284()8.62(21

A

AAA

In dB

Adb = 20log 17, 835.2 = 85.02dB

Step 5

Verify that ft is lower than fz and fp2

Since ft = 1MHZ

And gm6 = Gm2

VV

MIM

rrgA mi

|8.62

10500101256.0

)1||(101256.0

)||(

33

3

04021

27

MHZf

f

C

Gf

z

z

C

mz

044.9

10044.910256.1

1036.1

28.61020

10136.1

2

1

610

3

12

32

MHZf

Hz

C

Gf

CCnb

p

mp

L

074.15

10074.15

101228.6

1036.11

2

1

2

6

12

3

2

22

2

Thus ft is indeed lower than fz and fp2

Step 6

The lower limit of the input common mode range is the value of the input voltage at

which Q1 and Q2 leave saturation region. This occurs when the input voltage below the

voltage at the drain of Q1 by voltsVtp || . But vVtp 8.0|| .

xVV GSDD 3

To get VGS3

28

VVx

VVx

VV

V

VVVov

VVVov

L

WVkI

DD

GSDD

GS

GS

tGS

tg

ovnD

834.0

834.08.0034.0

8.0034.0

||

||

2

1

3

3

3

33

333

2

33

3

29

The lower limit of common mode range is VVICM 3min

VV

Vx

xV

DD

p

1.2

1.2|8.0|3

||3

The upper limit of the ICMR is the value of input voltage of which input voltage of Q5

leaves saturation region. Since for Q5 to operate in saturation, the voltage across it i.e.

55PV should be at least equal to the overdrive voltage at which it is operating i.e. 0.048v,

the highest permitted at the drain of Q5 should be vVVS 3.18.01.2055 . It follows

that;

Step 7

)1( OLdin ArR

Typically 1210dr

1612 10784.1)2.178351(10

/2.835,17

1

in

OL

R

VVA

30

REFERENCES

Adel S. Sedra, Kenneth C. Smith, “Microelectronic Circuits, Theory and Applications,

“Oxford University Press, 5th Edition, 2009

William D. Stanley, Operational Amplifiers with Linear Integrated Circuits. Pearson

Education, Fourth Edition, 2009.

Robert Boylestad Louis Nasheskly, Electronics Devices and Circuits Theory, 10th

Edition.