deca - Intel...SMA Connectors & Differential Amplifier Page Ethernet 22 23 24 07.0 Title MIPI...
Transcript of deca - Intel...SMA Connectors & Differential Amplifier Page Ethernet 22 23 24 07.0 Title MIPI...
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
2.5V & 2.8V & 3.3V
12
02.01
02.05 MAX 10 Clocks & Configuration
802.06
USB Blaster II
05.01 Expansion Headers - BBB Headers
1
Page
15
11
02.0
01.0
Title
Cover Page
Section
Block Diagram
1.01
2
Design Introduction
4
3
1.02
6
5
7
MAX 10 10M50DAF484
MAX 10 BANK3 & BANK402.02
MAX 10 BANK1 & BANK2
02.04
02.03 MAX 10 BANK5 & BANK6
MAX 10 BANK7 & BANK8
MAX10 Power & GND
05.0 Expansion Port
06.0 Memory06.01 DDR3 SDRAM & QSPI Flash
06.02 SD Card
07.01
20
08.01
Accelerometer
Ethernet
09.02
USB PHY09.01
08.0
SMA Connectors & Differential Amplifier
Page
Ethernet
22
23
24
07.0
Title
MIPI Interface
Section
HDMI TX 16
17
07.02
19
18
Audio CODEC
09.0 USB PHY
10.0 Analog Interface10.01
Gesture, Humidity, Temperature Sensors11.02
11.0 Sensors
LED & BUTTON & SWITCH
11.01
12.01
12.0 User Interface
1.2V & 1.5V & 1.8V & 5V
13
14
25
21
System Power
MAX10 Decoupling
Clock
02.07 9
13.013.01
DECA
Clock03.003.01 10
04.004.01
JTAG
Video & Audio
07.03
13.02
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page C
DECAB
1 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page C
DECAB
1 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Cover Page C
DECAB
1 25Wednesday, March 11, 2015
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Block Diagram C
DECAB
2 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Block Diagram C
DECAB
2 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Block Diagram C
DECAB
2 25Thursday, March 19, 2015
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Notes: 1. Put all the 1pF caps close to each MAX10 analog pin.2. Route the analog input signal adjacent to the REFGND.
VCCIO = 2.5V
VCCIO = 2.5V
VCCIO = 2.5V
Audio LINE-IN to MAX10 ADC
Ethernet
MIPI I2C Interface
MIPI Interface
MIPI Control Interface
Header Analog Input
ADC1IN1ADC1IN2
ADC1IN3
ADC1IN5ADC1IN6
ADC1IN7
ADC1IN4
ADC1IN1
ADC1IN2
ADC1IN3
ADC1IN4
ADC1IN5
ADC1IN6
ADC1IN7REFGND
LINE_IN_L_ADC
MIPI_MD_p0
MIPI_MD_n0
MIPI_MD_p1
MIPI_MD_n1
MIPI_MD_p2
MIPI_MD_n2
MIPI_MD_p3
MIPI_MD_n3
NET_RX_ER
NET_RX_DV
NET_TXD3
NET_RXD3
NET_TXD0
NET_RXD0NET_RXD1
NET_CRS
NET_COL
NET_TXD1
NET_TXD2
MIPI_MD_p3MIPI_MD_n3
MIPI_MD_p2MIPI_MD_n2
MIPI_MD_p1MIPI_MD_n1
MIPI_MD_p0MIPI_MD_n0
MIPI_I2C_SDAMIPI_I2C_SCL
MIPI_RESET_n
MIPI_MCLKMIPI_CORE_EN
NET_MDC
MIPI_WP
NET_RXD2
NET_MDIO
AIN0 12
AIN1 12
AIN2 12
AIN3 12
AIN4 12
AIN5 12
AIN6 12
LINE_IN_L_ADC17
NET_TXD[3..0] 18
NET_RX_ER 18NET_RX_DV 18NET_COL 18NET_CRS 18
NET_RXD[3..0] 18
MIPI_MD_p[3..0]15
MIPI_MD_n[3..0]15MIPI_MC_p7,15
MIPI_MC_n7,15
MIPI_RESET_n 15
MIPI_MCLK 15
MIPI_WP 15
MIPI_CORE_EN 15
MIPI_I2C_SDA 15
MIPI_I2C_SCL 15
AIN[6..0] 12
NET_MDC 18
NET_MDIO18
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECAB
3 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECAB
3 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 1, Bank 2 C
DECAB
3 25Wednesday, March 11, 2015
R178
10
C126
1p
R179
10
C125
1p
R219
100
R180
10
C124
1p
R181
10
R221
100
REFGND1DNI
R230
100
C123
1p
R51
10
C24
1p
R5010
C25
1p
R49
10
C26
1p
MAX 10 LEFT BANKSBANK-2BANK-1A
BANK-1B
10M50DAF484C6GES
U1A
DIFFIO_RX_L1N/ADC1IN1F5
DIFFIO_RX_L1P/ADC1IN2F4
DIFFIO_RX_L2N/ADC2IN1E4
DIFFIO_RX_L2P/ADC2IN8E3
DIFFIO_RX_L3N/ADC1IN3J8
DIFFIO_RX_L3P/ADC1IN4J9
DIFFIO_RX_L4N/ADC2IN3G4
DIFFIO_RX_L4P/ADC2IN4F3
DIFFIO_RX_L5P/ADC1IN6H3
DIFFIO_RX_L5N/ADC1IN5J4
DIFFIO_RX_L6N/ADC2IN5H4
DIFFIO_RX_L6P/ADC2IN6G3
DIFFIO_RX_L7N/ADC1IN7K5
DIFFIO_RX_L7P/ADC1IN8K6
DIFFIO_RX_L8P/ADC2IN2J3
DIFFIO_RX_L8N/ADC2IN7K4
DIFFIO_RX_L15NK8
VREFB1N0C1
DIFFIO_RX_L19NK2
DIFFIO_RX_L19PL2
DIFFIO_RX_L23NG1
DIFFIO_RX_L21PF2
DIFFIO_RX_L23PF1
DIFFIO_RX_L21NE1
DIFFIO_RX_L24NM4
DIFFIO_RX_L24PM3
DIFFIO_RX_L25NK1
DIFFIO_RX_L25PL1
DIFFIO_RX_L16PD2
IO_BANK1D1
DIFFIO_RX_L29NP4
DIFFIO_RX_L29PP5
DIFFIO_RX_L37NN3
DIFFIO_RX_L37PN2
DIFFIO_RX_L39NR4
DIFFIO_RX_L39PR5
DIFFIO_RX_L40NT1
DIFFIO_RX_L40PT2
DIFFIO_RX_L41NN8
DIFFIO_RX_L41PN9
DIFFIO_RX_L42NP1
DIFFIO_RX_L42PN1
DIFFIO_RX_L43NT3
DIFFIO_RX_L43PU2
DIFFIO_RX_L44NU1
DIFFIO_RX_L44PV1
DIFFIO_RX_L45NU4
DIFFIO_RX_L45PU5
DIFFIO_RX_L46NU3
DIFFIO_RX_L46PV3
DIFFIO_RX_L47NP8
DIFFIO_RX_L47PR7
DIFFIO_RX_L48NW1
DIFFIO_RX_L48PW2
DIFFIO_RX_L60NR1
DIFFIO_RX_L60PR2
VREFB2N0M2
IO_BANK2M1
DIFFIO_RX_L16ND3
DIFFIO_RX_L20NL8
DIFFIO_RX_L20PL9
DIFFIO_RX_L22NH1
DIFFIO_RX_L22PJ1
R220
100
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO = 3.3V VCCIO = 3.3V
QSPI Flash
Header GPIO
Temperature Sensor
Humidity and Temperature Sensor
Gesture Sensor
Power Monitor
CapSense Buttons
Micro SD Card
GPIO1_D17
TEMP_CS_n
GPIO1_D0
GPIO1_D12
GPIO1_D2
GPIO1_D3GPIO1_D4
GPIO1_D16FLASH_RESET_n
GPIO1_D7GPIO1_D5GPIO1_D18
FLASH_NCSO
GPIO1_D20
FLASH_DATA3
GPIO1_D15
GPIO1_D1
GPIO1_D13
GPIO1_D11
RH_TEMP_I2C_SCLRH_TEMP_I2C_SDA
RH_TEMP_DRDY_n
LIGHT_I2C_SCL
LIGHT_I2C_SDA
LIGHT_INT
GPIO1_D10GPIO1_D9
GPIO1_D6
GPIO1_D22GPIO1_D19
SYS_RESET_n
TEMP_SIOTEMP_SC
FLASH_DCLKFLASH_DATA0
FLASH_DATA1FLASH_DATA2
PMONITOR_I2C_SCL
PMONITOR_I2C_SDA
PMONITOR_ALERT
CAP_SENSE_I2C_SCLCAP_SENSE_I2C_SDA
SD_SEL
PWR_BUT
GPIO0_D38
GPIO0_D30
GPIO0_D29
GPIO0_D28
GPIO0_D27
GPIO0_D10
GPIO0_D40
GPIO0_D18
GPIO0_D15
GPIO0_D14GPIO0_D11
GPIO0_D9
GPIO0_D8GPIO0_D7
GPIO0_D6
GPIO0_D33
GPIO0_D32
GPIO0_D16
GPIO0_D22
GPIO0_D26
GPIO0_D41
GPIO0_D31GPIO0_D20
GPIO0_D19GPIO0_D42
GPIO0_D3
GPIO0_D12
GPIO0_D25
GPIO0_D17GPIO0_D2
GPIO0_D5GPIO0_D1
GPIO0_D4
GPIO0_D21
GPIO0_D23
GPIO0_D24
GPIO0_D0
GPIO0_D37GPIO0_D36
GPIO0_D39
GPIO0_D34
GPIO0_D35
GPIO0_D43
FLASH_NCSO 13FLASH_DCLK 13
FLASH_DATA[3..0] 13FLASH_RESET_n 13
GPIO1_D[22..0]7,12
TEMP_CS_n22
RH_TEMP_I2C_SCL22RH_TEMP_I2C_SDA22RH_TEMP_DRDY_n22
LIGHT_I2C_SCL22LIGHT_I2C_SDA22LIGHT_INT22
SYS_RESET_n12
GPIO0_D[43..0]7,12
TEMP_SC22TEMP_SIO22
PMONITOR_I2C_SDA 24PMONITOR_I2C_SCL 24
PMONITOR_ALERT 24
CAP_SENSE_I2C_SDA 23CAP_SENSE_I2C_SCL 23
SD_SEL14
PWR_BUT12
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 3 & 4 C
DECAB
4 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 3 & 4 C
DECAB
4 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 3 & 4 C
DECAB
4 25Wednesday, March 11, 2015
BANK-3 BANK-4MAX 10 BOTTOM BANKS
10M50DAF484C6GES
U1B
DIFFIO_RX_B10NY7
DIFFIO_RX_B10PY8
DIFFIO_RX_B12NAB2
DIFFIO_RX_B12PAB3
DIFFIO_RX_B14NY3
DIFFIO_RX_B14PY4
DIFFIO_RX_B17NAA5
DIFFIO_RX_B17PAB5
DIFFIO_RX_B19NAB6
DIFFIO_RX_B19PAB7
DIFFIO_RX_B21NAA8
DIFFIO_RX_B21PAB8
DIFFIO_RX_B23NAA9
DIFFIO_RX_B23PAB9
DIFFIO_RX_B2NV4
DIFFIO_RX_B2PV5
DIFFIO_RX_B4NY1
DIFFIO_RX_B4PY2
DIFFIO_RX_B6NAA1
DIFFIO_RX_B6PAA2
DIFFIO_RX_B8NY5
DIFFIO_RX_B8PY6
DIFFIO_TX_RX_B11NW9
DIFFIO_TX_RX_B11PW10
DIFFIO_TX_RX_B13NW7
DIFFIO_TX_RX_B13PW8
DIFFIO_TX_RX_B15NR10
DIFFIO_TX_RX_B15PP10
DIFFIO_TX_RX_B16NAA6
DIFFIO_TX_RX_B16PAA7
DIFFIO_TX_RX_B1NW5
DIFFIO_TX_RX_B1PW6
DIFFIO_TX_RX_B22NY10
DIFFIO_TX_RX_B22PAA10
DIFFIO_TX_RX_B3NU6
DIFFIO_TX_RX_B3PU7
DIFFIO_TX_RX_B5NW4
DIFFIO_TX_RX_B5PW3
DIFFIO_TX_RX_B7NV7
DIFFIO_TX_RX_B7PV8
DIFFIO_TX_RX_B9NR9
DIFFIO_TX_RX_B9PP9
VREFB3N0AA3
IO_BANK3AB4
DIFFIO_RX_B25NW11
DIFFIO_RX_B25PY11
DIFFIO_RX_B27NAB10
DIFFIO_RX_B27PAB11
DIFFIO_RX_B29NAB12
DIFFIO_RX_B29PAB13
DIFFIO_RX_B35NW12
DIFFIO_RX_B35PW13
DIFFIO_RX_B38NAA14
DIFFIO_RX_B38PAB15
DIFFIO_RX_B40NAA15
DIFFIO_RX_B40PY16
DIFFIO_RX_B42NAB16
DIFFIO_RX_B42PAA16
DIFFIO_RX_B44NAB19
DIFFIO_RX_B44PAB20
DIFFIO_RX_B46NAA19
DIFFIO_RX_B46PY18
DIFFIO_RX_B50NAB21
DIFFIO_RX_B50PAA20
DIFFIO_RX_B58NAB17
DIFFIO_RX_B58PAB18
DIFFIO_TX_RX_B24NV11
DIFFIO_TX_RX_B24PV12
DIFFIO_TX_RX_B26NR12
DIFFIO_TX_RX_B26PP12
DIFFIO_TX_RX_B28NAA11
DIFFIO_TX_RX_B28PAA12
DIFFIO_TX_RX_B34NV13
DIFFIO_TX_RX_B34PW14
DIFFIO_TX_RX_B36NR13
DIFFIO_TX_RX_B36PP13
DIFFIO_TX_RX_B37NY13
DIFFIO_TX_RX_B37PY14
DIFFIO_TX_RX_B39NV14
DIFFIO_TX_RX_B39PW15
DIFFIO_TX_RX_B41NU15
DIFFIO_TX_RX_B41PV16
DIFFIO_TX_RX_B43NAA17
DIFFIO_TX_RX_B43PY17
DIFFIO_TX_RX_B45NV15
DIFFIO_TX_RX_B45PW16
DIFFIO_TX_RX_B49NY19
DIFFIO_TX_RX_B49PW18
VREFB4N0AA13
IO_BANK4AB14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO = 1.5VVCCIO = 1.5V
Micro SD Card
Audio CODEC Interface
Audio Control Interface
KEY
SWITCH
DDR3_A1
DDR3_DQS_n1DDR3_DQS_p1
DDR3_DQ10DDR3_DQ9DDR3_DQ11DDR3_DQ8
DDR3_DM1
DDR3_DQ12DDR3_DQ15DDR3_DQ14DDR3_DQ13
DDR3_DM0
DDR3_A14
DDR3_DQ6DDR3_DQ7
DDR3_DQ2DDR3_DQ4DDR3_DQ0DDR3_DQ1
DDR3_DQ5DDR3_DQ3
DDR3_CK_nDDR3_CK_p
DDR3_A8
DDR3_CAS_n
DDR3_CKE
DDR3_A9
DDR3_A4
DDR3_A6DDR3_RESET_n
DDR3_A11
DDR3_A13
DDR3_BA1
DDR3_VREF
DDR3_VREF
DDR3_BA2
DDR3_A0
DDR3_RAS_n
DDR3_WE_n
DDR3_A10
DDR3_A2 DDR3_A12
DDR3_A7
DDR3_A5
DDR3_BA0AUDIO_DOUT_MFP2
AUDIO_SCLK_MFP3AUDIO_SCL_SS_n
AUDIO_SDA_MOSI
AUDIO_MISO_MFP4
AUDIO_SPI_SELECT
AUDIO_RESET_nAUDIO_GPIO_MFP5
AUDIO_MCLK
AUDIO_BCLKAUDIO_WCLK
AUDIO_DIN_MFP1
SD_DAT0
SD_DAT1
SD_CLKSD_DAT3
SD_CMD_DIR
SD_D0_DIRSD_CMD
SD_D123_DIR
SD_DAT2
KEY0KEY1SW0SW1
SD_FB_CLK
DDR3_A3
DDR3_CS_nDDR3_ODT
VCC1P5_DDR3
VCC1P5_DDR3
DDR3_VREF
DDR3_RESET_n 13
DDR3_WE_n 13DDR3_RAS_n 13DDR3_CAS_n 13
DDR3_ODT 13
DDR3_BA[2..0]13
DDR3_DQ[ 15..0] 13
DDR3_DQS_p[1..0] 7,13
DDR3_DQS_n[1..0] 7,13
DDR3_DM[1..0]13
DDR3_A[14..0]13
DDR3_CK_p 13DDR3_CK_n 13
DDR3_CKE 13
DDR3_CS_n 13
SD_CLK14
SD_D0_DIR14SD_D123_DIR
14SD_CMD_DIR
14
SD_DAT[3..0]14
SD_CMD14
AUDIO_MCLK17
AUDIO_BCLK17
AUDIO_WCLK17
AUDIO_DIN_MFP117
AUDIO_DOUT_MFP217
AUDIO_SCLK_MFP317
AUDIO_SCL_SS_n17
AUDIO_SDA_MOSI17AUDIO_MISO_MFP4
17AUDIO_SPI_SELECT
17AUDIO_RESET_n17
AUDIO_GPIO_MFP517
SW[1..0]23
KEY[1..0]23
SD_FB_CLK14
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 5 & 6 C
DECAB
5 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 5 & 6 C
DECAB
5 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 5 & 6 C
DECAB
5 25Wednesday, March 11, 2015
BANK-5 BANK-6MAX 10 RIGHT BANKS
10M50DAF484C6GES
U1C
DIFFIO_RX_R19NU19
DIFFIO_RX_R19PV18
DIFFIO_RX_R1N/RDNU17 DIFFIO_RX_R1P/RUPU18
DIFFIO_RX_R20NW22
DIFFIO_RX_R20PY22
DIFFIO_RX_R21NW20
DIFFIO_RX_R21PW19
DIFFIO_RX_R22NY21
DIFFIO_RX_R22PY20
DIFFIO_RX_R23NU20
DIFFIO_RX_R23PV20
DIFFIO_RX_R24NV22
DIFFIO_RX_R24PV21
DIFFIO_RX_R25N/DQ1RR14
DIFFIO_RX_R25P/DQ1RR15
DIFFIO_RX_R26NT22
DIFFIO_RX_R26PT21
DIFFIO_RX_R27N/DM1RT18
DIFFIO_RX_R27P/DQ1RT19
DIFFIO_RX_R28N/DQ1RR20
DIFFIO_RX_R28P/DQ1RT20
DIFFIO_RX_R29NU22
DIFFIO_RX_R29PU21
DIFFIO_RX_R2NAA22
DIFFIO_RX_R2PAA21
DIFFIO_RX_R30N/DQ1RP14
DIFFIO_RX_R30P/DQ1RP15
DIFFIO_RX_R31NN22
DIFFIO_RX_R31PP21
DIFFIO_RX_R32N/DQSN1RP18
DIFFIO_RX_R32P/DQS1RR18
DIFFIO_RX_R33N/DQ1RP20
DIFFIO_RX_R33P/DQ1RP19
DIFFIO_RX_R34NL22
DIFFIO_RX_R34PM21
DIFFIO_RX_R35NM22
DIFFIO_RX_R35PN21
IO_BANK5R22 VREFB5N0P22
DIFFIO_RX_R39NH21
DIFFIO_RX_R39PH22
DIFFIO_RX_R41NJ21
DIFFIO_RX_R41PJ22
DIFFIO_RX_R42NG19
DIFFIO_RX_R42PG20
DIFFIO_RX_R43NF22
DIFFIO_RX_R43PG22
DIFFIO_RX_R44N/DQ2RM14
DIFFIO_RX_R44P/DQ2RM15
DIFFIO_RX_R45NE21
DIFFIO_RX_R45PE22
DIFFIO_RX_R46N/DM2RN19
DIFFIO_RX_R46P/DQ2RN18
DIFFIO_RX_R47P/DQ2RM20
DIFFIO_RX_R47N/DQ2RN20
DIFFIO_RX_R48NF20
DIFFIO_RX_R48PF21
VREFB6N0D21
DIFFIO_RX_R49PD22
DIFFIO_RX_R51N/DQ2RL18
DIFFIO_RX_R51P/DQ2RM18
DIFFIO_RX_R52N/DQ2RL20
DIFFIO_RX_R52P/DQ2RL19
DIFFIO_RX_R53NF18
DIFFIO_RX_R53PE19
DIFFIO_RX_R54NE20
DIFFIO_RX_R54PF19
DIFFIO_RX_R55N/DQSN3RK15
DIFFIO_RX_R55P/DQS3RK14
DIFFIO_RX_R56ND19
DIFFIO_RX_R56PC20
DIFFIO_RX_R57N/DQ3RJ18
DIFFIO_RX_R57P/DQ3RK18
DIFFIO_RX_R58N/DQ3RK20
DIFFIO_RX_R58P/DQ3RK19
DIFFIO_RX_R59NE17
DIFFIO_RX_R59PF17
DIFFIO_RX_R60NB21
DIFFIO_RX_R60PB22
DIFFIO_RX_R61N/DM3RJ15
DIFFIO_RX_R61P/DQ3RJ14
DIFFIO_RX_R62NA21
DIFFIO_RX_R62PB20
DIFFIO_RX_R63N/DQ3RH18
DIFFIO_RX_R63P/DQ3RH19
DIFFIO_RX_R64N/DQ3RH20
DIFFIO_RX_R64P/DQ3RJ20
DIFFIO_RX_R70N/CK#_6E18
DIFFIO_RX_R70P/CK_6D18
DIFFIO_RX_R49NC22
IO_BANK6C21
R229
49.9
C195
0.1u
C89
0.1u
DNI
C102
0.1u
R1771K
R217
49.9
R1671K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO = 1.2VVCCIO = 1.8V
USB PHY
LEDHDMI TX
HDMI Audio Interface
MIPI Interface
Accelerometer
HDMI_I2S1HDMI_LRCLK
HDMI_TX_HSHDMI_TX_VS
HDMI_I2C_SDA
HDMI_SCLK
HDMI_I2C_SCL
HDMI_I2S3
HDMI_I2S2
HDMI_TX_D20
HDMI_TX_D18
HDMI_TX_D8HDMI_TX_D21
HDMI_TX_D4
HDMI_TX_D16
HDMI_MCLK
HDMI_I2S0
HDMI_TX_D11
HDMI_TX_D23
HDMI_TX_D6
HDMI_TX_D14
HDMI_TX_DEHDMI_TX_INT
HDMI_TX_D17
HDMI_TX_D10
HDMI_TX_D22
HDMI_TX_D19
HDMI_TX_D15
HDMI_TX_D12
HDMI_TX_D2HDMI_TX_D1
HDMI_TX_D7
HDMI_TX_D3HDMI_TX_D5
HDMI_TX_D0
HDMI_TX_D9
HDMI_TX_D13
USB_FAULT_n
USB_DATA0
USB_DATA7
USB_DATA4
USB_DATA2
USB_NXT
USB_DIR
USB_STP
USB_CS
USB_DATA3
USB_DATA1
USB_DATA5
USB_DATA6USB_RESET_n
HDMI_TX_CLK
MIPI_LP_MD_p2
MIPI_LP_MD_n3MIPI_LP_MD_n0MIPI_LP_MD_p3
MIPI_LP_MD_n2MIPI_LP_MD_n1MIPI_LP_MD_p1
MIPI_LP_MD_p0
LED4
LED6
LED7
LED0LED1LED2LED3
LED5
USB_CLKOUT_NOPLL
G_SENSOR_CS_n
G_SENSOR_SCLK
G_SENSOR_INT1G_SENSOR_SDO
G_SENSOR_INT2G_SENSOR_SDI
USB_DATA[7..0]19
USB_NXT19USB_DIR19USB_STP19USB_CS19 USB_RESET_n19
USB_FAULT_n19
LED[7..0]23HDMI_TX_D[23..0]16
HDMI_TX_CLK6,7,16
HDMI_TX_HS16
HDMI_TX_VS16
HDMI_TX_DE16
HDMI_TX_INT
HDMI_I2C_SDA16
HDMI_I2C_SCL16
HDMI_I2S[3:0]16
HDMI_MCLK16
HDMI_LRCLK16
HDMI_SCLK16
USB_CLKOUT_NOPLL19
HDMI_TX_CLK6,7,16
MIPI_LP_MD_p[3..0]15
MIPI_LP_MD_n[3..0]15
G_SENSOR_SDO 21
G_SENSOR_SDI 21
G_SENSOR_SCLK 21
G_SENSOR_CS_n 21
G_SENSOR_INT1 21G_SENSOR_INT2 21
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 7 & 8 C
DECAB
6 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 7 & 8 C
DECAB
6 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Bank 7 & 8 C
DECAB
6 25Thursday, March 19, 2015
R168 0
BANK-7 BANK-8MAX 10 TOP BANKS
10M50DAF484C6GES
U1D
DIFFIO_RX_T10NA17
DIFFIO_RX_T10PA18
DIFFIO_RX_T15NC15
DIFFIO_RX_T15PC16
DIFFIO_RX_T16NA16
DIFFIO_RX_T16PB16
DIFFIO_RX_T17NJ13
DIFFIO_RX_T17PH14
DIFFIO_RX_T18NC13
DIFFIO_RX_T18PC14
DIFFIO_RX_T19NB14
DIFFIO_RX_T19PA14
DIFFIO_RX_T1NE15
DIFFIO_RX_T1PE16
DIFFIO_RX_T20NE13
DIFFIO_RX_T20PD14
DIFFIO_RX_T21PE12
DIFFIO_RX_T21ND13
DIFFIO_RX_T22NJ12
DIFFIO_RX_T22PH13
DIFFIO_RX_T23NA12
DIFFIO_RX_T23PA13
DIFFIO_RX_T24ND12
DIFFIO_RX_T24PC12
DIFFIO_RX_T25NA10
DIFFIO_RX_T25PA11
DIFFIO_RX_T26NC10
DIFFIO_RX_T26PC11
DIFFIO_RX_T27NB11
DIFFIO_RX_T27PB12
DIFFIO_RX_T28NJ11
DIFFIO_RX_T28PH12
DIFFIO_RX_T31NB8
DIFFIO_RX_T31PA9
DIFFIO_RX_T2NC17
DIFFIO_RX_T2PD17
DIFFIO_RX_T30NC9
DIFFIO_RX_T30PB10
DIFFIO_RX_T29PA7
DIFFIO_RX_T29NA8
DIFFIO_RX_T5NF15
DIFFIO_RX_T5PF16
DIFFIO_RX_T6NB19
DIFFIO_RX_T6PC19
DIFFIO_RX_T7NB17
DIFFIO_RX_T7PC18
DIFFIO_RX_T8NA19
DIFFIO_RX_T8PA20
DIFFIO_RX_T9NE14
DIFFIO_RX_T9PD15
IO_BANK7A15 VREFB7N0B15
DIFFIO_RX_T39NC7
DIFFIO_RX_T39PC8
DIFFIO_RX_T41NA6
DIFFIO_RX_T41PB7
DIFFIO_RX_T42PD8
DIFFIO_RX_T43NA4
DIFFIO_RX_T43PA5
DIFFIO_RX_T44NE9
DIFFIO_RX_T45PA2
DIFFIO_RX_T45NA3
DIFFIO_RX_T46PB3
DIFFIO_RX_T46NB4
DIFFIO_RX_T49ND5
DIFFIO_RX_T49PC5
DIFFIO_RX_T51NB1
DIFFIO_RX_T51PB2
DIFFIO_RX_T53PC3
VREFB8N0D7
IO_BANK8C6
DIFFIO_RX_T47PB5
DIFFIO_RX_T47NC4
DIFFIO_RX_T48PE8
DIFFIO_RX_T53NC2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO = 1.5V
VCCIO = 2.5V
VCCIO = 3.3V
VCCIO = 3.3V
VCCIO = 1.2V
VCCIO = 1.2VVCCIO = 2.5V
Ethernet
Header GPIO
HDMI TX
DDR3USB PHY
MIPI Interface
MAX10 CONFIG Status
JTAG Interface
DDR3_DQS_n0DDR3_DQS_p0
DDR3_CLK_50
ADC_CLK_10
MAX10_CLK2_50
NET_RX_CLK
GPIO1_D8GPIO1_D14
GPIO0_D13
HDMI_TX_CLK
USB_CLKOUT
USB_CLKIN
USB_CLKOUT
USB_CLKIN
MIPI_LP_MC_nMIPI_LP_MC_p
BOOT_SEL
BOOT_SELJTAG_TCK
JTAG_TDOJTAG_TMS
JTAG_TDI
JTAG_EN
MIPI_MC_pMIPI_MC_n
NCONFIG
NSTATUSCONF_DONE
MAX10_CLK1_50
GPIO1_D21
NET_RESET_nNET_TX_EN
MIPI_MC_p
MIPI_MC_n
NET_TX_CLK
NET_PCF_EN
VCC1P2
VCC2P5
DDR3_DQS_p0 13
DDR3_DQS_n0 13
DDR3_CLK_50 10
MAX10_CLK1_50 10MAX10_CLK2_50 10
NET_RX_CLK 18
GPIO1_D1412GPIO1_D812
GPIO0_D1312
HDMI_TX_CLK6,16
USB_CLOCK19
MIPI_MC_p15
MIPI_MC_n15
JTAG_TCK 11JTAG_TMS 11JTAG_TDO 11JTAG_TDI 11JTAG_EN 11
NSTATUS11
CONF_DONE11
NCONFIG11MIPI_LP_MC_p
15MIPI_LP_MC_n15
ADC_CLK_10 10
GPIO1_D2112NET_TX_CLK 18
NET_RESET_n 18
NET_TX_EN 18
NET_PCF_EN 18
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Clocks & Configuration C
DECAB
7 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Clocks & Configuration C
DECAB
7 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX 10 Clocks & Configuration C
DECAB
7 25Thursday, March 19, 2015
MAX 10 ConfigurationBANK-1B BANK-8
10M50DAF484C6GES
U1F
DIFFIO_RX_L15P/JTAGENK9
DIFFIO_RX_L17P/TCKG2
DIFFIO_RX_L17N/TMSH2
DIFFIO_RX_L18N/TDIL4
DIFFIO_RX_L18P/TDOM5
DIFFIO_RX_T42N/DEV_CLRND9
DIFFIO_RX_T44P/DEV_OED10
NCONFIGH9
BOOT_SELH10
DIFFIO_RX_T48N/CRC_ERRORF7
DIFFIO_RX_T50P/NSTATUSG9
DIFFIO_RX_T50N/CONF_DONEF8
R258
10K
BANK-2
MAX 10 CLOCK
BANK-3
BANK-4
BANK-6
BANK-8
10M50DAF484C6GES
U1E
DIFFIO_RX_L28N/CLK0NN4
DIFFIO_RX_L28P/CLK0PN5
DIFFIO_RX_L36N/CLK1NM8
DIFFIO_RX_L36P/CLK1PM9
DIFFIO_TX_RX_B18N/CLK6NV9
DIFFIO_TX_RX_B18P/CLK6PV10
DIFFIO_TX_RX_B20N/CLK7NR11
DIFFIO_TX_RX_B20P/CLK7PP11
DIFFIO_RX_R38N/CLK2NN15
DIFFIO_RX_R38P/CLK2PN14
DIFFIO_RX_R40N/CLK3NK21
DIFFIO_RX_R40P/CLK3PK22
DIFFIO_RX_T38N/CLK4NE10
DIFFIO_RX_T38P/CLK4PE11
DIFFIO_RX_T40P/CLK5PJ10
DIFFIO_RX_T40N/CLK5NH11
DIFFIO_RX_L38N/DPCLK0P3
DIFFIO_RX_L38P/DPCLK1R3
DIFFIO_RX_L59N/PLL_L_CLKOUTNT5
DIFFIO_RX_L59P/PLL_L_CLKOUTPT6
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTNW17
DIFFIO_TX_RX_B57P/PLL_B_CLKOUTPV17
DIFFIO_RX_R50N/DPCLK2/DQSn2RL15
DIFFIO_RX_R50P/DPCLK3/DQS2RL14
DIFFIO_RX_R69N/PLL_R_CLKOUTNG17
DIFFIO_RX_R69P/PLL_R_CLKOUTPH17
DIFFIO_RX_T52N/PLL_T_CLKOUTNE6
DIFFIO_RX_T52P/PLL_T_CLKOUTPD6
R259
10K
R171 0
DNI
R2561K
R170 0
R218
100
R195 10K
R169 0DNI
1
ON
SW2
SW-DIP2
1 2
R257
10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place this FB close to MAX10 ADC_VREF
Place filter close to VCCIO1A pins
REFGND
VCC1P2_VCC
VCC1P2_VCC
VCC1P2_VCCD
VCC1P2_VCCD
VCC2P5 VCC2P5_VCCA
VCC2P5_VCCAVCC1P2_VCC 1.2V_VDDADC
1.2V_VDDADC
VCC2P5 VCC2P5_VCCAADC
VCC2P5_VCCAADC
VCC2P5_VREF
VCC2P5
VCC2P5
VCC2P5
VCC3P3
VCC3P3
VCC1P5_DDR3
VCC1P5_DDR3
VCC1P8
VCC1P2
ANAIN1 20ANAIN2 20
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Power & GND C
DECAB
8 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Power & GND C
DECAB
8 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Power & GND C
DECAB
8 25Wednesday, March 11, 2015
L15 30ohm, 3A
C16410u
MAX 10 GROUND
10M50DAF484C6GES
U1H
GNDY9
GNDY15
GNDY12
GNDW21
GNDV6
GNDV2
GNDV19
GNDU13
GNDU10
GNDT8
GNDT4
GNDT16
GNDT14
GNDR21
GNDR19
GNDP6
GNDP2
GNDP17
GNDN13
GNDN11
GNDM7
GNDM19
GNDM16
GNDM10
GNDL5
GNDL21
GNDL17
GNDL13
DNUL3
GNDK3
GNDK12
GNDK10
GNDJ6
GNDJ2
GNDJ19
GNDJ16
GNDG8
GNDG6
GNDG21
GNDG18
GNDG15
GNDF13
GNDF10
GNDE7
GNDE2
GNDD4
GNDD20
GNDD16
GNDD11
GNDB9
GNDB6
GNDB18
GNDB13
GNDAB22
GNDAB1
GNDAA4
GNDAA18
GNDA22
GNDA1
NC2F6NC1E5
REFGNDH5
L21 30ohm, 3A
C26010u
C4110u
MAX 10 POWER
10M50DAF484C6GES
U1G
VCCN12
VCCN10
VCCM13
VCCM12
VCCM11
VCCL12
VCCL11
VCCL10
VCCK13
VCCK11
VCCD_PLL1T7
VCCD_PLL2G16
VCCD_PLL3G7
VCCD_PLL4U16
VCCA1R8
VCCA2H15
VCCA3H8
VCCA4T15
VCCINTJ7
VCCA_ADCH7
ADC_VREFH6
ANAIN1G5
ANAIN2J5
VCCIO1AL6
VCCIO1AK7
VCCIO1BM6
VCCIO1BL7
VCCIO2R6
VCCIO2P7
VCCIO2N7
VCCIO2N6
VCCIO3U9
VCCIO3U8
VCCIO3T9
VCCIO3T11
VCCIO3T10
VCCIO4U14
VCCIO4U12
VCCIO4U11
VCCIO4T13
VCCIO4T12
VCCIO5T17
VCCIO5R17
VCCIO5R16
VCCIO5P16
VCCIO5N16
VCCIO6N17
VCCIO6M17
VCCIO6L16
VCCIO6K17
VCCIO6K16
VCCIO6J17
VCCIO6H16
VCCIO7G14
VCCIO7G13
VCCIO7G12
VCCIO7F14
VCCIO7F12
VCCIO8G11
VCCIO8G10
VCCIO8F9
VCCIO8F11
C242
0.1u
C163
0.1u
C23010u
REFGND2DNIL16 30ohm, 3A
C143
0.1u
L26 30ohm, 3A
L8 30ohm, 3A
C181
0.1u
L170.35ohm, 0.3A
C219
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC1P2_VCC VCC1P5_DDR3
VCC2P5_VCCA
VCC1P2_VCCD
VCC1P2
VCC1P8
VCC3P3
VCC2P5
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Decoupling C
DECAB
9 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Decoupling C
DECAB
9 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MAX10 Decoupling C
DECAB
9 25Wednesday, March 11, 2015
C121
4.7u
C178
1u
C157
22n
C122
4.7u
C208
10u
C38
10u
C159
1u
C198
1u
C139
10n
C218
0.1u
C179
22n
C220
1u
C204
1u
C259
1u
C138
10n
C224
0.1u
C203
0.1u
C116
0.1u
C161
1u
C217
1u
C205
10n
C156
10n
C199
1u
C206
0.1u
C140
0.1u
C136
0.1u
C120
0.1u
C155
1u
C226
0.1u
C228
0.1u
C154
1u
C118
0.1u
C160
10n
C221
1u
C90
10u
C119
0.1u
C200
1u
C158
10n
C162
10n
C227
1u
C225
0.1u
C137
1u
C135
1u
C223
0.1u
C202
1u
C262
0.1u
C114
0.1u
C207
10n
C115
10n
C222
4.7u
C229
0.1u
C117
0.1u
C201
1u
C141
0.1u
C209
10u
C180
1u
C197
1u
C196
10n
C261
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
25.00MHz
19.2MHz
VCC3P3_CLKGEN
VCC3P3_CLKGEN
VCC3P3_CLKGEN
VCC3P3
VCC1P5_DDR3VCC3P3_CLKGEN
VCC2P5
VCC2P5VCC3P3_CLKGEN
VCC3P3_CLKGEN
VCC1P5_DDR3VCC3P3_CLKGEN
UB2_CLK_2411
ADC_CLK_107
MAX10_CLK1_507
MAX10_CLK2_507
NET_CLK_2518
DDR3_CLK_507USB_CLK_1919
UB2_CLK_5011
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Oscillator, Clock Generator C
DECAB
10 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Oscillator, Clock Generator C
DECAB
10 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Oscillator, Clock Generator C
DECAB
10 25Wednesday, March 11, 2015
C42
0.1u
Y1
501BAB25M0000CAFR
VCC4
OUT3
GND2
EN1
VCCA VCCB
DIR GND
A B
U33
SN74AVC1T45
3 46
25
1
C257
0.47u
C255
0.47u
U20
Si5350C-B03812-GM
XA1
XB2
CLK013
CLK112
CLK29
CLK38
CLK419
CLK517
CLK616
CLK715
VDD
OA
11
VDD
OB
10
VDD
OC
18
VDD
OD
14
VDD
20G
ND
_EP
21
GND3
GND4
GND5
CLKIN6
GND7
C256
0.47u
L250.35ohm, 0.3A
C63
0.1u
C64
0.1u
C258
0.1u
C43
0.1u
VCCA VCCB
DIR GND
A B
U24
SN74AVC1T45
3 46
25
1
C269
0.47u
C268
0.47u
R105 24.9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UB2 Clock
MAX10 CONFIG Status
CPLD ISP
Place Near CY7C68013A
JTAG Interface
Place near MAX V Place near MAX V
VCCIO = 2.5V
VCCIO = 3.3V
CONF_DONE_DISP
FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
CONF_DONE_DISP
CONF_DONE
CONF_DONE_MAX10NSTATUS_MAX10NCONFIG_MAX10
C_USB_MAX_TDI
C_USB_MAX_TDOC_USB_MAX_TMS
C_USB_MAX_TCK
UB2_CLK_24
C_USB_MAX_TCK
C_USB_MAX_TMS
CONF_DONE
NSTATUS
NCONFIG
CONF_DONE_MAX10
NSTATUS_MAX10
NCONFIG_MAX10
FX2_RESETn
FX2_D_NFX2_D_P
VCC5_USB FX2_WAKEUP
JTAG_TX
FX2_PD4FX2_PD3
FX2_PD0FX2_PD1FX2_PD2
FX2_PD5FX2_PD6FX2_PD7
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
USB_CLK
JTAG_RX
FX2_FLAGCFX2_FLAGB
FX2_WAKEUP
FX2_SLWRnFX2_SLRDn
FX2_FLAGA
FX2_SCLFX2_SDA
FX2_RESETn
FX2_RESETnFX2_SDA
FX2_PB7USB_CLK
C_USB_MAX_TDO
FX2_FLAGB
FX2_FLAGC
FX2_PA1
FX2_PB4
C_USB_MAX_TDI
FX2_PA2
FX2_PA4
FX2_FLAGA
FX2_PB6
FX2_PB2
FX2_PA3
FX2_PA6
FX2_PA7
FX2_PB5
FX2_PB0
FX2_SCLFX2_PB3FX2_PB1
FX2_SLWRn
FX2_PD6
FX2_PD5
FX2_PD4
FX2_SLRDnFX2_PA5
FX2_PD7
CLK_12MHzJTAG_TXJTAG_RX
UB2_CLK_24UB2_CLK_50
JTAG_EN
JTAG_TMSJTAG_TDI
JTAG_TDOJTAG_TCK
FX2_PD3
FX2_PD2
FX2_PD0
FX2_PD1
VCC3P3VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC3P3
VCC1P2 VCC2P5
VCC3P3
VCC1P8
VCC3P3
VCC3P3VCC2P5 VCC1P8
VCC1P2
VCC5_USB
VCC2P5
JTAG_TCK 7
JTAG_TDI 7
JTAG_TMS 7JTAG_TDO 7
UB2_CLK_24 10
NSTATUS 7
CONF_DONE 7
NCONFIG 7
JTAG_EN 7
UB2_CLK_50 10
CLK_12MHz 16
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB Blaster II C
DECAB
11 25Friday, March 13, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB Blaster II C
DECAB
11 25Friday, March 13, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB Blaster II C
DECAB
11 25Friday, March 13, 2015
C2510.1u10V
U39
TLV809K33DBVRGND
1RESET
2VCC
3
R12210K
C2430.1u10V
Q9AO3400
1
2 3
R121 0
Q8 AO3400
1
2 3
R119 0
C2540.1u10V
R242100K
R20610K
R245 10K
C490.1u10V
C2710.1u10V
R110 0
D5 LEDG21
R248 1K
TP1 DNI
R109 0
C2460.1u10V
C2450.1u10V
C2500.1u10V
Bank 25M570ZM100
5M570ZM100
U21-2
IOB2_17B11 IOB2_16C10 IOB2_15C11 IOB2_14D10 IOB2_13D11 IOB2_12
D9 IOB2_11E10 IOB2_10E11
IOB2/CLK2F10
IOB2_9F11 IOB2_8
F9 IOB2_7G10
IOB2/CLK3G11
IOB2_5H10
IOB2_37A1
IOB2_20A10IOB2_19A11
IOB2_35A2
IOB2_33A3
IOB2_30A5IOB2_29A6
IOB2_26A7
IOB2_24A8
IOB2_22A9
IOB2_18B10
IOB2_36B2
IOB2_34B3
IOB2_32B4IOB2_31B5
IOB2_28B6
IOB2_25B7
IOB2_23B8
IOB2_21B9
IOB2_27C6
IOB2_6H11
IOB2_4H9
IOB2_2J10
IOB2_3J11
IOB2_1K11
R239 2K
TP6 DNI
R238 2K
D7 LEDG21
C2700.1u10V
U19
CY7C68013A_VFBGA
RDY0A1
RDY1B1
XTALINC1
AVCCD1
DMINUSE1
AGNDF1
VCCG1
GNDH1
PD7A2
CLKOUTB2
XTALOUTC2
AVCCD2
DPLUSE2
AGNDF2
IFCLKG2
RESERVEDH2
PD5A3PD4B3
PD6C3
SCLF3
SDAG3
PB0H3
GNDA4
GNDB4
GNDC4
PB1F4
PB3G4PB2H4
VCCA5
VCCB5
PB6F5PB5G5PB4H5
PD3A6PD2B6
PA7C6
PA4F6
PA1G6
PB7H6
PD1A7
WAKEUPB7
PA6C7
GNDD7
VCCE7
PA3F7
CTL1G7CTL0H7
PD0A8
RESETB8
PA5C8
GNDD8
VCCE8
PA2F8
PA0G8
CTL2H8
VCCC5
C2530.1u10V
C2720.1u10V
5M570ZM100Bank 1
5M570ZM100
U21-1
TMSJ1
TDIJ2
IOB1_1B1
IOB1_3C1 IOB1_2C2
IOB1_6D1 IOB1_5D2 IOB1_4D3
IOB1/CLK1E1
IOB1_7F1
IOB1/CLK0F2
IOB1_10F3
IOB1_8G1
IOB1_9G2
IOB1_11H1
IOB1_13H2 IOB1_12H3
IOB1_14L1
TCKK1
TDOK2
IOB1/DEV_CLRNK8 IOB1/DEV_OEL8
IOB1_24J6
IOB1_30K10
IOB1_16K3
IOB1_18K4
IOB1_20K5
IOB1_23K6
IOB1_26K7
IOB1_28K9
IOB1_29L10
IOB1_31L11IOB1_15
L2
IOB1_17L3
IOB1_19L4
IOB1_21L5
IOB1_22L6
IOB1_25L7
IOB1_27L9
TP5 DNI
D8 LEDG21
R228 120
Q4UTC8050DNI
1
23
R11310K
J10
Mini-USB-B
VBUS1
D-2
D+3
ID4
GND5
SHIELD16
SHIELD27
C2440.1u10V
R82 10
Q1 AO3400
1
2 3
R120 0
C2520.1u10V
C2670.1u10V
C2640.1u10V
C2630.1u10V
C2660.1u10V
C2490.1u10V
R118 0
R18810K
R108 0
R234 120
R102 1KDNI
R247 0
R117 10DNI
R93 1M
R24620K
TP4 DNITP3 DNI
U36
TPD2EUSB30DRTRD-
2D+1
GND3
Power5M570ZM100
5M570ZM100
U21-3
VCCIO1E3
VCCIO1J4
GNDA4GNDE2GNDE4GNDG4GNDH5
VCCINTG3
VCCIO1J8
GNDC5
GNDD5
GNDD7
GNDE8
GNDG8
GNDH7
GNDJ5
VCCINTC7
VCCINTE9
VCCINTJ7
VCCIO2C4
VCCIO2C8
VCCIO2G9
R11410K
R216 120
C2650.1u10V
C50 4.7n50V
TP2 DNI
R101 1K
C550.1u10V
R19710K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Header GPIOP8 P9
Header Analog Input
GPIO1_D21 is connected to MAX 10 PLL output pin
AIN3AIN5
AIN6
AIN1AIN2AIN0
AIN4
GPIO0_D0 GPIO0_D1
GPIO0_D43
GPIO0_D4GPIO0_D2
GPIO0_D6
GPIO0_D10GPIO0_D8
GPIO0_D14GPIO0_D12
GPIO0_D16
GPIO0_D20GPIO0_D18
GPIO0_D22
GPIO0_D26GPIO0_D24
GPIO0_D30GPIO0_D28
GPIO0_D32
GPIO0_D36GPIO0_D34
GPIO0_D38
GPIO0_D42GPIO0_D40
GPIO0_D3
GPIO0_D13GPIO0_D11GPIO0_D9GPIO0_D7GPIO0_D5
GPIO0_D23GPIO0_D21GPIO0_D19GPIO0_D17GPIO0_D15
GPIO0_D25
GPIO0_D35GPIO0_D33GPIO0_D31GPIO0_D29GPIO0_D27
GPIO0_D41GPIO0_D39GPIO0_D37
PWR_BUT SYS_RESET_nGPIO1_D0GPIO1_D2
GPIO1_D8GPIO1_D10
GPIO1_D4GPIO1_D6
GPIO1_D12GPIO1_D14
GPIO1_D20
GPIO1_D16GPIO1_D18
GPIO1_D7GPIO1_D5
GPIO1_D11GPIO1_D13
GPIO1_D19GPIO1_D17
GPIO1_D3GPIO1_D1
GPIO1_D9
GPIO1_D15
GPIO1_D21 GPIO1_D22
VCC3P3VCC5
VCC1P8_VCCADC
VCC3P3 VCC5
VCC1P8
VCC3P3
GPIO0_D[43..0]4,7
GPIO1_D[22..0]4,7
AIN[6..0]3
SYS_RESET_n4
PWR_BUT4
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Expansion Headers - BBB Headers C
DECAB
12 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Expansion Headers - BBB Headers C
DECAB
12 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Expansion Headers - BBB Headers C
DECAB
12 25Wednesday, March 11, 2015
R2010K
C10.1u10V
L4 30ohm, 3A
P8
HEADER 23x2
13579
111315171921232527293133353739414345
246810121416182022242628303234363840424446
C410u6.3V
P9
HEADER 23x2
13579
111315171921232527293133353739414345
246810121416182022242628303234363840424446
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
place close to DDR3 chip
Note: place a pull down resistor on the FLASH_DCLK wire at the Master
DDR3_BA0DDR3_BA1DDR3_BA2
DDR3_CK_nDDR3_CK_p
DDR3_RESET_n
DDR3_CKE
DDR3_DQS_p0DDR3_DQS_n0DDR3_DQS_p1DDR3_DQS_n1
DDR3_RZQ
DDR3_DM1DDR3_DM0
DDR3_A0DDR3_A1DDR3_A2DDR3_A3DDR3_A4DDR3_A5DDR3_A6DDR3_A7DDR3_A8DDR3_A9DDR3_A10DDR3_A11DDR3_A12DDR3_A13DDR3_A14
DDR3_DQ15DDR3_DQ14DDR3_DQ13DDR3_DQ12DDR3_DQ11DDR3_DQ10DDR3_DQ9DDR3_DQ8DDR3_DQ7DDR3_DQ6DDR3_DQ5DDR3_DQ4DDR3_DQ3DDR3_DQ2DDR3_DQ1DDR3_DQ0
DDR3_VREF
FLASH_RESET_nFLASH_DATA0
FLASH_DATA2FLASH_DATA1
FLASH_DATA3 FLASH_DCLK
FLASH_NCSO
FLASH_DCLK
FLASH_RESET_n
FLASH_NCSO
FLASH_DATA0
FLASH_DATA1
FLASH_DATA2
FLASH_DATA3
VCC1P5_DDR3
DDR3_VREF
VCC1P5_DDR3
VCC1P5_DDR3
VCC1P5_DDR3
DDR3_VREF
VCC1P5_DDR3
GND
VCC3P3
GND
VCC3P3
GND
VCC3P3
DDR3_CK_p 5DDR3_CK_n 5DDR3_CKE 5
DDR3_CS_n 5DDR3_RESET_n 5DDR3_WE_n 5DDR3_RAS_n 5DDR3_CAS_n 5
DDR3_ODT 5
DDR3_BA[2..0] 5
DDR3_DQS_p[1..0] 5,7
DDR3_DQ[ 15..0] 5
DDR3_A[14..0] 5
DDR3_DQS_n[1..0] 5,7
DDR3_DM[1..0] 5
FLASH_DCLK 4FLASH_NCSO 4
FLASH_DATA[3..0] 4
FLASH_RESET_n 4
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECAB
13 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECAB
13 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
DDR3 SDRAM, QSPI Flash C
DECAB
13 25Wednesday, March 11, 2015
U12
MT41K256M16HA-125 IT:E
VSSA9
VDDB2
NC3L1
UDMD3
VSSB3
VDDD9
VSSE1
VSSQB1
DQ0E3
LDME7
VSSQB9
VDDQA1
VDDQA8
DQ2F2
LDQSF3
DQ3F8
DQ1F7
VSSQD8VSSQD1
DQ6G2
LDQSnG3
VDDG7
VSSG8
VSSQE2
VREFDQH1
VDDQC1
DQ4H3
DQ7H7
DQ5H8
VDDQC9
VSSJ8
RASJ3
CLKJ7
VSSJ2
ODTK1
VDDK8
CASK3
CLK_nK7
CKEK9
CSL2
WEL3
A10/APL7
ZQL8
VSSM1
BA0M2
BA2M3
NC4L9
VREFCAM8
VSSM9
A3N2
A0N3
A12/BC_nN7
BA1N8
VSSP1
A5P2
A2P3 A1P7
A4P8
VSSP9
A7R2
A9R3
A11R7
A6R8
VSST1
A13T3
A8T8
VSST9
A14T7
VDDQD2
VDDQE9
VDDQF1
VDDQH2
VDDQH9
VDDK2
VDDN1
VDDN9
VDDR1
VDDR9
VSSQE8
VSSQF9
VSSQG1
VSSQG9
NC1J1
NC2J9
DQ8D7
DQ9C3
DQ10C8
DQ11C2
DQ12A7
DQ13A2
DQ14B8
DQ15A3
UDQSC7
UDQSnB7
RESETT2
NC5M7
R235 DNI
R91 DNI
R107 DNI
C239
0.1u
DNI
R215 100
R112 DNI
U37
N25Q512A83GSF40F
HOLD_n/DQ31
VCC2
DNU_13
DNU_24
DNU_35
DNU_46
S_n7
DQ18
W_n/Vpp/DQ29VSS10DNU_511DNU_612DNU_713DNU_814DQ015C16
C600.1u10V
C194
2.2n
R90 2K
C132
0.1u
C216
2.2n
C214
10n
C193
0.47u
C133
2.2n
C151
0.1u
R2271K
DNI
C153
10n
R106 DNI
C215
0.1u
R213 4.7K
C176
4.7n
C240
0.47u
R111 2k
R92 10K
C241
0.47u
C134
10n
C152
3.3n
C177
0.1u
C175
2.2n
C150
0.1u
C174
2.2n
C173
2.2n
R214240
R811K
DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Micro SD Card
SD_SEL = 0, VCCIO_SD = 3.3VSD_SEL = 1, VCCIO_SD = 1.8V
ex_SD_CMD
ex_SD_CLK
SD_DAT1SD_DAT0
SD_DAT3SD_DAT2
SD_CMD
SD_CLKSD_FB_CLK
SD_D0_DIRSD_D123_DIR
SD_CMD_DIR
ex_SD_DAT1ex_SD_DAT0ex_SD_DAT3ex_SD_DAT2
ex_SD_CMD
ex_SD_DAT1
ex_SD_DAT2ex_SD_DAT3
ex_SD_DAT0
ex_SD_CMD
ex_SD_CLKex_SD_DAT0ex_SD_DAT1ex_SD_DAT2ex_SD_DAT3
SD_SEL
VCC3P3 VCC3P3_SD
VCCIO_SD
VCC3P3_SD
VCCIO_SDVCC1P5_DDR3
VCC3P3
VCC2P8
VCC1P8
VCC1P8
VCCIO_SD
SD_DAT[3..0]5
SD_CMD5
SD_CLK5
SD_D0_DIR5
SD_D123_DIR5
SD_CMD_DIR5
SD_FB_CLK5
SD_SEL4
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card C
DECAB
14 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card C
DECAB
14 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SD Card C
DECAB
14 25Wednesday, March 11, 2015
RN1
10K
12345
678
VCCIO_SD
R129 10K
C660.1u10V
C610.1u10V
123
11
45678
109
12 13 14 15 16
J11
SOC
KET-
SD_C
ARD
_3DAT3CMDVCCCLKVSSDAT0DAT1
DAT2
CD
VSS
VSS
CD2 VSS
VSS
VSS
VSS
R1301K
U25
TPS22912CYZVR
VINA2
ONB2
VOUTA1
GNDB1R250 1K
DNI
R1260
U22
SN74AVCA406L
VCCAA5
DATA0AB2
DATA1AA2
DATA2AB4
DATA3AA4
CMDAB1
CLKAA3
CLK-fA1
GNDB3
GNDC3
DATA0BD2
DATA1BD1
DATA2BC4
DATA3BD4
CMDBC2
CLKBD3
VCCBD5
DATA0_dirC5
DATA123_dirC1
CMD_dirB5
C6510u
Q10UTC8050DNI
1
23
L9 30ohm, 3A
R127 0
R128 0DNI
U26
TPS22910AYZVR
VINA2
ONB2
VOUTA1
GNDB1
C68
10u
C670.1u10V
R252 1KDNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MIPI Interface
MIPI Control Interface
MIPI_MCLK_TAVDD
AFVCC
MIPI_MD_n2MIPI_MD_p2
MIPI_RESET_n_T
MIPI_MD_n0MIPI_MD_p0
MIPI_MD_n3MIPI_MD_p3
MIPI_MD_n1MIPI_MD_p1
MIPI_I2C_SCL_TMIPI_I2C_SDA_TMIPI_CORE_EN_T
MIPI_MC_nMIPI_MC_p
DOVDD
AVDD12
MIPI_WP_T
MIPI_LP_MD_p1MIPI_LP_MD_n1 MIPI_MD_n1
MIPI_MD_p1
MIPI_LP_MD_p2MIPI_LP_MD_n2 MIPI_MD_n2
MIPI_MD_p2MIPI_LP_MD_n3MIPI_LP_MD_p3 MIPI_MD_p3
MIPI_MD_n3
MIPI_MC_pMIPI_MC_n
MIPI_I2C_SDA
MIPI_I2C_SCL
MIPI_MD_n0MIPI_MD_p0
MIPI_LP_MD_n0MIPI_LP_MD_p0
MIPI_LP_MC_pMIPI_LP_MC_n
MIPI_RESET_n
MIPI_MCLK
MIPI_WP
MIPI_CORE_EN
MIPI_I2C_SCL
MIPI_I2C_SDA MIPI_I2C_SDA_T
MIPI_WP_T
MIPI_RESET_n_T
MIPI_MCLK_T
MIPI_CORE_EN_T
MIPI_I2C_SCL_T
GND
GND
VCC1P2
VCC1P8
VCC2P8
GND
VCC2P5
VCC2P5 VCC2P5
VCC2P5
VCC2P5
VCC2P5
VCC1P8 VCC1P8 VCC1P8
VCC1P8 VCC1P8
DOVDDVCC2P5
DOVDD
VCC2P8
MIPI_I2C_SDA3
MIPI_I2C_SCL3
MIPI_MD_p[3..0]3
MIPI_MD_n[3..0]3
MIPI_MC_n7
MIPI_MC_p7
MIPI_MCLK3
MIPI_CORE_EN3
MIPI_WP3
MIPI_RESET_n3
MIPI_LP_MC_p7
MIPI_LP_MD_p[3..0]6
MIPI_LP_MD_n[3..0]6
MIPI_LP_MC_n7
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MIPI Interface C
DECAB
15 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MIPI Interface C
DECAB
15 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
MIPI Interface C
DECAB
15 25Thursday, March 19, 2015
R153150
R132150
C700.1u10V
R9 0
C7310u6.3V
R1049.9
D1
SD107WS-TP
21
R349.9
R3349.9
R136 0
R249.9
R1249.9
R1149.9
J4
HEADER 15X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
R131150
R163 0DNI
R137150
R4 0
R141150
R8 0
L2 30ohm, 3A
R35 0
C6910u6.3V
R13 0
C720.1u10V
R23 0
R2449.9
R148 49.9
C7133p
DNI50V
D12
SD107WS-TP
21
R649.9
R139 0
R3649.9
D2
SD107WS-TP
21
R549.9
D10
SD107WS-TP
21
R7 0
L1 30ohm, 3A
R152 49.9
R25
560
R15 49.9
R134 49.9
D11
SD107WS-TP
21
R158150
R140
560
R150 49.9
R149150
R1512K
R133150
R262KDNI
R135 0DNI
R159150
R1 0
R138150
Q7AO34001
23
R14 0
R34 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI TX
Default : I2C Address 0x72/0x73
HDMI TX
HDMI Audio Interface
From MAX
I2C Interface
Note:Place Capacitor near ADV7513 DVDD pins
Note:Place Capacitor near ADV7513 AVDD pins
Note:Place Capacitor near ADV7513 PVDD and BGVDD pin
Note:Place Capacitor near ADV7513 DVDD_3V
TMDS_TX_p1TMDS_TX_n1TMDS_TX_p2TMDS_TX_n2
TMDS_TX_p0TMDS_TX_n0
TMDS_TX_p0TMDS_TX_n0
TMDS_TX_p1TMDS_TX_n1 TMDS_TX_n1
TMDS_TX_p1
TMDS_TX_p2TMDS_TX_n2 TMDS_TX_n2
TMDS_TX_p2
TMDS_TXC_pTMDS_TXC_n TMDS_TXC_n
TMDS_TXC_p
HDMI_TX_D0HDMI_TX_D1HDMI_TX_D2HDMI_TX_D3HDMI_TX_D4HDMI_TX_D5HDMI_TX_D6HDMI_TX_D7
HDMI_TX_D8
HDMI_TX_D16
HDMI_TX_CLK_THDMI_TX_DE
HDMI_TX_VSHDMI_TX_HS
HDMI_I2C_SDA_THDMI_I2C_SCL
DDCSCLDDCSDA
CEC
HDMI_TX_D9
HDMI_HPD
HDMI_TX_D10HDMI_TX_D11HDMI_TX_D12HDMI_TX_D13HDMI_TX_D14HDMI_TX_D15
HDMI_TX_D17HDMI_TX_D18HDMI_TX_D19HDMI_TX_D20HDMI_TX_D21HDMI_TX_D22HDMI_TX_D23
TMDS_TXC_pTMDS_TXC_n
TMDS_TX_p0TMDS_TX_n0
DDCSDADDCSCLCEC_IO
HDMI_HPD
CEC_CLK
CEC_CLK
HDMI_I2C_SCL
HDMI_SPDIFHDMI_MCLK
HDMI_I2S0HDMI_I2S1HDMI_I2S2HDMI_I2S3
HDMI_SCLKHDMI_LRCLK
CECDDCSCL
DDCSDAHDMI_HPD
HDMI_TX_INT
CLK_12MHz
HDMI_TX_CLK_T
HDMI_I2C_SDA HDMI_I2C_SDA_T
VCC1P8 VCC1P8_DVDD
VCC1P8 VCC1P8_AVDD
VCC1P8 VCC1P8_PVDD
VCC3P3
VCC1P8_DVDD
VCC3P3_DVDD
VCC1P8_PVDD
VCC1P8_AVDD
VCC3P3_DVDD
VCC5
VCC3P3_DVDD
VCC1P8_AVDD
VCC1P8
GND_EXT
VCC5
VCC1P8
VCC3P3VCC1P2
VCC3P3VCC1P2
VCC3P3_DVDDVCC1P8
VCC1P8
HDMI_TX_HS6
HDMI_TX_VS6
HDMI_TX_DE6
HDMI_TX_D[23..0]6
HDMI_TX_INT6
CLK_12MHz11
HDMI_I2C_SDA6
HDMI_I2C_SCL6
HDMI_I2S[3:0]6
HDMI_MCLK6
HDMI_LRCLK6
HDMI_SCLK6
HDMI_TX_CLK6,7
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HDMI TX C
DECAB
16 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HDMI TX C
DECAB
16 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
HDMI TX C
DECAB
16 25Thursday, March 19, 2015
C1010.1u10V
D3 RClamp0514P1
84
6
392
57
10
R52 2K
C770.1u10V
R176 887
L3 10uH
74479777310
R165 0DNI
C19
0.1u
R1570
R18
4.99KDNI
C610u6.3V
L10 10uH
74479777310
C150.1u10V
R161 49.9DNI
R142 22DNI
R30
4.99K
C9810u6.3V
D13DFLS1150-7DNI
L12 10uH
74479777310
C32 0.1u25V
R1562K
D4 RClamp0514P
1
84
6
392
57
10
R59 10K
C1000.1u10V
C1120.1u10V
U31
TPD4E001_0
13246
5
C760.1u10V
SHELL
GND
CEC
D2-
D1-
CK-
D1+
D0+
SDA
CK+
GND
GND
GND
D0-
D2+
+5V
GND
HPD
SCL
J6
1
23
4
56
7
89
10
1112
13151617
1819
20212223
R166 2KDNI
R53 2K
Q6AO3400
DNI1
2 3
R19
4.99K
C9
0.1u
C7410u6.3V
VCCA VCCB
DIR GND
A B
U4
SN74AVC1T45
DNI
3 46
25
1
L11 10uH
74479777310 C990.1u10V
R62 1M
C11110u6.3V
C830.1u10V
U5
ADV7513BSWZ
D062
D161
D260
D359
D458
D557
D656
D755
D854
D952
D1050
D1149
D1248
D1347
D1446
D1545
D1644
D1743
D1842
D1941
D2040
D2139
D2238
D2337
CLK53
DE63
HSYNC64
VSYNC2
R_EXT14
HPD16
SPDIF3
MCLK4
I2S05
I2S16
I2S27
I2S38
SCLK9
LRCLK10
PD22
TXC+18
TXC-17
TX0+21
TX0-20
TX1+24
TX1-23
TX2+27
TX2-26
INT28
SDA36
SCL35
DDCSDA34
DDCSCL33
CEC30
CEC_CLK32
DVDD_3V29
DVDD11
DVDD211
DVDD331
DVDD451
PVDD12
BGVDD13
AVDD115
AVDD219
AVDD325
EPAD_GND65
R15427KDNI
R160 2KR421 0
R1550
C1130.1u10V
C880.1u10V
R162 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LINE IN
LINE OUT
Audio CODEC Interface
Audio Control Interface
Default :I2C Address 0x30/31
LINE-IN for ADC
Audio LINE-IN to MAX10 ADC
LINE_IN_L
LINE_IN_R
AUDIO_GPIO_MFP5
AUDIO_SCLK_MFP3
AUDIO_MISO_MFP4
AUDIO_SCL_SS_n
AUDIO_SDA_MOSI
AUDIO_DIN_MFP1
AUDIO_BCLK
AUDIO_DOUT_MFP2
AUDIO_RESET_n
AUDIO_MCLK
AUDIO_WCLK
AUDIO_SPI_SELECTLINE_OUT_R
LINE_OUT_L
LINE_IN_L_AUD
LINE_IN_R_AUD
AUDIO_RESET_nAUDIO_SPI_SELECT
AUDIO_SDA_MOSI
AUDIO_SCL_SS_n
LINE_OUT_L
LINE_OUT_R
LINE_AC_L
LINE_IN_R_AUD
LINE_IN_L
LINE_AC_L
LINE_AC_L
LINE_IN_L_AUD
LINE_IN_L_ADC
VCC_AUD
VCC_AUD_IO VCC_AUD
VCC_AUD
VCC3P3VCC1P5_DDR3 VCC_AUD_IO
VCC_AUD_IO
VCC_AUD_IO
VCC2P5_VCCAADC
VCC2P5_VCCAADC
VCC5_ADC
VCC5_ADC
VCC5_ADC
VCC2P5_VCCAADC
AUDIO_WCLK5
AUDIO_SCLK_MFP35
AUDIO_MISO_MFP45
AUDIO_SPI_SELECT5
AUDIO_GPIO_MFP55
AUDIO_RESET_n5
AUDIO_MCLK5
AUDIO_DOUT_MFP25
AUDIO_DIN_MFP15
AUDIO_SDA_MOSI5
AUDIO_SCL_SS_n5
AUDIO_BCLK5
LINE_IN_L_ADC3
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Audio CODEC C
DECAB
17 25Friday, March 13, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Audio CODEC C
DECAB
17 25Friday, March 13, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Audio CODEC C
DECAB
17 25Friday, March 13, 2015
R582K
C1280.1u10VDNI
J2PHONE JACK B
L1
R2
GN
D3
NC
R4
NC
L5
R187 100
C107 1u10V
C21010u6.3V
R572K
R19147KDNI
J1PHONE JACK G
L1
R2
GN
D3
NC
R4
NC
L5
C1830.1u10V
L19 30ohm, 3A
R66 4.7K
R55 0
R193 47K
DNI
R1901K
C230.1u10V
R6710K
C129 1u
10V DNI
C10847n25V
+
-
U8A
OPA1612AIDR
31
84
2
C97 1u
10V
R253 0
R17447KDNI
+
-
U8B
OPA1612AIDR
57
84
6
R25510
C1670.1u10V
C109 1u10V
U9
TLV320AIC3254_0
MCLK1
BCLK2
WCLK3
DIN/MFP14
DOUT/MFP25
IOVD
D6
IOVS
S7
SCLK/MFP38
SCL/SS9
SDA/MOSI10
MISO/MFP411
SPI_SELECT12
AVSS
17
REF18
MICBIAS19
IN3_L20
IN3_R21
LOL22
LOR23
AVD
D24
HPL25
IN1_L13
IN1_R14
IN2_L15
IN2_R16
GPIO/MFP532
RESET31
LDO_SELECT30
DVD
D29
DVS
S28
HPR27
LDO
IN26
PPAD
33
C18422u6.3V
R19247KDNI
R54 0DNI
R186 100
C14610u6.3V
C16822u6.3V
R182 47K
DNI
R5610KDNI
C18210u6.3V
C1660.1u10V
R183 0
C10647n25V
R18547K
L7 30ohm, 3A
C96 1u
10V
C1450.1u10V
R18447K
R17547KDNI
C280
1p
C130 1u
10V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Analog interface , so using 3.3v
NET_TX_CLK
NET_TXD0NET_TXD1NET_TXD2NET_TXD3
NET_RXD0NET_RXD1NET_RXD2NET_RXD3
NET_TX_EN
NET_RX_CLK
NET_RX_ERNET_RX_DV
NET_COLNET_CRS
NET_RESET_n
NET_MDIONET_MDC
ETD_PETD_N
ERD_PERD_N
NET_CLK_25
LED_ACTIVE
NET_PCF_EN
LED_LINK
SPEED
LED_ACTIVE
NET_VCC3P3
GND
VCC3P3 NET_VCC3P3
GND
GND
VCC2P5 NET_VCC2P5
GND
NET_VCC2P5
NET_VCC2P5
GND GND
NET_VCC3P3 NET_VCC3P3
GND GND
NET_VCC3P3
GND
GND
NET_VCC3P3
GNDNET_VCC3P3
NET_VCC3P3
GND_S
NET_RX_CLK 7
NET_TX_EN 7
NET_RESET_n 7
NET_MDIO 3
NET_TXD[3..0]3
NET_RXD[3..0]3
NET_RX_ER 3NET_RX_DV 3
NET_MDC 3
NET_COL 3
NET_CLK_25 10
NET_TX_CLK 7
NET_CRS 3
NET_PCF_EN 7
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Ethernet C
DECAB
18 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Ethernet C
DECAB
18 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Ethernet C
DECAB
18 25Wednesday, March 11, 2015
C33
0.1uC212
0.1u
C186
0.1u
R65
49.9
R261 0
DNI
R231 2.2K
R224 4.87K
R74 2.2KDNI
L23 BEAD
R236 1.5K
L24 BEAD
R201
110
R207 2.2K
R80 2.2K
U14
DP83620_3
TX_CLK1
TXD_03
TXD_14
TXD_25
TXD_36
TX_EN2
MDIO30
MDC31
COL42
CRS/CRS_DV40
RX_DV39 RX_ER41
RXD_343 RXD_244 RXD_145 RXD_046
RX_CLK38
PCF_EN22
IO_VDD32
IO_VDD48
TD+17
TD-16
RD+14
RD-13
X134
X233
RESERVED225
LED_ACT26
LED_SPEED/FX_SD27
LED_LINK28
CLK_OUT24
RESERVED123
ANAVSS18
RESERVED437
CLK_OUT_EN21
VREF20
IO_CORE_VSS35
IO_VSS47
CD_VSS15
ANA33VDD19
RESERVED336
RESET_N29
PWR_DOWN/INTN7
TCK8TDO9TMS10TRST#11TDI12
DAP49
R202
2.2K
C46
0.1u
R70
49.9
R64
49.9
R237 2.2K
R225
0
R210
0
C234
0.1u
R233
110
C235
10u
R260 0
J7
480749001
TD+3
TD-4
CTT5
RD+7
RD-8
CTR6
LA12
LC11
RA1
RC2
CHS_GND9 CHS_GND
10
SHIELD214SHIELD113
R241 2.2K
R71
49.9
C185
0.1u
C211
0.1u
C233
10u
R45
0
R232
2.2K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Notes: Put the TPD4S012 close to each USB connector.
CAD Notes: Put the TUSB1210 close to FPGA.
Default Connection: ULPI with clock output mode
USB_DPUSB_DM
USB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7
TUSB1210_CLK_R
GND
GND
VCC5 USB_VCC5VCC1P2
GND
USB_VCC5
GND
GND
GND
VCC1P8_USB
USB_REG1P5
USB_REG3P3
GND
USB_REG1P5
GND
USB_REG3P3
VBAT
VCC1P8 VCC1P8_USB
GND
VCC3P3 VBAT
GND
VCC1P8_USB
GNDGND
VCC1P8_USBVCC1P2
VCC1P8_USBVCC1P2
GND
GND
USB_FAULT_n6
USB_DATA[7..0]6
USB_STP6
USB_NXT6USB_DIR6
USB_CS6USB_RESET_n6
USB_CLK_19 10
USB_CLOCK7
USB_CLKOUT_NOPLL6
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB PHY C
DECAB
19 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB PHY C
DECAB
19 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
USB PHY C
DECAB
19 25Thursday, March 19, 2015
CPEN1DNI
R69 22
R63
1M
C187
4.7u
R60 0
U17
TPS2553DRVR
IN6
GND5
EN4
FAULT_n3
ILIM2
OUT1
EP_GND7
C2364.7u
U13
TUSB1210
REFCLK1
NXT2
DATA03
DATA14
DATA25
DATA36
DATA47
NC
18
DATA59
DATA610
CS11
VDD
1512
DATA713
CFG14
NC
215
NC
316
CPEN17
DP18DM19
VDD
3320
VBAT
21
VBUS22
ID23
NC
424
NC
525
CLOCK26
RESETB27
VDD
1828
STP29
VDD
1830
DIR31
VDD
IO32
GN
D33
C110
0.1u
C170
0.1u
VCCA VCCB
DIR GND
A B
U10
SN74AVC1T45
3 46
25
1
C281
1n
C191
0.1u
R21210K
DNI
L20 60ohm 3A
R73 0
U34TPD4S012
D+
1
D-
2
ID3
GN
D4
NC
5
VBU
S6
R68 0
R2090
C282
0.1u
R2050DNI
R83820
C237
0.1u
C190
0.1u
R211
0
C131
0.1u
C188
0.1u
C1724.7u
R7910k
R196 0
R22620K
C1894.7u
R208 0DNI
C238
0.1u
C169
0.1u
C1924.7u
C213
0.1u
C171
0.1u
R61
2K
DNI
VBUS
D-
D+
ID
GND
Mini-USB AB
J8
Jack-Mini-USB-AB_3123
5
76
4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Notes: the input voltage Vin range (-6.25V --- 8.75V)
Notes: the input voltage Vin range (-6.25V --- 8.75V)
Notes: the output voltage Vo range (0.0V --- 3.0V)
Notes: the output voltage Vo range (0.0V --- 3.0V)
CAD Notes:Put the 1pF caps close to MAX10 pin.
CAD Notes:Put the 1pF caps close to MAX10 pin.
Notes: Amplifier output voltage Vo=(6.25+Vin)/5
Notes: Amplifier output voltage Vo=(6.25+Vin)/5
ANAIN2_SMA
ANAIN2_VOUT2
ANAIN1_SMA
ANAIN1_VOUT2
VCC3P3VCC2P5_VREF
VCC5_ADCVCC5
VCC5_ADC
VCC5_ADC
VCC2P5_VREF
VCC2P5_VREF
ANAIN2 8
ANAIN1 8
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SMA Connectors & Difference Amplifier C
DECAB
20 25Monday, March 16, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SMA Connectors & Difference Amplifier C
DECAB
20 25Monday, March 16, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
SMA Connectors & Difference Amplifier C
DECAB
20 25Monday, March 16, 2015
C165
0.47u
C86
0.1u
C127
0.1u
L13 60ohm 3A
C104
0.1u
C27
1p
C95
1u
R1891
U3
INA159AIDGKR
REF11
IN-2
IN+3
V-4
SENSE5
OUT6
V+7
REF28
C10310u
C14410u
C87
10u
U32
REF3125
VIN1
VOUT2
GND3
U7
INA159AIDGKR
REF11
IN-2
IN+3
V-4
SENSE5
OUT6
V+7
REF28
J3
Analog IN
J5
Analog IN
C93
1u
R46
10
C9410u
C28
1p
R44
10
C142
1u
C105
10u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Accelerometer
Digital Gsensor
G_SENSOR_SCLK_EG_SENSOR_SDI_EG_SENSOR_CS_n_EG_SENSOR_SDO_E
G_SENSOR_INT1_EG_SENSOR_INT2_E
G_SENSOR_INT1_EG_SENSOR_INT2_E
G_SENSOR_SCLK_E
G_SENSOR_SDI_E
G_SENSOR_CS_n_EG_SENSOR_SDO_E
G_SENSOR_SDI
G_SENSOR_SCLKG_SENSOR_CS_nG_SENSOR_SDO
G_SENSOR_INT1G_SENSOR_INT2
VCC2P5 VCC2P5_Gsensor
VCC2P5_Gsensor
VCC2P5_GsensorVCC1P2
G_SENSOR_SDO 6
G_SENSOR_SDI 6
G_SENSOR_INT1 6G_SENSOR_INT2 6
G_SENSOR_SCLK 6
G_SENSOR_CS_n 6
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Accelerometer C
DECAB
21 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Accelerometer C
DECAB
21 25Thursday, March 19, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Accelerometer C
DECAB
21 25Thursday, March 19, 2015
U30
LSF0108
GND1
Vref_A2
A13
A24
A35
A46
A57
A68
A79
A810
B811B712B613B514B415B316B217B118Vref_B19EN20
EP21
U6
LIS2DH12TR
SCL/SPC1
SDA/SDI/SDO4
CS2
SDO/SA03
Res5
GN
D6
GN
D7
GN
D8
INT112
INT211
Vdd
9
Vdd_
IO10
R412301
R414301
C285
0.1u
R408200K
R410301
R416301
R420301
R415301
R419301
C284
10u
C418 0.1u
R409301
R411301
R413301
L280.35ohm, 0.3A
C419 0.1u
R418301
R417301
C283
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LED*s are ~ 1.4" to1.6" away from the sensor
"T" formationconfiguration
Si1143
or place some other ICs to Isolate it?
Default : I2C Address 0xB4/0xB5
Proximity/Ambient Light Sensor
Note:keep the seneor close to the "hot" area on board
Note:keep the seneor away from heat area
Default : I2C Address 0x80/0x81LIGHT_I2C_SCLLIGHT_I2C_SDALIGHT_INT
VCC3P3
VCC5
VCC3P3 VCC3P3_Si1143 VCC3P3_Si1143
VCC3P3
VCC3P3
VCC3P3_HDC1000
VCC3P3_HDC1000
VCC3P3_LM71
VCC3P3_HDC1000LIGHT_INT 4
LIGHT_I2C_SDA 4
LIGHT_I2C_SCL 4
TEMP_CS_n 4
TEMP_SIO 4
TEMP_SC 4
RH_TEMP_I2C_SDA4RH_TEMP_I2C_SCL4
RH_TEMP_DRDY_n4
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECAB
22 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECAB
22 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Gesture,Humidity,Temperature Sensors C
DECAB
22 25Wednesday, March 11, 2015
R43
4.99K
R1942.2K
C149
0.1u
U11
HDC1000YPAR
SCLA1
VDDB1
ADR0C1
ADR1D1DRDYn
D2DNC
C2GNDB2
SDAA2
DS1
SFH4056NQ
21
R249
47
L22
BEAD
R42
4.99K
C10
0.1u
C273
100u
R2042.2K
DS2
SFH4056NQ
21
U35
LM71CIMF
CS_n1
GND2
SIO3
SC4
VCC5
L14 BEAD
R2032.2K
Si1143
U28
SDA1 SCL2
VDD3
INT4
DNC_15
LED26
LED37
GND8
LED19
DNC_210
R41
4.99K
L5 BEAD
DS3
SFH4056NQ
21
(1/4" dia, 3/32" tall)
O-R1
Isolation O-ring
C248
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Default : I2C Address 0x37
LED
KEY
SWITCH
KEY1KEY0
SW1
SW0
LED0LED1LED2LED3
LED4LED5LED6LED7
VCC3P3
VCC3P3_CS
VCC3P3_CS
VCC1P5_DDR3
VCC1P5_DDR3 VCC1P5_DDR3
VCC3P3
VCC3P3
CAP_SENSE_I2C_SCL4 CAP_SENSE_I2C_SDA4
LED[7..0]6
SW[1..0]5
KEY[1..0]5
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
CapSense Controller, Buttons, Switchs C
DECAB
23 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
CapSense Controller, Buttons, Switchs C
DECAB
23 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
CapSense Controller, Buttons, Switchs C
DECAB
23 25Wednesday, March 11, 2015
RN2
120
1234 5
678
C275
0.1u
R251100K
LED7LEDB
21
ShieldSensor
B1
CapSense Button 8mm RoundDNI
1 2
U38
CY8CMBR3102-SX1I
I2C_SCL1
I2C_SDA8
CMOD2
VDD
4
VCC
3VS
S5
CS1/PS1/GPO0/SH6
CS0/PS07
LED0LEDB
21
LED5LEDB
21
ShieldSensor
B0
CapSense Button 8mm RoundDNI
1 2
R173 120
R243 560
C276
0.1u
SW1
SLIDE SW
123
4
5
KEY0
TACT SW
4 3
21
C274
1u
R244 560
LED1LEDB
21
SW0
SLIDE SW
123
4
5
C2791u10V
LED3LEDB
21
R100
2K
R124100K
LED6LEDB
21RN3
120
1234 5
678
CSSH1
CapSense Shield Electrode
DNI 1
KEY1
TACT SW
4 3
21
C2772.2n
R99
2K
R164 120
L27220 ohm, 0.3A
LED4LEDB
21
LED2LEDB
21
C2781u10V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Overvoltage Protection Threshold Voltage : 5.45V
5V Power from USB Port
DC 5V Power Input
POWER
Ramp Time = 1.2 msec1.2V / 3A
I2C ADDRESS = 1000000
Ramp Time = 1.2 msec1.8V / 1.5A
1.5V / 1.5ARamp Time = 1.2 msec
Delay Enable signal 2.59 msec than AVIN
Delay Enable signal 1.1 msec than AVIN
Power up Sequence:5V -->3.3V--->1.5V--->1.8V--->2.5V--->1.2V--->2.8V
PMONITOR_ALERTPMONITOR_I2C_SDAPMONITOR_I2C_SCL
2P5_POK
1P8_POK
1P2_POK
VCC3P3
VCC3P3
VCC5
VCC5_USB
VCC3P3
VCC5
VCC3P3
VCC1P2_VCC
VCC3P3 VCC1P8
VCC3P3 VCC1P5_DDR3
VCC3P3
VCC3P3
VCC1P2
PMONITOR_I2C_SCL 4PMONITOR_I2C_SDA 4PMONITOR_ALERT 4
1P2_POK 25
1P8_POK 25
2P5_POK 25
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
DECAB
24 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
DECAB
24 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 1.2V, 1.5V, 1.8V, 5V, Power Monitor C
DECAB
24 25Wednesday, March 11, 2015
VCC5
GND1
C53
15n
C51
47u10V
R98
2K
C13
680p
R28
10
J9 DC_5V123
C14
5p
R84 6.8K R27
100K
C44
22u
R37
237K
FID8 FID3FID9
C8522u6.3V
R12330K
C45
47u
R94806
C3
1u
FID6
C78
10u
R856.8K
C39
0.1u
C2022u6.3V
Q3AO3415
C8422u6.3V
R29
158K
R96 0
C79
680p
R240
2K
MTG3GND
C11
5p
FID7
R223
2.2
VCC1P5_DDR3
C12
10u
FID12
VCC1P2_VCC
Q2HE8550G
1
23
R172K
NC(SW):1-2, 12,34-38
NC: 3-4, 22-25
U16
EN6337QI
PVIN_119
PVIN_220
PVIN_321
ENABLE27
AVIN33
SS30
LLM/SYNC26
32AG
ND
PGN
D_1
13
PGN
D_2
14
PGN
D_3
15
PGN
D_4
16
PGN
D_5
17
PGN
D_6
18
VOUT_15
VOUT_26
VOUT_37
VOUT_48
VOUT_59
VOUT_610
VOUT_711
VFB31
RLLM29
POK28
EP39
R75
120
U18
INA230AIRGTR
A02
A11
ALERT3 GND
10SCL5
SDA4
BUS11
13
IN+
12
IN-
Vs9
EP17
FID10
C232 0.1u
D16
PMEG2010AEB
MTG4GND
C54
15p
Q5AO3415
FID11
VCC1P8
U2
EP53F8QI
PVIN13
PVIN14
AVIN110
AVIN24
ENABLE12
AGN
D9
PGN
D2
PGN
D3
VOUT7
VOUT8
POK11
VFB5
C231
0.1u
R144
10
C75
1u
R86
100K
R143
100KDNI
C5
1u
C52
0.1uDNI
R88
200K
R164.7K
D6
LEDB
21
D17
PMEG2010AEB
FID4
C40
47u
R39
237K
PCB1
10-31409160-A0
R72
0.003
U27
EP53F8QI
PVIN13
PVIN14
AVIN110
AVIN24
ENABLE12
AGN
D9
PGN
D2
PGN
D3
VOUT7
VOUT8
POK11
VFB5
MTG1GND
R95100K
D9
BZX84C5V1
3
21
R89 0
R10330K
C2
1u
FID1
R222
2.2
C2122u6.3V
R97
2K
FID5
R87
332K
FID2
R38
118K
L18 30ohm, 3A
MTG2GND
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ramp Time = 1.2msec3.3V / 4A
Ramp Time = 1.18msec2.5V / 1A
Ramp Time = 1.18msec2.8V / 1A
Power up Sequence:5V -->3.3V--->1.5V--->1.8V--->2.5V--->1.2V--->2.8V
2P5_POK
VCC3P3
VCC5
VCC3P3
VCC3P3 VCC2P5
VCC3P3
VCC3P3 VCC2P8
VCC3P3
1P2_POK 24
1P8_POK 24
2P5_POK 24
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 2.5V, 2.8V, 3.3V C
DECAB
25 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 2.5V, 2.8V, 3.3V C
DECAB
25 25Wednesday, March 11, 2015
Title
Size Document Number Rev
Date: Sheet of
Copyright (c) 2014 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.
Power - 2.5V, 2.8V, 3.3V C
DECAB
25 25Wednesday, March 11, 2015
C35
47u
C82
2.2u
R115
649
R172 0
C80
82p
R77
56.2K
C36
47u
C34
0.1u
R78 191K
R125
100K
C56
2.2u
C62
4.7n
R147
4.3K
C91
10u
C57
10u
C37
47u GND2
VCC2P8
C8122u6.3V
U29
EY1501DI-ADJ
VIN_19
VIN_210 VOUT_1
1
VOUT_22
VFB3EN
7
SS6
GN
D5
POK4
EP11
NC8
R76100KDNI
C5922u6.3V
R145
100K
DNI
VCC2P5
C58
82p
R146
931
C47
15n
C48 10p
VCC3P3
U23
EY1501DI-ADJ
VIN_19
VIN_210 VOUT_1
1
VOUT_22
VFB3EN
7
SS6
GN
D5
POK4
EP11
NC8
R104
2.61K
NC(SW):1-2, 12,34-38
NC: 3-4, 22-25
U15
EN6347QI
PVIN_119
PVIN_220
PVIN_321
ENABLE27
AVIN33
SS30
LLM/SYNC26
AGN
D32
PGN
D_1
13
PGN
D_2
14
PGN
D_3
15
PGN
D_4
16
PGN
D_5
17
PGN
D_6
18VOUT_1
5
VOUT_26
VOUT_37
VOUT_48
VOUT_59
VOUT_610
VOUT_711
VFB31
RLLM29
POK28
EP39
C18
4.7n
R254 0