DE0-CV Board SCHEMATIC CONTENT PAGE Cover Cover Page …
17
5 5 4 4 3 3 2 2 1 1 D D C C B B A A 03 ~ 09 Block Diagram FPGA Memory Video User Interface User Interface User Interface 16 Power Power PS2 and Switch and Key LED and 7'Segment VGA FPGA IO, Clock, Configuration and Power Block Diagram SDRAM, SD Card 14 Cover 01 11 10 PAGE 02 SCHEMATIC DE0-CV Board 12~13 CONTENT Cover Page 15 GPIO_0,GPIO_1 - two 2x20 Header Title Size Document Number Rev Date: Sheet of Copyright (c) 2011 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page C DE0-CV Board B 1 17 Wednesday, June 03, 2015 Title Size Document Number Rev Date: Sheet of Copyright (c) 2011 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page C DE0-CV Board B 1 17 Wednesday, June 03, 2015 Title Size Document Number Rev Date: Sheet of Copyright (c) 2011 by Terasic Technologies Inc. Taiwan. No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic. All rights reserved. Cover Page C DE0-CV Board B 1 17 Wednesday, June 03, 2015
Transcript of DE0-CV Board SCHEMATIC CONTENT PAGE Cover Cover Page …
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03 ~ 09Block DiagramFPGAMemoryVideoUser InterfaceUser InterfaceUser Interface
16Power PowerPS2 and Switch and KeyLED and 7'Segment
VGA
FPGA IO, Clock, Configuration and PowerBlock Diagram
SDRAM, SD Card
14
Cover 01
1110
PAGE
02
SCHEMATIC
DE0-CV Board
12~13
CONTENTCover Page
15
GPIO_0,GPIO_1 - two 2x20 Header
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DE0-CV Board
B
1 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DE0-CV Board
B
1 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Cover Page C
DE0-CV Board
B
1 17Wednesday, June 03, 2015
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DE0-CV Board
B
2 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DE0-CV Board
B
2 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Block Diagram C
DE0-CV Board
B
2 17Wednesday, June 03, 2015
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDRAMSwitch
7-Segment
SW9
SW8
SW7
SW5SW4
SW3
SW1SW0 HEX53
HEX52
HEX45
HEX44
HEX43
HEX42
HEX41
HEX40
HEX56
HEX36HEX35
HEX34
HEX32HEX30
HEX23HEX22
HEX21
HEX15
HEX14
HEX13
HEX12
HEX11
HEX10
HEX26
HEX25HEX06
HEX05
HEX04
HEX03
HEX02
HEX01
HEX00
HEX16
DRAM_DQ13DRAM_DQ12
DRAM_DQ11DRAM_DQ9
DRAM_DQ8
DRAM_DQ0
DRAM_DQ1
DRAM_DQ3
DRAM_DQ4DRAM_DQ5
DRAM_DQ6
DRAM_DQ7
DRAM_ADDR3
DRAM_ADDR6
DRAM_ADDR2DRAM_ADDR8
DRAM_DQ10DRAM_DQ14DRAM_DQ15
DRAM_DQ2
SW2
SW6
HEX20
DRAM_DQ[15..0] 10
DRAM_ADDR[12..0] 6,7,10
SW[9..0] 15
HEX0[6..0] 14HEX1[6..0] 14HEX2[6..0] 6,14HEX3[6..0] 6,14HEX4[6..0] 6,14HEX5[6..0] 4,6,14
DRAM_LDQM10DRAM_UDQM 10
DRAM_WE_N 10DRAM_RAS_N 10
DRAM_BA1 10
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 3, BANK 4 C
DE0-CV Board
B
3 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 3, BANK 4 C
DE0-CV Board
B
3 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 3, BANK 4 C
DE0-CV Board
B
3 17Wednesday, June 03, 2015
BANK 3
Bank 3B
5CEBA4F23C7N
U6G
IO_3B/DIFFIO_TX_B9NAB6
IO_3B/DIFFIO_RX_B10N/DQ2BV9
IO_3B/DIFFIO_TX_B9P/DQ2BAB5
IO_3B/DIFFIO_RX_B10P/DQ2BV10
IO_3B/DIFFIO_RX_B11N/DQSN2BP8
IO_3B/DIFFIO_TX_B12N/DQ2BAA7
IO_3B/DIFFIO_RX_B11P/DQS2BN8
IO_3B/DIFFIO_TX_B12PAB7
IO_3B/DIFFIO_TX_B13N/DQ2BAA8
IO_3B/DIFFIO_RX_B14N/DQ2BT9
IO_3B/DIFFIO_TX_B13P/DQ2BAB8
IO_3B/DIFFIO_RX_B14P/DQ2BU10
IO_3B/DIFFIO_TX_B16N/DQ2BAA10 IO_3B/DIFFIO_TX_B16P/DQ2B
AA9
IO_3B/DIFFIO_TX_B17NY10
IO_3B/DIFFIO_RX_B18N/DQ3BT10
IO_3B/DIFFIO_TX_B17P/DQ3BY9
IO_3B/DIFFIO_RX_B18P/DQ3BR9
IO_3B/DIFFIO_RX_B19N/DQSN3BU11
IO_3B/DIFFIO_TX_B20N/DQ3BR12
IO_3B/DIFFIO_RX_B19P/DQS3BU12
IO_3B/DIFFIO_TX_B20PP12
IO_3B/DIFFIO_RX_B22N/DQ3BR10IO_3B/DIFFIO_RX_B22P/DQ3BR11
IO_3B/DIFFIO_TX_B24N/DQ3BY11IO_3B/DIFFIO_TX_B24P/DQ3BAA12
BANK 4
Bank 4A
5CEBA4F23C7N
U6H
IO_4A/RZQ_0/DIFFIO_TX_B25NAB13
IO_4A/DIFFIO_RX_B26N/DQ4BV13
IO_4A/DIFFIO_TX_B25P/DQ4BAB12
IO_4A/DIFFIO_RX_B26P/DQ4BU13
IO_4A/DIFFIO_RX_B27N/DQSN4BT12
IO_4A/DIFFIO_TX_B28N/DQ4BAA14
IO_4A/DIFFIO_RX_B27P/DQS4BT13
IO_4A/DIFFIO_TX_B28PAA13
IO_4A/DIFFIO_TX_B29N/DQ4BAB15
IO_4A/DIFFIO_RX_B30N/DQ4BY14
IO_4A/DIFFIO_TX_B29P/DQ4BAA15
IO_4A/DIFFIO_RX_B30P/DQ4BY15
IO_4A/DIFFIO_TX_B32N/DQ4BAB17 IO_4A/DIFFIO_TX_B32P/DQ4BAB18
IO_4A/DIFFIO_TX_B33NAB20
IO_4A/DIFFIO_RX_B34N/DQ5BY16
IO_4A/DIFFIO_TX_B33P/DQ5BAB21
IO_4A/DIFFIO_RX_B34P/DQ5BY17
IO_4A/DIFFIO_RX_B35N/DQSN5BT14
IO_4A/DIFFIO_TX_B36N/DQ5BAA17
IO_4A/DIFFIO_RX_B35P/DQS5BU15
IO_4A/DIFFIO_TX_B36PAA18
IO_4A/DIFFIO_TX_B37N/DQ5BAA19
IO_4A/DIFFIO_RX_B38N/DQ5BV20
IO_4A/DIFFIO_TX_B37P/DQ5BAA20
IO_4A/DIFFIO_RX_B38P/DQ5BW19
IO_4A/DIFFIO_TX_B40N/DQ5BAB22 IO_4A/DIFFIO_TX_B40P/DQ5BAA22
IO_4A/DIFFIO_TX_B41NY22
IO_4A/DIFFIO_RX_B42N/DQ6BY20
IO_4A/DIFFIO_TX_B41P/DQ6BW22
IO_4A/DIFFIO_RX_B42P/DQ6BY19
IO_4A/DIFFIO_RX_B43N/DQSN6BP14
IO_4A/DIFFIO_TX_B44N/DQ6BY21
IO_4A/DIFFIO_RX_B43P/DQS6BR14
IO_4A/DIFFIO_TX_B44PW21
IO_4A/DIFFIO_TX_B45N/DQ6BU22
IO_4A/DIFFIO_RX_B46N/DQ6BV19
IO_4A/DIFFIO_TX_B45P/DQ6BV21
IO_4A/DIFFIO_RX_B46P/DQ6BV18
IO_4A/DIFFIO_RX_B47NU16
IO_4A/DIFFIO_TX_B48N/DQ6BU21
IO_4A/DIFFIO_RX_B47PU17
IO_4A/DIFFIO_TX_B48P/DQ6BU20
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LED
7-Segment
GPIO 0
LEDR5
LEDR7LEDR6
LEDR2
LEDR1LEDR0
HEX55HEX54
GPIO_024
GPIO_021
GPIO_020GPIO_019
GPIO_014
GPIO_015
GPIO_017
GPIO_028
GPIO_029GPIO_030
GPIO_032
GPIO_023
GPIO_06GPIO_07
GPIO_08GPIO_09
GPIO_010
GPIO_022
LEDR8LEDR9
LEDR4
LEDR3
GPIO_035
GPIO_027
GPIO_025PS2_CLK2 15PS2_CLK 15
PS2_DAT2 15PS2_DAT 15
LEDR[9..0] 14GPIO_0[35..0] 5,6,7,12
HEX5[6..0] 3,6,14
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 2, BANK 5 C
DE0-CV Board
B
4 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 2, BANK 5 C
DE0-CV Board
B
4 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 2, BANK 5 C
DE0-CV Board
B
4 17Wednesday, June 03, 2015
BANK 2
Bank 2A
5CEBA4F23C7N
U6L
IO_2A/DIFFIO_TX_L9NC1
IO_2A/DIFFIO_RX_L10N/DQ1LG1
IO_2A/DIFFIO_TX_L9P/DQ1LC2
IO_2A/DIFFIO_RX_L10P/DQ1LG2
IO_2A/DIFFIO_RX_L11N/DQSN1LE2
IO_2A/DIFFIO_TX_L12N/DQ1LL1
IO_2A/DIFFIO_RX_L11P/DQS1LD3
IO_2A/DIFFIO_TX_L12PL2
IO_2A/DIFFIO_TX_L13N/DQ1LN1
IO_2A/DIFFIO_RX_L14N/DQ1LU1
IO_2A/DIFFIO_TX_L13P/DQ1LN2
IO_2A/DIFFIO_RX_L14P/DQ1LU2
IO_2A/DIFFIO_RX_L15NW2
IO_2A/DIFFIO_TX_L16N/DQ1LAA1
IO_2A/DIFFIO_RX_L15PY3
IO_2A/DIFFIO_TX_L16P/DQ1LAA2
BANK 5
Bank 5BBank 5A
5CEBA4F23C7N
U6I
IO_5A/RZQ_1/DIFFIO_TX_R1P/DQ1RT19
IO_5A/DIFFIO_RX_R4P/DQ1RT15
IO_5A/DIFFIO_RX_R4N/DQ1RR15
IO_5A/DIFFIO_RX_R6P/DQS1RR16
IO_5A/DIFFIO_RX_R6N/DQSN1RR17
IO_5A/DIFFIO_TX_R7P/DQ1RP19
IO_5A/DIFFIO_RX_R8P/DQ1RP16 IO_5A/DIFFIO_TX_R7NP18
IO_5A/DIFFIO_RX_R8N/DQ1RP17
IO_5B/DIFFIO_TX_R10P/DQ2RN20
IO_5B/DIFFIO_TX_R10N/DQ2RN21
IO_5B/DIFFIO_RX_R11P/DQ2RN19
IO_5B/DIFFIO_RX_R11N/DQ2RM18
IO_5B/DIFFIO_RX_R13P/DQS2RK17
IO_5B/DIFFIO_TX_R14PM20
IO_5B/DIFFIO_RX_R13N/DQSN2RL17
IO_5B/DIFFIO_TX_R14N/DQ2RM21
IO_5B/DIFFIO_RX_R15P/DQ2RL19
IO_5B/DIFFIO_TX_R16P/DQ2RK21IO_5B/DIFFIO_RX_R15N/DQ2RL18
IO_5B/DIFFIO_TX_R16NK22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock_outClock_out
GPIO 1
GPIO 0 VGA
GPIO_116GPIO_118
VGA_B3VGA_G2VGA_G3
VGA_G1VGA_G0
GPIO_16GPIO_17
GPIO_18
GPIO_19
GPIO_110
GPIO_111GPIO_112
GPIO_113
GPIO_114GPIO_115
GPIO_117GPIO_120
GPIO_121
GPIO_123
GPIO_124
GPIO_122
GPIO_125
GPIO_126
GPIO_127
GPIO_128
GPIO_129
GPIO_130
GPIO_131
GPIO_135
GPIO_133
GPIO_134
GPIO_11GPIO_13
GPIO_15
GPIO_01GPIO_03GPIO_04
GPIO_026GPIO_05
GPIO_14
GPIO_119
VGA_R3
VGA_R0VGA_R1VGA_R2
VGA_B1VGA_B0
VGA_B2
SD_DATA010SD_DATA110SD_DATA210SD_DATA310
SD_CLK10
GPIO_1[35..0] 6,13
GPIO_0[35..0] 4,6,7,12
VGA_G[3..0] 11
VGA_R[3..0] 11
VGA_B[3..0] 11
SD_CMD10
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 7, BANK 8 C
DE0-CV Board
B
5 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 7, BANK 8 C
DE0-CV Board
B
5 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA BANK 7, BANK 8 C
DE0-CV Board
B
5 17Wednesday, June 03, 2015
BANK 8
Bank 8A
5CEBA4F23C7N
U6K
IO_8A/DIFFIO_TX_T26P/DQ4TL7
IO_8A/DIFFIO_TX_T26N/DQ4TK7
IO_8A/DIFFIO_RX_T27P/DQ4TJ7
IO_8A/DIFFIO_RX_T27N/DQ4TJ8
IO_8A/DIFFIO_RX_T29P/DQS4TJ9
IO_8A/DIFFIO_TX_T30PA10
IO_8A/DIFFIO_RX_T29N/DQSN4TH9
IO_8A/DIFFIO_TX_T30N/DQ4TA9
IO_8A/DIFFIO_RX_T31P/DQ4TB10
IO_8A/DIFFIO_TX_T32P/DQ4TA5 IO_8A/DIFFIO_RX_T31N/DQ4TC9
IO_8A/DIFFIO_TX_T32NB5
IO_8A/DIFFIO_TX_T34P/DQ5TB6
IO_8A/DIFFIO_TX_T34N/DQ5TB7
IO_8A/DIFFIO_RX_T35P/DQ5TA8
IO_8A/DIFFIO_TX_T36P/DQ5TC6IO_8A/DIFFIO_RX_T35N/DQ5TA7
IO_8A/DIFFIO_TX_T36N/DQ5TD6
IO_8A/DIFFIO_RX_T37P/DQS5TE9
IO_8A/DIFFIO_TX_T38PD7
IO_8A/DIFFIO_RX_T37N/DQSN5TD9
IO_8A/DIFFIO_TX_T38N/DQ5TC8
IO_8A/DIFFIO_RX_T39P/DQ5TG6
IO_8A/DIFFIO_TX_T40P/DQ5TF7IO_8A/DIFFIO_RX_T39N/DQ5TH6
IO_8A/DIFFIO_TX_T40NE7
BANK 7
Bank 7A
5CEBA4F23C7N
U6J
IO_7A/DIFFIO_RX_T1PK20
IO_7A/DIFFIO_TX_T2P/DQ1TB16 IO_7A/DIFFIO_RX_T1NK19
IO_7A/DIFFIO_TX_T2N/DQ1TC16
IO_7A/DIFFIO_RX_T3P/DQ1TD17
IO_7A/DIFFIO_TX_T4P/DQ1TG17 IO_7A/DIFFIO_RX_T3N/DQ1TE16
IO_7A/DIFFIO_TX_T4N/DQ1TG16
IO_7A/DIFFIO_RX_T5P/DQS1TG18
IO_7A/DIFFIO_TX_T6PJ19
IO_7A/DIFFIO_RX_T5N/DQSN1TH18
IO_7A/DIFFIO_TX_T6N/DQ1TJ18
IO_7A/DIFFIO_RX_T7P/DQ1TE15
IO_7A/DIFFIO_TX_T8P/DQ1TA15 IO_7A/DIFFIO_RX_T7N/DQ1TF15
IO_7A/DIFFIO_TX_T8NA14
IO_7A/DIFFIO_TX_T10P/DQ2TJ17
IO_7A/DIFFIO_TX_T10N/DQ2TK16
IO_7A/DIFFIO_RX_T11P/DQ2TC15
IO_7A/DIFFIO_TX_T12P/DQ2TG15 IO_7A/DIFFIO_RX_T11N/DQ2TB15
IO_7A/DIFFIO_TX_T12N/DQ2TF14
IO_7A/DIFFIO_RX_T13P/DQS2TH14
IO_7A/DIFFIO_TX_T14PB13
IO_7A/DIFFIO_RX_T13N/DQSN2TJ13
IO_7A/DIFFIO_TX_T14N/DQ2TA13
IO_7A/DIFFIO_RX_T15P/DQ2TE14
IO_7A/DIFFIO_TX_T16P/DQ2TJ11 IO_7A/DIFFIO_RX_T15N/DQ2TF13
IO_7A/DIFFIO_TX_T16NH10
IO_7A/DIFFIO_TX_T18P/DQ3TG11
IO_7A/DIFFIO_TX_T18N/DQ3TF12
IO_7A/DIFFIO_RX_T19P/DQ3TD13
IO_7A/DIFFIO_TX_T20P/DQ3TB12IO_7A/DIFFIO_RX_T19N/DQ3TC13
IO_7A/DIFFIO_TX_T20N/DQ3TA12
IO_7A/DIFFIO_RX_T21P/DQS3TH11
IO_7A/DIFFIO_TX_T22PL8
IO_7A/DIFFIO_RX_T21N/DQSN3TG12
IO_7A/DIFFIO_TX_T22N/DQ3TK9
IO_7A/DIFFIO_RX_T23P/DQ3TD12
IO_7A/DIFFIO_TX_T24P/DQ3TC11IO_7A/DIFFIO_RX_T23N/DQ3TE12
IO_7A/RZQ_2/DIFFIO_TX_T24NB11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock_inClock_in Clock_out
Clock_out
Clock_inClock_in
GPIO 0
GPIO 1
7-Segment
SDRAM
CLOCK_50
CLOCK3_50
GPIO_00GPIO_02
GPIO_016GPIO_018
GPIO_10GPIO_12
CLOCK2_50
CLOCK3_50
CLOCK_50
CLOCK2_50
HEX51HEX50
HEX33HEX31HEX24
GPIO_132
HEX46
DRAM_ADDR5
CLOCK4_50
CLOCK4_50
VCC3P3
VCC3P3
VCC3P3
VCC3P3
DRAM_CLK10
GPIO_0[35..0] 4,5,7,12
GPIO_1[35..0] 5,13
HEX5[6..0] 3,4,14
HEX4[6..0] 3,14
HEX3[6..0] 3,14
HEX2[6..0] 3,14
DRAM_ADDR[12..0] 3,7,10
VGA_HS11VGA_VS11
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Clocks C
DE0-CV Board
B
6 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Clocks C
DE0-CV Board
B
6 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Clocks C
DE0-CV Board
B
6 17Friday, July 03, 2015
R95 0
R92 0R96 0
CDCLVC1104PWR
U3
CLKIN1
1G2
Y03
GN
D4
Y25
VD
D6
Y37
Y18
C16
0.1u
Clocks
Bank 3B
Bank 4A
Bank 5B
Bank 7A
Bank 8A
5CEBA4F23C7N
U6B
IO_3B/CLK0N,FPLL_BL_FBN/DIFFIO_RX_B15NM8 IO_3B/CLK0P,FPLL_BL_FBP/DIFFIO_RX_B15PM9
IO_3B/FPLL_BL_CLKOUT1,FPLL_BL_CLKOUTN/DIFFIO_TX_B21N/DQ3BAB10IO_3B/FPLL_BL_CLKOUT0,FPLL_BL_CLKOUTP,FPLL_BL_FB/DIFFIO_TX_B21P/DQ3BAB11
IO_3B/CLK1N/DIFFIO_RX_B23NP9 IO_3B/CLK1P/DIFFIO_RX_B23PN9
IO_4A/CLK2N/DIFFIO_RX_B31NV14 IO_4A/CLK2P/DIFFIO_RX_B31PV15
IO_4A/CLK3N/DIFFIO_RX_B39NV16 IO_4A/CLK3P/DIFFIO_RX_B39PW16
IO_5B/CLK6P/DIFFIO_RX_R9PN16
IO_5B/CLK6N/DIFFIO_RX_R9NM16 IO_5B/FPLL_BR_CLKOUT0,FPLL_BR_CLKOUTP,FPLL_BR_FB/DIFFIO_TX_R12P/DQ2R
M22
IO_5B/FPLL_BR_CLKOUT1,FPLL_BR_CLKOUTN/DIFFIO_TX_R12N/DQ2RL22
IO_7A/CLK11P/DIFFIO_RX_T9PH16
IO_7A/CLK11N/DIFFIO_RX_T9NH15
IO_7A/CLK10P/DIFFIO_RX_T17PH13
IO_7A/CLK10N/DIFFIO_RX_T17NG13
IO_8A/CLK9P/DIFFIO_RX_T25PG10
IO_8A/CLK9N/DIFFIO_RX_T25NF10
IO_8A/FPLL_TL_CLKOUT0,FPLL_TL_CLKOUTP,FPLL_TL_FB/DIFFIO_TX_T28P/DQ4TH8
IO_8A/FPLL_TL_CLKOUT1,FPLL_TL_CLKOUTN/DIFFIO_TX_T28N/DQ4TG8IO_8A/CLK8P,FPLL_TL_FBP/DIFFIO_RX_T33P
E10
IO_8A/CLK8N,FPLL_TL_FBN/DIFFIO_RX_T33NF9
Y1
50MHZ
VCC4
OUT3
GND2
EN1
R94 0
C59
0.47u
R93 0
C58
0.1u
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MSEL Settings : MSEL[4:0] = 10010 Active serial (AS)(x1 and x4), no compression, no security, fast POR
Design Note:Optional termination resistorfor DCLK
CAD Note:Place near FPGA DCLK pin
USB Blaster
EPCQ Interface
BUTTON
SDRAM
GPIO 0
KEY1
KEY0
KEY2KEY3
FPGA_CONF_DONE
FPGA_NCONFIG
MSEL0
MSEL1
MSEL3
MSEL2
MSEL4
EPCS_DATAEPCS_ASDO
EPCS_DCLKEPCS_NCSO
EPCS_DCLK
EPCS_ASDOEPCS_DATA
RESERVED_EPCQ_DATA2
EPCS_NCSO
FPGA_NSTATUS
FPGA_NCE
BST_TCK
BST_TMSBST_TCK
BST_TDOBST_TDI
GPIO_033
GPIO_034
GPIO_031
GPIO_011
GPIO_012
GPIO_013
DRAM_ADDR0
DRAM_ADDR12
DRAM_ADDR11
DRAM_ADDR7
DRAM_ADDR4
DRAM_ADDR10
DRAM_ADDR1
DRAM_ADDR9
RESERVED_EPCQ_DATA3
RESERVED_EPCQ_DATA2RESERVED_EPCQ_DATA3
VCC3P3_PGMVCC3P3_PGM
VCC3P3
VCC3P3
VCC3P3
VCCIO_PD_3P3
VCCIO_PD_3P3VCCIO_PD_3P3
RESET_N15
GPIO_0[35..0] 4,5,6,12
DRAM_ADDR[12..0] 3,6,10
KEY[3..0] 15
BST_TCK 17
BST_TMS 17
BST_TDO 17
BST_TDI 17
EPCS_DATA 17
EPCS_DCLK 17
EPCS_ASDO 17
EPCS_NCSO 17
FPGA_CONF_DONE 17
FPGA_NCONFIG 17
FPGA_NCE 17 DRAM_CAS_N 10DRAM_CS_N 10
DRAM_BA0 10
DRAM_CKE 10
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Configuration C
DE0-CV Board
B
7 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Configuration C
DE0-CV Board
B
7 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Configuration C
DE0-CV Board
B
7 17Friday, July 03, 2015
R1000
R980DNI
R1060
C1200.1u10V
C2833p
DNI50V
R1030DNI
R41 0DNI
R990DNI
R11610K
R481K
R7210K
C3012p
DNI50V
R970
R1131K
RN30
10K
1 2 3 45678
R51 0DNI
R1010
R1151K
R1040
R5610KDNI
Bank 9A
Bank 3A Bank 5A
Configuration
5CEBA4F23C7N
U6A
TDOM5
NCSO/DATA4R4
TMSP5
AS_DATA3/DATA3T4
TCKV5
AS_DATA2/DATA2AA5
TDIW5
AS_DATA1/DATA1AB3
DCLKV3
AS_DATA0,ASDO/DATA0AB4
IO_3A/DATA6/DIFFIO_RX_B1N/DQ1BR6
IO_3A/DATA5/DIFFIO_TX_B2NU7
IO_3A/DATA8/DIFFIO_RX_B1P/DQ1BR5
IO_3A/DATA7/DIFFIO_TX_B2P/DQ1BU8
IO_3A/DATA10/DIFFIO_RX_B3N/DQSN1BP6
IO_3A/DATA9/DIFFIO_TX_B4N/DQ1BW8
IO_3A/DATA12/DIFFIO_RX_B3P/DQS1BN6
IO_3A/DATA11/DIFFIO_TX_B4PW9
IO_3A/DATA14/DIFFIO_RX_B5N/DQ1BT7
IO_3A/DATA13/DIFFIO_TX_B6N/DQ1BU6
IO_3A/CLKUSR/DIFFIO_RX_B5P/DQ1BT8
IO_5A/INIT_DONE/DIFFIO_RX_R2PT18
IO_5A/CRC_ERROR/DIFFIO_RX_R2NT17
IO_5A/NCEO/DIFFIO_TX_R3P/DQ1RT22
IO_5A/DEV_OE/DIFFIO_TX_R5PR21
IO_5A/DEV_CLRN/DIFFIO_TX_R5N/DQ1RP22
MSEL0L6
CONF_DONEK6
MSEL1J6
NSTATUSH5
NCEG5
MSEL2A2
MSEL3E5
NCONFIGA4
MSEL4F3
IO_3A/DATA15/DIFFIO_TX_B6P/DQ1BV6
IO_3A/PR_DONE/DIFFIO_RX_B7NM6
IO_3A/PR_READY/DIFFIO_TX_B8N/DQ1BR7
IO_3A/PR_ERROR/DIFFIO_RX_B7PM7
IO_3A/DIFFIO_TX_B8P/DQ1BP7
IO_5A/PR_REQUEST/DIFFIO_TX_R1N/DQ1RT20
IO_5A/CVP_CONFDONE/DIFFIO_TX_R3N/DQ1RR22
R1020DNI
U14
EPCS64
VC
C2
NC013
NC024
NC035
NC046
nCS7
DATA18
DCLK16
DATA015
NC0511
NC0612
NC0713
NC0814
GN
D1
0
DATA29
DATA31
R551KDNI
R1050DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCINT_FPGA
VCC2P5 VCCBAT VCCA_FPLLVCC2P5
VCC2P5VCC_AUX
VCC3P3VCC3P3_PGM
VCC3P3 VCCIO_PD_3P3 VCCIO_PD_3P3
VCCIO_PD_3P3
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Power , GND C
DE0-CV Board
B
8 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Power , GND C
DE0-CV Board
B
8 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Power , GND C
DE0-CV Board
B
8 17Friday, July 03, 2015
L8 BEAD
R114 0
Power
5CEBA4F23C7N
U6C
VCCN4
VCCP15
VCCP13
VCCP11
VCCP3
VCCN14
VCCN12
VCCN10
VCCM15
VCCM13
VCCM11
VCCL16
VCCL14
VCCL12
VCCL10
VCCL4
VCCK15
VCCK13
VCCK11
VCCK5
VCCK3
VCCJ16
VCCJ14
VCCJ12
VCCJ10
VCCJ4
VCCPD1A2AE1
VCCPD1A2AR2
VCCPD1A2AJ2
VCCPD3AW6
VCCPD3B4AW17
VCCPD3B4AW14
VCCPD3B4AW12
VCCPD3B4AW11
VCCPD5AP21
VCCPD5BN18
VCCPD5BM17
VCCPD7A8AD16
VCCPD7A8AE11
VCCPD7A8AD14
VCCPD7A8AD8
VCCPD7A8AC10
VCCA_FPLLM3
VCCA_FPLLT3
VCCA_FPLLT5
VCCA_FPLLF4
VCCA_FPLLU18
VCCA_FPLLH19
VCC_AUXE6
VCC_AUXD11
VCC_AUXD18
VCC_AUXW18
VCC_AUXW13
VCC_AUXW7
VCCPGMV8
VCCPGMR19
VCCPGMF8
VCCBATA3
L7 BEAD
Power
Bank IO
5CEBA4F23C7N
U6D
VCCIO2AD4
VCCIO2AY4
VCCIO2AR1
VCCIO2AJ1
VCCIO3AT6
VCCIO3AY8
VCCIO3BT11
VCCIO3BY13
VCCIO3BW10
VCCIO3BR8
VCCIO4AU19
VCCIO4AAA21
VCCIO4AAA16
VCCIO4AW20
VCCIO4AW15
VCCIO4AU14
VCCIO5AP20
VCCIO5AR18
VCCIO5BM19
VCCIO5BK18
VCCIO7AA16
VCCIO7AH17
VCCIO7AG14
VCCIO7AF21
VCCIO7AF11
VCCIO7AE18
VCCIO7AD15
VCCIO7AC22
VCCIO7AC12
VCCIO7AB19
VCCIO8AA6
VCCIO8AG7
VCCIO8AE8
VCCIO8AC7
VREFB2AN0W1
VREFB3AN0Y7
VREFB3BN0Y12
VREFB4AN0AB16
VREFB5AN0R20
VREFB5BN0L20
VREFB7AN0C14
VREFB8AN0B8
R1072K
L9 BEAD
R117 0
R118 0
GND
5CEBA4F23C7N
U6E
GNDF17
GNDC5
GNDP2
GNDAB19
GNDAB14
GNDAB9
GNDAB2
GNDAB1
GNDAA11
GNDAA6
GNDAA4
GNDAA3
GNDY18
GNDY5
GNDY2
GNDY1
GNDW4
GNDW3
GNDV22
GNDV17
GNDV12
GNDV7
GNDV4
GNDV2
GNDV1
GNDU9
GNDU5
GNDU4
GNDU3
GNDT21
GNDT16
GNDT2
GNDT1
GNDR13
GNDR3
GNDP10
GNDP4
GNDP1
GNDN22
GNDN17
GNDN15
GNDN13
GNDN11
GNDN7
GNDN5
GNDN3
GNDM14
GNDM12
GNDM10
GNDM4
GNDM2
GNDM1
GNDL21
GNDL15
GNDL13
GNDL11
GNDL5
GNDL3
GNDK14
GNDK12
GNDK10
GNDK8
GNDK4
GNDK2
GNDK1
GNDJ20
GNDJ15
GNDJ5
GNDJ3
GNDH22
GNDH12
GNDH7
GNDH4
GNDH3
GNDH2
GNDH1
GNDG19
GNDG9
GNDG4
GNDG3
GNDF16
GNDF6
GNDF5
GNDF2
GNDF1
GNDE13
GNDE4
GNDE3
GNDD20
GNDD10
GNDD5
GNDD2
GNDD1
GNDC17
GNDC4
GNDC3
GNDB14
GNDB9
GNDB2
GNDB1 GND
A21 GNDA11
DNU_1B3
DNU_2B4
DNU_3E17
DNU_4L9
NC_1Y6
NC_2V11
NC_3J22
NC_4J21
NC_5H21
NC_6H20
NC_7G22
NC_8G21
NC_9G20
NC_10F22
NC_11F20
NC_12F19
NC_13F18
NC_14E22
NC_15E21
NC_16E20
NC_17E19
NC_18D22
NC_19D21
NC_20D19
NC_21C21
NC_22C20
NC_23C19
NC_24C18
NC_25B22
NC_26B21
NC_27B20
NC_28B18
NC_29B17
NC_30A22
NC_31A20
NC_32A19
NC_33A18
NC_34A17
5CEBA4F23C7N
U6F
RREF_TLA1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA VCCINTFPGA VCCIO & VCCPD
Panasonic6TPE100MPB Panasonic
6TPE100MPB
VCCINT_FPGA
VCCINT_FPGA VCCINT_FPGA
VCCIO_PD_3P3
VCCIO_PD_3P3 VCCIO_PD_3P3
VCCA_FPLL VCC3P3_PGMVCCBAT
VCC_AUX
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Decoupling C
DE0-CV Board
B
9 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Decoupling C
DE0-CV Board
B
9 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
FPGA Decoupling C
DE0-CV Board
B
9 17Friday, July 03, 2015
C104
2.2n
C97
0.1u
C63
2.2uC78
0.1u
C77
0.1u
C115
0.1u
C75
4.7n
C85
0.47u
C83
47n
C106
22n
C71
0.1u
+ C1116.3V
100u
12
C68
2.2n
C91
0.1u
C76
0.1u
C84
4.7n
C81
0.1u
C107
2.2n
+ C746.3V
100u
12
C116
10n
C82
22n
C66
0.1u
+C1196.3V
100u
12
C67
0.1u
C108
10n
C102
0.1u
C80
0.1u
C92
4.7n
C100
10n
C70
0.47u
C105
4.7n
C99
10n
C73
0.22u
C93
4.7n
C109
47n
C95
4.7n
C94
2.2n
C118
22n
C112
4.7n
C90
10n
C69
0.47u
C101
2.2n
C88
0.47u
C117
0.1u
C64
2.2u
C103
2.2n
C72
10n
C86
0.47u
C96
0.1u
C89
10n
C79
4.7n
C114
1u
C87
0.47u
C110
0.22u
C98
0.1u
C113
10n
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SDRAM
Micro SD Card
DRAM_CKE
DRAM_CAS_N
DRAM_RAS_N
DRAM_CS_N
DRAM_WE_N
DRAM_ADDR0
DRAM_ADDR3
DRAM_ADDR1DRAM_ADDR2
DRAM_ADDR10
DRAM_DQ0
DRAM_DQ5
DRAM_DQ3
DRAM_DQ6DRAM_DQ7
DRAM_DQ4
DRAM_DQ2DRAM_DQ1
DRAM_ADDR5
DRAM_ADDR12
DRAM_ADDR8
DRAM_ADDR6DRAM_ADDR7
DRAM_ADDR9
DRAM_ADDR4
DRAM_ADDR11 DRAM_DQ11
DRAM_DQ15
DRAM_DQ8
DRAM_DQ13
DRAM_DQ10DRAM_DQ9
DRAM_DQ12
DRAM_DQ14
SD_CD
SD_DATA0SD_DATA1SD_DATA2SD_DATA3
SD_CMD
SD_DATA1
SD_DATA2SD_DATA3
SD_DATA0
SD_CMD
SD_CLK
SD_CD
DR_VCC3P3DR_VCC3P3
DR_VCC3P3
DR_VCC3P3
VCC3P3
VCC3P3_SDVCC3P3
VCC3P3_SD
VCC3P3_SD
DRAM_ADDR[12..0] 3,6,7
DRAM_DQ[15..0] 3
DRAM_CLK 6DRAM_CKE 7DRAM_LDQM 3DRAM_UDQM 3
DRAM_WE_N 3DRAM_CAS_N 7DRAM_RAS_N 3
DRAM_CS_N 7DRAM_BA0 7DRAM_BA1 3
SD_CLK 5
SD_DATA3 5
SD_DATA2 5SD_DATA1 5SD_DATA0 5
SD_CMD 5
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM , SD CARD C
DE0-CV Board
B
10 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM , SD CARD C
DE0-CV Board
B
10 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
SDRAM , SD CARD C
DE0-CV Board
B
10 17Friday, July 03, 2015
C49
4.7u
R84 10K
C122
0.1u
C128
0.1u
G
S D
Q1PMOS
20V4ADNI
2
1
3
U11
ESD5V3U2UDNI
K1
1
K2
2A
3
C127
0.1u
R123 4.7K
U10
ESD5V3U2UDNI
K1
1
K2
2A
3
C50
0.1u
R121 4.7K
C520.1u10VDNI
U12
ESD5V3U2UDNI
K1
1
K2
2A
3
C125
0.1u
C129
0.1u
Q2MMBT3904DNI
C121
0.1u
R8610KDNI
123
11
45678
109
12
J11
Mic
ro S
D C
ard
Socket
DAT3CMDVCCCLKVSSDAT0DAT1
DAT2
CD
VS
SV
SS
CD2
R119 4.7K
C126
0.1u
R85100KDNI
C124
10u
C51
0.1u
R124 4.7K
R87 1KDNI
C123
10u
U7
SDRAM 32Mx16
A023
A124
A225
A326
A429
A530
A631
A732
A833
A934
nCAS17
nRAS18
LDQM15
nWE16
nCS19
CKE37 CLK38
UDQM39
D02
D14
D25
D37
D48
D510
D611
D713
D842
D944
D1045
D1147
D1248
D1350
D1451
D1553
A1236
BA020
VD
D1
VD
D2
7
VS
S2
8
VS
S4
1
A1022
VD
DQ
3
VD
DQ
9
VD
DQ
43
VD
DQ
49
VS
SQ
6
VS
SQ
12
VS
SQ
46
VS
SQ
52
A1135
BA121
VS
S5
4V
DD
14
R8810KDNI
R120 0
L6 30ohm, 3A
R122 4.7K
RN29
10K
1234 5
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA
VGA_R1
VGA_B
VGA_R2VGA_R3
VGA_G
VGA_R0
VGA_G3
VGA_G1VGA_G2
VGA_G0
VGA_B3
VGA_B1VGA_B2
VGA_B0
VGA_R
VGA_R[3..0] 5VGA_G[3..0] 5VGA_B[3..0] 5
VGA_HS 6VGA_VS 6
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
VGA C
DE0-CV Board
B
11 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
VGA C
DE0-CV Board
B
11 17Wednesday, June 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
VGA C
DE0-CV Board
B
11 17Wednesday, June 03, 2015
RN40 1K1234 5
678
10
11
6
1
5 15
J9 VGA
5
9
4
8
3
7
2
6
1
17
16
101112131415
C135 0.1u
RN42 1K1234 5
678
R130 120
RN41 2K
12345
678
RN38 1K1234 5
678
RN37 2K
12345
678
R129 120
RN39 2K
12345
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Clock_inClock_in
GPIO 0
GPIO 0
Clock_outClock_out
GPIO_0_D30
GPIO_0_D0
GPIO_0_D1
GPIO_0_D2
GPIO_0_D3
GPIO_0_D4
GPIO_0_D5
GPIO_0_D6
GPIO_0_D7
GPIO_0_D8
GPIO_0_D9
GPIO_0_D10
GPIO_0_D11
GPIO_0_D12
GPIO_0_D13
GPIO_0_D14
GPIO_0_D15
GPIO_0_D16
GPIO_0_D17
GPIO_0_D18
GPIO_0_D19
GPIO_0_D20
GPIO_0_D21
GPIO_0_D22
GPIO_0_D23
GPIO_0_D24
GPIO_0_D25
GPIO_0_D26
GPIO_0_D27
GPIO_0_D28
GPIO_0_D29
GPIO_0_D30
GPIO_0_D31
GPIO_0_D32
GPIO_0_D33
GPIO_0_D34
GPIO_0_D35
GPIO_0_D0GPIO_0_D2GPIO_0_D4GPIO_0_D6GPIO_0_D8
GPIO_0_D1GPIO_0_D3GPIO_0_D5GPIO_0_D7GPIO_0_D9
GPIO_0_D14GPIO_0_D12GPIO_0_D10
GPIO_0_D18GPIO_0_D16
GPIO_0_D22GPIO_0_D20
GPIO_0_D24
GPIO_0_D15GPIO_0_D13GPIO_0_D11
GPIO_0_D19GPIO_0_D17
GPIO_0_D23GPIO_0_D21
GPIO_0_D25
GPIO_0_D26GPIO_0_D28
GPIO_0_D32GPIO_0_D34
GPIO_0_D33GPIO_0_D31GPIO_0_D29GPIO_0_D27
GPIO_0_D35
GPIO_014GPIO_015
GPIO_08GPIO_09GPIO_010
GPIO_032GPIO_033GPIO_034GPIO_035
GPIO_017
GPIO_022
GPIO_020
GPIO_023
GPIO_021
GPIO_011
GPIO_012GPIO_013
GPIO_00
GPIO_06
GPIO_04
GPIO_02GPIO_01
GPIO_03
GPIO_018
GPIO_016
GPIO_019
GPIO_07
GPIO_05
GPIO_025
GPIO_030
GPIO_028
GPIO_026
GPIO_024
GPIO_031
GPIO_029
GPIO_027
GPIO_0_D0GPIO_0_D1GPIO_0_D2GPIO_0_D3
GPIO_0_D4GPIO_0_D5GPIO_0_D6GPIO_0_D7
GPIO_0_D8GPIO_0_D9GPIO_0_D10GPIO_0_D11
GPIO_0_D12GPIO_0_D13GPIO_0_D14GPIO_0_D15
GPIO_0_D20GPIO_0_D21
GPIO_0_D16GPIO_0_D17GPIO_0_D18GPIO_0_D19
GPIO_0_D22GPIO_0_D23
GPIO_0_D24GPIO_0_D25GPIO_0_D26GPIO_0_D27
GPIO_0_D28GPIO_0_D29GPIO_0_D30GPIO_0_D31
GPIO_0_D32GPIO_0_D33GPIO_0_D34GPIO_0_D35
VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3
VCC3P3
VCC5
GPIO_0[35..0] 4,5,6,7
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 0 C
DE0-CV Board
B
12 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 0 C
DE0-CV Board
B
12 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 0 C
DE0-CV Board
B
12 17Friday, July 03, 2015
D46
BAT54SDNI
1
23
D43
BAT54SDNI
1
23
D44
BAT54SDNI
1
23
D78
BAT54SDNI
1
23
D19
BAT54SDNI
1
23
D23
BAT54SDNI
1
23
RN1
47
1234 5
678
D75
BAT54SDNI
1
23
D64
BAT54SDNI
1
23
D67
BAT54SDNI
1
23
D51
BAT54SDNI
1
23
D25
BAT54SDNI
1
23
D59
BAT54SDNI
1
23
D48
BAT54SDNI
1
23
D70
BAT54SDNI
1
23
D33
BAT54SDNI
1
23
D27
BAT54SDNI
1
23
RN5
47
1234 5
678
D31
BAT54SDNI
1
23
RN11
47
1234 5
678
D29
BAT54SDNI
1
23
D80
BAT54SDNI
1
23
D72
BAT54SDNI
1
23
D10
BAT54SDNI
1
23
D17
BAT54SDNI
1
23
D6
BAT54SDNI
1
23
D21
BAT54SDNI
1
23
JP1
BOX Header 2X20M
1 23 45 67 89 10
1113
1214161820222426
27
151719212325
28293133353739
303234363840
D13
BAT54SDNI
1
23
D54
BAT54SDNI
1
23
D56
BAT54SDNI
1
23
RN7
47
1234 5
678
D36
BAT54SDNI
1
23
D52
BAT54SDNI
1
23
D62
BAT54SDNI
1
23
D68
BAT54SDNI
1
23
D38
BAT54SDNI
1
23
D76
BAT54SDNI
1
23
RN9
47
1234 5
678
D82
BAT54SDNI
1
23
RN3
47
1234 5
678
RN15
47
1234 5
678
RN13
47
1234 5
678
RN27
47
1234 5
678
D60
BAT54SDNI
1
23
D40
BAT54SDNI
1
23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO 1
GPIO 1
Clock_inClock_in
GPIO_1_D30
GPIO_1_D0
GPIO_1_D1
GPIO_1_D2
GPIO_1_D3
GPIO_1_D4
GPIO_1_D5
GPIO_1_D6
GPIO_1_D7
GPIO_1_D8
GPIO_1_D9
GPIO_1_D10
GPIO_1_D11
GPIO_1_D12
GPIO_1_D13
GPIO_1_D14
GPIO_1_D15
GPIO_1_D16
GPIO_1_D17
GPIO_1_D18
GPIO_1_D19
GPIO_1_D20
GPIO_1_D21
GPIO_1_D22
GPIO_1_D23
GPIO_1_D24
GPIO_1_D25
GPIO_1_D26
GPIO_1_D27
GPIO_1_D28
GPIO_1_D29
GPIO_1_D30
GPIO_1_D31
GPIO_1_D32
GPIO_1_D33
GPIO_1_D34
GPIO_1_D35
GPIO_1_D0GPIO_1_D2GPIO_1_D4GPIO_1_D6GPIO_1_D8
GPIO_1_D1GPIO_1_D3GPIO_1_D5GPIO_1_D7GPIO_1_D9
GPIO_1_D14GPIO_1_D12GPIO_1_D10
GPIO_1_D18GPIO_1_D16
GPIO_1_D22GPIO_1_D20
GPIO_1_D24
GPIO_1_D15GPIO_1_D13GPIO_1_D11
GPIO_1_D19GPIO_1_D17
GPIO_1_D23GPIO_1_D21
GPIO_1_D25
GPIO_1_D26GPIO_1_D28
GPIO_1_D32GPIO_1_D34
GPIO_1_D33GPIO_1_D31GPIO_1_D29GPIO_1_D27
GPIO_1_D35
GPIO_114GPIO_115
GPIO_18GPIO_19GPIO_110
GPIO_132GPIO_133GPIO_134GPIO_135
GPIO_117
GPIO_122
GPIO_120
GPIO_123
GPIO_121
GPIO_111
GPIO_112GPIO_113
GPIO_10
GPIO_16
GPIO_14
GPIO_12GPIO_11
GPIO_13
GPIO_118
GPIO_116
GPIO_119
GPIO_17
GPIO_15
GPIO_125
GPIO_130
GPIO_128
GPIO_126
GPIO_124
GPIO_131
GPIO_129
GPIO_127
GPIO_1_D0GPIO_1_D1GPIO_1_D2GPIO_1_D3
GPIO_1_D4GPIO_1_D5GPIO_1_D6GPIO_1_D7
GPIO_1_D8GPIO_1_D9GPIO_1_D10GPIO_1_D11
GPIO_1_D12GPIO_1_D13GPIO_1_D14GPIO_1_D15
GPIO_1_D20GPIO_1_D21
GPIO_1_D16GPIO_1_D17GPIO_1_D18GPIO_1_D19
GPIO_1_D22GPIO_1_D23
GPIO_1_D24GPIO_1_D25GPIO_1_D26GPIO_1_D27
GPIO_1_D28GPIO_1_D29GPIO_1_D30GPIO_1_D31
GPIO_1_D32GPIO_1_D33GPIO_1_D34GPIO_1_D35
VCC3P3
VCC5
VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3VCC3P3
GPIO_1[35..0] 5,6
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 1 C
DE0-CV Board
B
13 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 1 C
DE0-CV Board
B
13 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
GPIO 1 C
DE0-CV Board
B
13 17Friday, July 03, 2015
D65
BAT54S
1
23
D71
BAT54S
1
23
RN10
47
1234 5
678
D20
BAT54S
1
23
D22
BAT54S
1
23
D30
BAT54S
1
23
D73
BAT54S
1
23
D35
BAT54S
1
23
D53
BAT54S
1
23
D42
BAT54S
1
23
D57
BAT54S
1
23
D32
BAT54S
1
23
D55
BAT54S
1
23
RN2
47
1234 5
678
D34
BAT54S
1
23
D7
BAT54S
1
23
D39
BAT54S
1
23
D58
BAT54S
1
23
JP2
BOX Header 2X20M
1 23 45 67 89 10
1113
1214161820222426
27
151719212325
28293133353739
303234363840
D24
BAT54S
1
23
RN28
47
1234 5
678
D26
BAT54S
1
23
D47
BAT54S
1
23
RN8
47
1234 5
678
D41
BAT54S
1
23
D61
BAT54S
1
23
D66
BAT54S
1
23
RN26
47
1234 5
678
D81
BAT54S
1
23
RN6
47
1234 5
678
RN14
47
1234 5
678
D77
BAT54S
1
23
RN4
47
1234 5
678
D50
BAT54S
1
23
D49
BAT54S
1
23
D45
BAT54S
1
23
D11
BAT54S
1
23
D14
BAT54S
1
23
D37
BAT54S
1
23
D79
BAT54S
1
23
D63
BAT54S
1
23
D69
BAT54S
1
23
D28
BAT54S
1
23
D18
BAT54S
1
23
RN12
47
1234 5
678
D74
BAT54S
1
23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
7-Segment
LED
F4
G5
G4
F0
D2
A2
E5
C2B2
D4
E3
C4
A3
B4
F1E1
C1
A1
D1
B1
D3
E4
C3B3
B5
D5
F2
C5
A5
E2
E0
G0
A0B0C0D0
HEX14HEX13HEX12
HEX00HEX16
HEX15
HEX01
HEX35
HEX30
HEX34
HEX33HEX32HEX31
HEX36
HEX53
HEX55HEX54
HEX52
HEX41HEX40HEX56
HEX06HEX05HEX04HEX03
HEX21HEX22HEX23HEX24
HEX25HEX26
HEX46
HEX43
HEX45HEX44
HEX10
HEX50
G1
G2
F3F5 G3
HEX20HEX42
HEX11
HEX02
HEX51
A4
LEDR4LEDR5
LEDR7LEDR6
LEDR8LEDR9
LEDR3LEDR2LEDR1LEDR0
VCC3P3
VCC3P3
VCC3P3VCC3P3
VCC3P3VCC3P3
HEX0[6..0] 3
HEX1[6..0] 3
HEX2[6..0] 3,6
HEX3[6..0] 3,6
HEX4[6..0] 3,6
HEX5[6..0] 3,4,6
LEDR[9..0] 4
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
7-Segment Display, LED C
DE0-CV Board
B
14 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
7-Segment Display, LED C
DE0-CV Board
B
14 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
7-Segment Display, LED C
DE0-CV Board
B
14 17Friday, July 03, 2015
LEDR1 LEDR2 1
RN19
680
1234 5
678
LEDR9 LEDR2 1
RN17
680
1234 5
678
LEDR5 LEDR2 1
RN23
680
1234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX4
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX1
7Segment Display
1
23
45
6
1098
7
RN16
680
1234 5
678
LEDR0 LEDR2 1
R75 680
e
d
dp
c
g
b
f
a
CA1
CA2
HEX2
7Segment Display
1
23
45
6
1098
7
R76 680
RN34 330
1234 5
678
RN20
680
1234 5
678
LEDR2 LEDR2 1
RN18
680
1234 5
678
LEDR7 LEDR2 1
RN21
680
1234 5
678
LEDR8 LEDR2 1
R126 330
RN25
680
1234 5
678
e
d
dp
c
g
b
f
a
CA1
CA2
HEX5
7Segment Display
1
23
45
6
1098
7
LEDR6 LEDR2 1
R128 330
RN22
680
1234 5
678
RN32 330
1234 5
678
LEDR4 LEDR2 1
e
d
dp
c
g
b
f
a
CA1
CA2
HEX0
7Segment Display
1
23
45
6
1098
7
e
d
dp
c
g
b
f
a
CA1
CA2
HEX3
7Segment Display
1
23
45
6
1098
7
LEDR3 LEDR2 1
RN24
680
1234 5
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RESET_N
PS/2
Switch
BUTTON
KBCLK
KBDAT
MSDAT
MSCLK
SW7SW6SW5SW4
SW3SW2SW1SW0
GNDGND
VCC3P3GND GND
GND
VCC3P3
GND
GND
GNDGNDGND
GNDVCC3P3
GNDGND
GND
GND
VCC3P3
GND
GNDVCC3P3
GND
GND
GND
GNDVCC3P3
GNDGND
VCC3P3
GND
GND
GND
GNDVCC3P3
GNDGND
GND
VCC3P3
SW9SW8
KEY0
KEY2KEY3
KEY1
VCC3P3
FPGA_RESET_NFPGA_RESET_N
VCC5
VCC5 VCC5 VCC5VCC5
VCC3P3 VCC3P3VCC3P3VCC3P3
VCC3P3
VCC3P3
VCC3P3
PS2_DAT 4PS2_CLK 4PS2_DAT2 4PS2_CLK2 4
SW[9..0] 3
KEY[3..0] 7
RESET_N7
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2, SW , KEY C
DE0-CV Board
B
15 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2, SW , KEY C
DE0-CV Board
B
15 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
PS2, SW , KEY C
DE0-CV Board
B
15 17Friday, July 03, 2015
R7 120
KEY4
TACT SW
4 3
21
R125 120
RN36 10K12345
678
C132
1u
SW7
SLIDE SW
123
4
5
C130
0.1u
R11 120
R127 120
SW4
SLIDE SW
123
4
5
D4
BAT54S
1 23
D5
BAT54S
1 23
KEY0
TACT SW
4 3
21
KEY1
TACT SW
4 3
21
U8
SN74AUC17
1A1
2A3
3A5
4A9
5A11
6A13
1Y2
2Y4
3Y6
4Y8
5Y10
6Y12
GND7
VCC14
ETP15
KEY2
TACT SW
4 3
21
SW2
SLIDE SW
123
4
5
D2
BAT54S
1 23
SW8
SLIDE SW
123
4
5
34
TOP
6 5
2 1
J12
PS2
345
7 8 9
21
6
R13 120
SW5
SLIDE SW
123
4
5
C134
1u
SW1
SLIDE SW
123
4
5
KEY3
TACT SW
4 3
21
SW0
SLIDE SW
123
4
5
R9 120
RN33 12012345
678
C131
1u
C10
0.1u
SW3
SLIDE SW
123
4
5
RN35 100K1234 5
678
R78100K
SW9
SLIDE SW
123
4
5
R10
2K
R77 10K
SW6
SLIDE SW
123
4
5
RN31 12012345
678
C9 0.1u
R8
2K
C451u10V
D3
BAT54S1 2
3
C133
1u
R12
2K
R14
2K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Ramp Time = 0.8 msec
1.1V / 3A
Switching Frequency : 2.4MHz
Ramp Time = 0.8 msec3.3V / 3A
Switching Frequency : 2.4MHz
Overvoltage Protection Threshold Voltage : 5.45V
2.5V / 1A
5V Power from USB Port
Place this capacitor close to GPIO 5V power pin
DC 5V Power Input
POWER
Panasonic2R5TPE330MAZB
Panasonic6TPE330MAP
V_CONTROL_3P3VCC1P1_PGOOD
VCC1P1_PGOOD
VCC5 VCCINT_FPGA
VCC5
VCC3P3
VCC5
VCC3P3
VCC2P5
VCC5_USB
VCC5
VCC3P3
VCC3P3
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.1V,2.5V,3.3V,5V C
DE0-CV Board
B
16 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.1V,2.5V,3.3V,5V C
DE0-CV Board
B
16 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
Power - 1.1V,2.5V,3.3V,5V C
DE0-CV Board
B
16 17Friday, July 03, 2015
R53
100K
+C41
6.3V330u
12
R49 75K
+ C34
2.5V330u
12
Q6
HE8550G
C3539p50V
DNI
C4447u6.3V
GND6
R63 0REG3
TPS73701DRBT
IN8
EN5
GN
D4
FB3
OUT1
EP
9
NC12
NC26
NC37
GND4
C29
22u16V
R58562KDNI
PCB
MPB-3236-C0
C431u
C33
47u10V
GND5
R1126.8K
C31 39p50V
DNI
GND2
L5 0.47uH74402500047
R71 0DNI
FID7
VCC1P1
C3747u
6.3V
D8
SM5819A
GND1
D12
BZX84C5V1
3
21
TPS62085RLTR
REG2
EN1
PG2
FB3
GND5
VOS4
SW6
VIN7
FID5
R47200K
R39 6.8K
FID8
R6139.2K
GND3C36
0.1u25V
MH1
D15
LEDB
21
FID6
R45
120
J14 DC_5V123
JP3HEADER 2 DNI1 2
MH2
R37330
C2639p50V
DNI
TPS62085RLTR
REG1
EN1
PG2
FB3
GND5
VOS4
SW6
VIN7
R6239.2K
DNI
MH3
R50 0
MH5
C27
0.1u25V
C40
10u6.3V
R54 0
DNI
R6036.5K
MH4
C421u
DNI
SW11
POWER SW
51
6
24
3
FID2
C38
22u16V
R57
100K
FID4
MH6
Q5AO3415
C321u
DNI
R40
75K
DNI
VCC2P5
JP4HEADER 2 DNI1 2
FID1
D9
SM5819A
Q4AO3415
+C576.3V
100u
12
R44100K
FID3
R67 0
L4 0.47uH74402500047
VCC3P3
R4230K
R68
10K
R4330K
C39 39p50V
DNI
R52 0
JP5HEADER 2 DNI1 2
VCC5
R65 562K
R59178K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPLD ISP
Blaster TO FPGA
The direction of SW10 should be same as DE board
JTAG/AS mode
Close to EPCQ
EPCQ Interface
ULED
Close to FPGA
PROG
RUN
CLK_6MHz
URXF
OSC_24
BST_TMS
UD7UD6UD5
URD
UTXEUWR
UD4
URXF
ISP_TDI
ISP_TMSISP_TDO
UD1
ISP_TCK
SI_WU
UD2UD3
UD5UD6
UD4
UD7
UD0
UD3
EEPDATA
EEPCSEEPCLK
UD1UD0
USB_RESETn
BST_TDIEEPCSEEPCLKEEPDATA
BST_TDO
SI_WU
ISP_TCKISP_TMSISP_TDI
UD2
ISP_TDO
USB_RESETn
CLK_6MHz
OSC_24
USB_DPUSB_DM
TRGOE
FPGA_NCE
TRGNST
TRGDCLK
TRGNCSO
TRGASDO
TRGTDO
TRGTMS
TRGNCE
EPCS_DATA
EPCS_DCLK
EPCS_NCSO
EPCS_ASDO
FPGA_CONF_DONE
FPGA_NCONFIG
FPGA_NCE
ULED
TRGNSTTRGNCSOTRGASDOTRGDCLK
TRGTMS
TRGOE
TRGOEFPGA_NCE
PWRON
PWRON
UWRUTXE
URD
ULED
BST_TCK
TRGTDOTRGNCE
VCC3P3
VCCIO3P3_MAX
VCC5_USB
VCCIO3P3_MAX
VCC5_USBVCC5_USB
VCC5_UBT
VCC5_USB
VCC3P3
VCC3P3
VCCIO3P3_MAX
VCC3P3
VCC5_UBTVCC5
VCC3P3
VCCIO3P3_MAX
VCC5_UBT
VCCINT3P3_MAX
VCC3P3
VCCINT3P3_MAX
VCCIO3P3_MAX
VCCIO3P3_MAX
BST_TCK 7
BST_TMS 7
BST_TDO 7
BST_TDI 7
EPCS_ASDO 7
EPCS_DATA 7
EPCS_DCLK 7
EPCS_NCSO 7
FPGA_CONF_DONE 7
FPGA_NCONFIG 7
FPGA_NCE 7
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster C
DE0-CV Board
B
17 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster C
DE0-CV Board
B
17 17Friday, July 03, 2015
Title
Size Document Number Rev
Date: Sheet o f
Copyright (c) 2011 by Terasic Technologies Inc. Taiwan.
No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.
All rights reserved.
USB Blaster C
DE0-CV Board
B
17 17Friday, July 03, 2015
R25 27
R1 1K
R35 0
R74 1.5K
C230.1u25V
R22 10KDNI
C7 0.1u25V
U13
EPM240T100
IO-B1-02
IO-B1-13
IO-B1-1016
IO-B1-1117
IO-B1-1218
IO-B1-1319
IO-B1-1420
IO-B1-1521
IO-B1-1626
IO-B1-1727
IO-B1-1828
IO-B1-1929
IO-B1-24
IO-B1-2030
IO-B1-2133
IO-B1-2234
IO-B1-2335
IO-B1-2436
IO-B1-2537
IO-B1-2638
IO-B1-2739
IO-B1-2840
IO-B1-2941
IO-B1-35
IO-B1-3042
IO-B1-31/DEV_OE43
IO-B1-32/DEV_CLRN44
IO-B1-3347
IO-B1-3448
IO-B1-3549
IO-B1-3650
IO-B1-3751
IO-B1-46
IO-B1-57
IO-B1-68
IO-B1-7/GCLK012
IO-B1-8/GCLK114
IO-B1-915
IO-B2-01
IO-B2-152
IO-B2-10/GCLK364
IO-B2-1166
IO-B2-1267
IO-B2-1368
IO-B2-1469
IO-B2-1570
IO-B2-1671
IO-B2-1772
IO-B2-1873
IO-B2-1974
IO-B2-253
IO-B2-2075
IO-B2-2176
IO-B2-2277
IO-B2-2378
IO-B2-2481
IO-B2-2582
IO-B2-2683
IO-B2-2784
IO-B2-2885
IO-B2-2986
IO-B2-354
IO-B2-3087
IO-B2-3188
IO-B2-3289
IO-B2-3390
IO-B2-3491
IO-B2-3592
IO-B2-3695
IO-B2-3796
IO-B2-3897
IO-B2-3998
IO-B2-455
IO-B2-4099
IO-B2-41100
IO-B2-556
IO-B2-657
IO-B2-758
IO-B2-861
IO-B2-9/GCLK262
TCK24
TDI23
TDO25
TMS22
VC
CIN
T6
3
VC
CIN
T1
3
VC
CIO
19
VC
CIO
13
1
VC
CIO
14
5
VC
CIO
28
0
VC
CIO
29
4
VC
CIO
25
9
GN
DIN
T6
5G
ND
INT
11
GN
DIO
32
GN
DIO
10
GN
DIO
79
GN
DIO
46
GN
DIO
60
GN
DIO
93
C220.1u25V
R24 27
SW10
SLIDE SW
123
4
5
R38 0
VBUSGND
D-D+
J13USB B-TYPE
4
32
1
5 6
R231K
C190.1u25V
R29 4.7K
C2147p50V
C1310u6.3V
D1
BAT54SDW
1
2
6
34
5
C250.1u25V
R109 0DNI
L2 30ohm, 3A
DNIC150.1u25V
C170.1u25V
C1433n16V
R34 22
R70 10KDNI
C20.1u25V
R111 0DNI
R108 0DNI
X1
24MHz
VCC4
OUT3
GND2
EN1
R3210K
C200.1u25V
R5 10K
R46120
R69 0
R64 24.9
R33 330
U5
FT245BL
LQFP-32
USBDP7
TEST31
AV
CC
30
RXF#12
EEDATA2
VC
C3
D421D322D223D124D025V
CC
26
XTIN27
XTOUT28
GN
D1
7
D718D619D520
RD#16
WR15
TXE#14
VC
CIO
13
AG
ND
29
EECS32 EESK
1
RESET#4
SI/WU11
PWREN#10
RSTOUT#5
3V3OUT6
USBDM8
GN
D9
L3 30ohm, 3A
R28 4.7KDNI
C80.1u25V
R26 1.5K
D16
LEDG
21
R6 1M
R73 0
R66 0
R110 0DNI
J5
Header 2x5DNI
1 23 45 67 89 10
R2710K
C620.1u10V
C180.1u25V
