LM25118

LM25118/LM25118Q Wide Voltage Range Buck-Boost Controller

Literature Number: SNVS726A

LM25118/LM25118Q

November 28, 2011

Wide Voltage Range Buck-Boost ControllerGeneral DescriptionThe LM25118 wide voltage range Buck-Boost switching reg-ulator controller features all of the functions necessary toimplement a high performance, cost efficient Buck-Boost reg-ulator using a minimum of external components. The Buck-Boost topology maintains output voltage regulation when theinput voltage is either less than or greater than the outputvoltage making it especially suitable for automotive applica-tions. The LM25118 operates as a buck regulator while theinput voltage is sufficiently greater than the regulated outputvoltage and gradually transitions to the buck-boost mode asthe input voltage approaches the output. This dual mode ap-proach maintains regulation over a wide range of input volt-ages with optimal conversion efficiency in the buck mode anda glitch-free output during mode transitions. This easy to usecontroller includes drivers for the high side buck MOSFET andthe low side boost MOSFET. The regulator’s control methodis based upon current mode control utilizing an emulated cur-rent ramp. Emulated current mode control reduces noisesensitivity of the pulse-width modulation circuit, allowing reli-able control of the very small duty cycles necessary in highinput voltage applications. Additional protection features in-clude current limit, thermal shutdown and an enable input.The device is available in a power enhanced TSSOP-20package featuring an exposed die attach pad to aid thermaldissipation.

Features LM25118Q1 is an Automotive Grade product that is AEC-

Q100 Grade 1 qualified (-40°C to 125°C operating junctiontemperature)

Input voltage operating range from 3V to 42V

Emulated peak current mode control

Smooth transition between step-down and step- up modes

Switching frequency programmable to 500KHz

Oscillator synchronization capability

Internal high voltage bias regulator

Integrated high and low-side gate drivers

Programmable soft-start time

Ultra low shutdown current

Enable input

Wide bandwidth error amplifier

1.5% feedback reference accuracy

Thermal shutdown

PackageTSSOP-20EP (Exposed pad)

Typical Application Circuit

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© 2011 Texas Instruments Incorporated 301651 www.ti.com

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Connection Diagram

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Top View20-Lead TSSOP with Exposed PadSee NS Package Number MXA20A

Ordering Information

Ordering Number Grade Package TypeNSC Package

DrawingSupplied As

LM25118MH Standard TSSOP-20EP MXA20A Rail of 73 Units

LM25118MHX Standard TSSOP-20EP MXA20A Reel of 2500 Units

LM25118Q1MH Automotive (*) TSSOP-20EP MXA20A Rail of 73 Units

LM25118Q1MHX Automotive (*) TSSOP-20EP MXA20A Reel of 2500 Units

* Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identifiedwith the letter Q. For more information go to http://www.national.com/automotive.

Pin Descriptions

Pin Name Description

1 VIN Input supply voltage.

2 UVLO

If the UVLO pin is below 1.23V, the regulator will be in standby mode (VCC regulator running, switching

regulator disabled). When the UVLO pin exceeds 1.23V, the regulator enters the normal operating mode. An

external voltage divider can be used to set an under-voltage shutdown threshold. A fixed 5 µA current is sourced

out of the UVLO pin. If a current limit condition exists for 256 consecutive switching cycles, an internal switch

pulls the UVLO pin to ground and then releases.

3 RTThe internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The

recommended frequency range is 50 kHz to 500 kHz.

4 ENIf the EN pin is below 0.5V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN

must be raised above 3V for normal operation.

5 RAMPRamp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope

used for emulated current mode control.

6 AGND Analog ground.

7 SS

Soft-Start. An external capacitor and an internal 10 µA current source set the rise time of the error amp

reference. The SS pin is held low when VCC is less than the VCC under-voltage threshold (< 3.7V), when the

UVLO pin is low (< 1.23V), when EN is low (< 0.5V) or when thermal shutdown is active.

8 FB Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.

9 COMPOutput of the internal error amplifier. The loop compensation network should be connected between COMP

and the FB pin.

10 VOUT Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.

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Pin Name Description

11 SYNC Sync input for switching regulator synchronization to an external clock.

12 CS Current sense input. Connect to the diode side of the current sense resistor.

13 CSG Current sense ground input. Connect to the ground side of the current sense resistor.

14 PGND Power Ground.

15 LO Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.

16 VCCOutput of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to

the controller as possible.

17 VCCX

Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9V, the

internal VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not

used, connect to AGND.

18 HB

High side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge

the high side MOSFET gate. This capacitor should be placed as close to the controller as possible and

connected between HB and HS.

19 HOBuck MOSFET gate drive output. Connect to the gate of the high side buck MOSFET through a short, low

inductance path.

20 HSBuck MOSFET source pin. Connect to the source terminal of the high side buck MOSFET and the bootstrap

capacitor.

EP Exposed thermal pad. Solder to the ground plane under the IC to aid in heat dissipation.

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Absolute Maximum Ratings (Note 1)

VIN, EN, VOUT to GND -0.3V to 45V

VCC, LO, VCCX, UVLO to GND (Note 3) -0.3V to 16V

HB to HS -0.3V to 16V

HO to HS -0.3 to HB+0.3V

HS to GND -4V to 45V

CSG, CS to GND -0.3V to +0.3V

RAMP, SS, COMP, FB, SYNC, RT to GND -0.3V to 7V

ESD RatingHBM (Note 2)

2 kV

Storage Temperature Range -55°C to +150°C

Junction Temperature +150°C

Operating Ratings (Note 1)

VIN (Note 4) 3V to 42V

VCC, VCCX 4.75V to 14V

Junction Temperature -40°C to +125°C

Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the

operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design,

or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference

purposes only. Unless otherwise stated the following conditions apply: VIN = 24V, VCCX = 0V, EN = 5V, RT = 29.11 kΩ, No load

on LO and HO.

Symbol Parameter Conditions Min Typ Max Units

VIN SUPPLY

IBIAS VIN Operating Current VCCX = 0V 4.5 5.5 mA

IBIASX VIN Operating Current VCCX = 5V 1 1.85 mA

ISTDBY VIN Shutdown Current EN = 0V 1 10 µA

VCC REGULATOR

VCC(REG) VCC Regulation VCCX = 0V 6.8 7 7.2 V

VCC(REG) VCC Regulation VCCX = 0V, VIN = 6V 5 5.25 5.5 V

VCC Sourcing Current Limit VCC = 0 21 35 mA

VCCX Switch threshold VCCX Rising 3.68 3.85 4.02 V

VCCX Switch hysterisis 0.2 V

VCCX Switch RDS(ON) ICCX = 10 mA 5 12 Ω VCCX Switch Leakage VCCX = 0V 0.5 1 µA

VCCCX Pull-down Resistance VCCX = 3V 70 kΩ VCC Under-Voltage Lockout Voltage VCC Rising 3.52 3.7 3.86 V

VCC Under-Voltage Hysterisis 0.21 V

HB DC Bias current HB-HS = 15V 205 260 µA

VC LDO Mode Turn-off 10 V

EN INPUT

VEN(OFF) EN Input Low Threshold VEN Falling 0.5 V

VEN(ON) EN Input High Threshold VEN Rising 3.00 V

EN Input Bias Current VEN = 3V -1 1 µA

EN Input Bias Current VEN = 0.5V -1 1 µA

EN Input Bias Current VEN = 42V 50 µA

UVLO THRESHOLDS

UVLO UVLO Standby Threshold UVLO Rising 1.191 1.231 1.271 V

ΔUVLO UVLO Threshold Hysteresis 0.105 V

UVLO Pull-up Current Source UVLO = 0V 5 µA

UVLO Pull-down RDS(ON) 100 200 ΩSOFT-START

SS Current Source SS = 0V 7.5 10.5 13.5 µA

SS to FB Offset FB = 1.23V 150 mV

SS Output Low Voltage Sinking 100 µA, UVLO = 0V 7 mV

ERROR AMPLIFIER

VREF FB Reference VoltageMeasured at FB pin,

FB = COMP1.212 1.230 1.248 V

FB Input Bias Current FB = 2V 20 200 nA

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Symbol Parameter Conditions Min Typ Max Units

COMP Sink/Source Current 3 mA

AOL DC Gain 80 dB

fBW Unity Bain Bandwidth 3 MHz

PWM COMPARATORS

tHO(OFF) Forced HO Off-time 305 400 495 ns

TON(MIN) Minimum HO On-time 70 ns

COMP to Comparator Offset 200 mV

OSCILLATOR (RT PIN)

fSW1 Frequency 1 RT = 29.11 kΩ 178 200 224 kHz

fSW2 Frequency 2 RT = 9.525 kΩ 450 515 575 kHz

SYNC

Sync threshold falling 1.3 V

CURRENT LIMIT

VCS(TH)

Cycle-by-cycle Sense Voltage

Threshold (CS-CSG)RAMP = 0 Buck Mode -103 -125 -147 mV

VCS(THX)

Cycle-by-cycle Sense Voltage

Threshold (CS-CSG)RAMP = 0 Buck-Boost Mode -218 -255 -300 mV

CS Bias Current CS = 0V 45 60 µA

CSG Bias Current CSG = 0V 45 60 µA

Current Limit Fault Timer 256 cycles

RAMP GENERATOR

IR2 RAMP Current 2 VIN = 12V, VOUT = 12V 95 115 135 µA

IR3 RAMP Current 3 VIN = 5V, VOUT = 12V 65 80 95 µA

VOUT Bias Current VOUT = 42V 245 µA

LOW SIDE (LO) GATE DRIVER

VOLL LO Low-state Output Voltage ILO = 100 mA 0.095 0.14 0.23 V

VOHL LO High-state Output VoltageILO = -100 mA

VOHL = VCC-VLO

0.25 V

LO Rise Time C-load = 1 nF, VCC = 8V 16 ns

LO Fall Time C-load = 1 nF, VCC = 8V 14 ns

IOHL Peak LO Source Current VLO = 0V, VCC = 8V 2.2 A

IOLL Peak LO Sink Current VLO = VCC = 8V 2.7 A

HIGH SIDE (HO) GATE DRIVER

VOLH HO Low-state Output Voltage IHO = 100 mA 0.1 0.135 0.21 V

VOHH HO High-state Output VoltageIHO = -100 mA,

VOHH = VHB-VOH

0.25 V

HO Rise Time C-load = 1 nF, VCC = 8V 14 ns

HO Fall Time C-load = 1 nF, VCC = 8V 12 ns

IOHH Peak HO Source Current VHO = 0V, VCC = 8V 2.2 A

IOLH Peak HO Sink Current VHO = VCC = 8V 3.5 A

HB-HS Under Voltage Lock-out 3 V

BUCK-BOOST CHARACTERISTICS

Buck-Boost Mode Buck Duty Cycle (Note 5) 69 75 80 %

THERMAL

TSD

Thermal Shutdown Junction

Temperature 165 °C

ΔTSD Thermal Shutdown Hysterisis 25 °C

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Symbol Parameter Conditions Min Typ Max Units

Thermal

Resistance

Junction to Case, θJC (Note 6) 4 °C/W

Junction to Ambient, θJA

(Note 7) 110

°C/W(Note 8) 40

(Note 9) 35

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliabilityand/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated inthe Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device shouldnot be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable standard is JESD-22-A114-C.

Note 3: If VIN ≥ 15.7V, the AbsMax Rating for VCC, LO, VCCX, and UVLO to GND is: -0.3V to 16V. If VIN < 15.7V, the AbsMax Rating for VCC, LO, VCCX,and UVLO to GND is: -0.3V to VIN+0.3V

Note 4: VIN ≥ 5.0V is required to initially start the controller.

Note 5: When the duty cycle exceeds 75%, the LM25118 controller gradually phases into the Buck-Boost mode.

Note 6: θJC refers to center of the Exposed Pad on the bottom of the package as the Case.

Note 7: JEDEC 2-Layer test board (JESD51-3)

Note 8: JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad.

Note 9: JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad.

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Typical Performance Characteristics

Efficiency vs VIN and IOUTVOUT = 12V

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Current Limit Threshold vs VOUT/VINVOUT = 12V

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VCC vs VIN

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VCC vs IVCC

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Error Amplifier Gain/Phase

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LO and HO Peak Gate Current vs Output VoltageVCC = 8V

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Oscillator Frequency vs RT

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Block Diagram and Typical Application Circuit

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Detailed Operating DescriptionThe LM25118 high voltage switching regulator features all ofthe functions necessary to implement an efficient high voltagebuck or buck-boost regulator using a minimum of externalcomponents. The regulator switches smoothly from buck tobuck-boost operation as the input voltage approaches theoutput voltage, allowing operation with the input greater thanor less than the output voltage. This easy to use regulatorintegrates high-side and low-side MOSFET drivers capableof supplying peak currents of 2 Amps. The regulator controlmethod is based on current mode control utilizing an emulat-ed current ramp. Peak current mode control provides inherentline feed-forward, cycle-by-cycle current limiting and ease ofloop compensation. The use of an emulated control ramp re-duces noise sensitivity of the pulse-width modulation circuit,allowing reliable processing of very small duty cycles neces-sary in high input voltage applications. The operating fre-quency is user programmable from 50 kHz to 500 kHz. Anoscillator synchronization pin allows multiple LM25118 regu-lators to self synchronize or be synchronized to an externalclock. Fault protection features include current limiting, ther-mal shutdown and remote shutdown capability. An under-voltage lockout input allows regulator shutdown when theinput voltage is below a user selected threshold, and a low

state at the enable pin will put the regulator into an extremelylow current shutdown state. The device is available in theTSSOP-20EP package featuring an exposed pad to aid inthermal dissipation.

A buck-boost regulator can maintain regulation for input volt-ages either higher or lower than the output voltage. Thechallenge is that buck-boost power converters are not as ef-ficient as buck regulators. The LM25118 has been designedas a dual mode controller whereby the power converter actsas a buck regulator while the input voltage is above the output.As the input voltage approaches the output voltage, a gradualtransition to the buck-boost mode occurs. The dual mode ap-proach maintains regulation over a wide range of input volt-ages, while maintaining the optimal conversion efficiency inthe normal buck mode. The gradual transition betweenmodes eliminates disturbances at the output during transi-tions. Figure 2 shows the basic operation of the LM25118regulator in the buck mode. In buck mode, transistor Q1 isactive and Q2 is disabled. The inductor current ramps in pro-portion to the Vin - Vout voltage difference when Q1 is activeand ramps down through the re-circulating diode D1 when Q1is off. The first order buck mode transfer function is VOUT/VIN = D, where D is the duty cycle of the buck switch, Q1.

30165111

FIGURE 2. Buck Mode Operation

Figure 3 shows the basic operation of buck-boost mode. Inbuck-boost mode both Q1 and Q2 are active for the same timeinterval each cycle. The inductor current ramps up (propor-tional to VIN) when Q1 and Q2 are active and ramps down

through the re-circulating diode during the off time. The firstorder buck-boost transfer function is VOUT/VIN = D/(1-D),where D is the duty cycle of Q1 and Q2.

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FIGURE 3. Buck-Boost Mode Operation

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FIGURE 4. Mode Dependence on Duty Cycle (VOUT =12V)

Operation ModesFigure 4 illustrates how duty cycle affects the operationalmode and is useful for reference in the following discussions.Initially, only the buck switch is active and the buck duty cycleincreases to maintain output regulation as VIN decreases.When VIN is approximately equal to 15.5V, the boost switchbegins to operate with a low duty cycle. If VIN continues tofall, the boost switch duty cycle increases and the buck switchduty cycle decreases until they become equal at VIN = 13.2V.

Buck Mode Operation: VIN > VOUT

The LM25118 buck-boost regulator operates as a conven-tional buck regulator with emulated current mode controlwhile VIN is greater than VOUT and the buck mode duty cycleis less than 75%. In buck mode, the LO gate drive output tothe boost switch remains low.

Buck-Boost Mode Operation: VIN ≊ VOUT

When VIN decreases relative to VOUT, the duty cycle of thebuck switch will increase to maintain regulation. Once the dutycycle reaches 75%, the boost switch starts to operate with avery small duty cycle. As VIN is further decreased, the boostswitch duty cycle increases until it is the same as the buckswitch. As VIN is further decreased below VOUT, the buckand boost switch operate together with the same duty cycleand the regulator is in full buck-boost mode. This feature al-lows the regulator to transition smoothly from buck to buck-boost mode. It should be noted that the regulator can bedesigned to operate with VIN less than 4 volts, but VIN mustbe at least 5 volts during start-up. Figure 5 presents a timingillustration of the gradual transition from buck to buck-boostmode when the input voltage ramps downward over a fewswitching cycles.

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FIGURE 5. Buck (HO) and Boost (LO) Switch Duty Cycle vs. Time,Illustrating Gradual Mode Change with Decreasing Input Voltage

High Voltage Start-Up RegulatorThe LM25118 contains a dual mode, high voltage linear reg-ulator that provides the VCC bias supply for the PWM con-troller and the MOSFET gate driver. The VIN input pin can beconnected directly to input voltages as high as 42V. For inputvoltages below 10V, an internal low dropout switch connectsVCC directly to VIN. In this supply range, VCC is approxi-mately equal to VIN. For VIN voltages greater than 10V, thelow dropout switch is disabled and the VCC regulator is en-abled to maintain VCC at approximately 7V. A wide operatingrange of 4V to 42V (with a startup requirement of at least 5volts) is achieved through the use of this dual mode regulator.

The output of the VCC regulator is current limited to 35 mA,typical. Upon power up, the regulator sources current into thecapacitor connected to the VCC pin. When the voltage at theVCC pin exceeds the VCC under-voltage threshold of 3.7Vand the UVLO input pin voltage is greater than 1.23V, the gatedriver outputs are enabled and a soft-start sequence begins.The gate driver outputs remain enabled until VCC falls below3.5V or the voltage at the UVLO pin falls below 1.13V.

In many applications the regulated output voltage or an aux-iliary supply voltage can be applied to the VCCX pin to reducethe IC power dissipation. For output voltages between 4V and15V, VOUT can be connected directly to VCCX. When thevoltage at the VCCX pin is greater than 3.85V, the internalVCC regulator is disabled and an internal switch connectsVCCX to VCC, reducing the internal power dissipation.

In high voltage applications extra care should be taken to en-sure the VIN pin voltage does not exceed the absolute max-

imum voltage rating of 45V. During line or load transients,voltage ringing on the VIN line that exceeds the absolutemaximum rating can damage the IC. Both careful PC boardlayout and the use of quality bypass capacitors located closeto the VIN and GND pins are essential.

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FIGURE 6. VIN and VCC Sequencing

EnableThe LM25118 contains an enable function which provides avery low input current shutdown mode. If the EN pin is pulledbelow 0.5V, the regulator enters shutdown mode, drawingless than 10 µA from the VIN pin. Raising the EN input above

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3V returns the regulator to normal operation. The EN pin canbe tied directly to the VIN pin if this function is not needed. Itmust not be left floating. A 1 MΩ pull-up resistor to VIN canbe used to interface with an open collector or open drain con-trol signal.

UVLOAn under-voltage lockout pin is provided to disable the regu-lator when the input is below the desired operating range. Ifthe UVLO pin is below 1.13V, the regulator enters a standbymode with the outputs disabled, but with VCC regulator op-erating. If the UVLO input exceeds 1.23V, the regulator willresume normal operation. A voltage divider from the input toground can be used to set a VIN threshold to disable the reg-ulator in brown-out conditions or for low input faults.

If a current limit fault exists for more than 256 clock cycles,the regulator will enter a “hiccup” mode of current limiting andthe UVLO pin will be pulled low by an internal switch. Thisswitch turns off when the UVLO pin approaches ground po-tential allowing the UVLO pin to rise. A capacitor connectedto the UVLO pin will delay the return to a normal operatinglevel and thereby set the off-time of the hiccup mode faultprotection. An internal 5 µA pull-up current pulls the UVLO pinto a high state to ensure normal operation when the VINUVLO function is not required and the pin is left floating.

Oscillator and Sync CapabilityThe LM25118 oscillator frequency is set by a single externalresistor connected between the RT pin and the AGND pin.The RT resistor should be located very close to the device andconnected directly to the pins of the IC. To set a desired os-cillator frequency (f), the necessary value for the RT resistorcan be calculated from the following equation:

The SYNC pin can be used to synchronize the internal oscil-lator to an external clock. The external clock must be of higher

frequency than the free-running frequency set by the RT re-sistor. A clock circuit with an open drain output is the recom-mended interface from the external clock to the SYNC pin.The clock pulse duration should be greater than 15 ns.

30165118

FIGURE 7. Sync from Multiple Devices

Multiple LM25118 devices can be synchronized together sim-ply by connecting the SYNC pins together. In this configura-tion all of the devices will be synchronized to the highestfrequency device. The diagram in Figure 7 illustrates theSYNC input/output features of the LM25118. The internal os-cillator circuit drives the SYNC pin with a strong pull-down/weak pull-up inverter. When the SYNC pin is pulled low, eitherby the internal oscillator or an external clock, the ramp cycleof the oscillator is terminated and forced 400 ns off-time isinitiated before a new oscillator cycle begins. If the SYNC pinsof several LM25118 IC’s are connected together, the IC withthe highest internal clock frequency will pull all the connectedSYNC pins low and terminate the oscillator ramp cycles of theother IC’s. The LM25118 with the highest programmed clockfrequency will serve as the master and control the switchingfrequency of all the devices with lower oscillator frequencies.

30165119

FIGURE 8. Simplified Oscillator and Block Diagram with Sync I/O Circuit

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Error Amplifier and PWM

ComparatorThe internal high gain error amplifier generates an error signalproportional to the difference between the regulated outputvoltage and an internal precision reference (1.23V). The out-put of the error amplifier is connected to the COMP pin. Loopcompensation components, typically a type II network illus-

trated in Figure 1 are connected between the COMP and FBpins. This network creates a low frequency pole, a zero, anda noise reducing high frequency pole. The PWM comparatorcompares the emulated current sense signal from the RAMPgenerator to the error amplifier output voltage at the COMPpin. The same error amplifier is used for operation in buck andbuck-boost mode.

30165125

FIGURE 9. Composition of Emulated Current Signal

Ramp GeneratorThe ramp signal of a pulse-width modulator with current modecontrol is typically derived directly from the buck switch draincurrent. This switch current corresponds to the positive slopeportion of the inductor current signal. Using this signal for thePWM ramp simplifies the control loop transfer function to asingle pole response and provides inherent input voltagefeed-forward compensation. The disadvantage of using thebuck switch current signal for PWM control is the large leadingedge spike due to circuit parasitics. The leading edge spikemust be filtered or blanked to avoid early termination of thePWM pulse. Also, the current measurement may introducesignificant propagation delays. The filtering, blanking timeand propagation delay limit the minimal achievable pulsewidth. In applications where the input voltage may be rela-tively large in comparison to the output voltage, controlling asmall pulse width is necessary for regulation. The LM25118utilizes a unique ramp generator which does not actuallymeasure the buck switch current but instead creates a signalrepresenting or emulating the inductor current. The emulatedramp provides signal to the PWM comparator that is free ofleading edge spikes and measurement or filtering delays. Thecurrent reconstruction is comprised of two elements, a sam-ple-and-hold pedestal level and a ramp capacitor which ischarged by a controlled current source. Refer to Figure 9 fordetails.

The sample-and-hold pedestal level is derived from a mea-surement of the re-circulating current through a current senseresistor in series with the re-circulating diode of the buck reg-ulator stage. A small value current sensing resistor is requiredbetween the re-circulating diode anode and ground. The CS

and CSG pins should be Kelvin connected directly to thesense resistor. The voltage level across the sense resistor issampled and held just prior to the onset of the next conductioninterval of the buck switch. The current sensing and sample-and-hold provide the DC level of the reconstructed currentsignal. The sample and hold of the re-circulating diode currentis valid for both buck and buck-boost modes. The positiveslope inductor current ramp is emulated by an external ca-pacitor connected from the RAMP pin to the AGND and aninternal voltage controlled current source. In buck mode, theramp current source that emulates the inductor current is afunction of the VIN and VOUT voltages per the followingequation:

In buck-boost mode, the ramp current source is a function ofthe input voltage VIN, per the following equation:

Proper selection of the RAMP capacitor (CRAMP) depends up-on the value of the output inductor (L) and the current senseresistor (RS). For proper current emulation, the sample andhold pedestal value and the ramp amplitude must have thesame relative relationship to the actual inductor current. Thatis:

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Where gm is the ramp generator transconductance (5 µA/V)and A is the current sense amplifier gain (10V/V). The rampcapacitor should be located very close to the device and con-nected directly to the RAMP and AGND pins.

The relationship between the average inductor current andthe pedestal value of the sampled inductor current can causeinstability in certain operating conditions. This instability isknown as sub-harmonic oscillation, which occurs when theinductor ripple current does not return to its initial value by thestart of the next switching cycle. Sub-harmonic oscillation isnormally characterized by observing alternating wide and nar-row pulses at the switch node. Adding a fixed slope voltageramp (slope compensation) to the current sense signal pre-vents this oscillation. The 50µA of offset current provided fromthe emulated current source adds enough slope compensa-tion to the ramp signal for output voltages less than or equalto 12V. For higher output voltages, additional slope compen-sation may be required. In such applications, the ramp ca-pacitor can be decreased from the nominal calculated valueto increase the ramp slope compensation.

The pedestal current sample is obtained from the currentsense resistor (Rs) connected to the CS and CSG pins. It issometimes helpful to adjust the internal current sense ampli-fier gain (A) to a lower value in order to obtain the highercurrent limit threshold. Adding a pair of external resistors RGin a series with CS and CSG as shown in Figure 10 reducesthe current sense amplifier gain A according to the followingequation:

Current LimitIn the buck mode the average inductor current is equal to theoutput current (Iout). In buck-boost mode the average induc-tor current is approximately equal to:

Consequently, the inductor current in buck-boost mode ismuch larger especially when VOUT is large relative to VIN.The LM25118 provides a current monitoring scheme to pro-tect the circuit from possible over-current conditions. Whenset correctly, the emulated current sense signal is proportion-al to the buck switch current with a scale factor determined bythe current sense resistor. The emulated ramp signal is ap-plied to the current limit comparator. If the peak of the emu-lated ramp signal exceeds 1.25V when operating in the buckmode, the PWM cycle is immediately terminated (cycle-by-cycle current limiting). In buck-boost mode the current limitthreshold is increased to 2.50V to allow higher peak inductorcurrent. To further protect the external switches during pro-longed overload conditions, an internal counter detects con-secutive cycles of current limiting. If the counter detects 256consecutive current limited PWM cycles, the LM25118 entersa low power dissipation hiccup mode. In the hiccup mode, theoutput drivers are disabled, the UVLO pin is momentarilypulled low, and the soft-start capacitor is discharged. Theregulator is restarted with a normal soft-start sequence oncethe UVLO pin charges back to 1.23V. The hiccup mode off-time can be programmed by an external capacitor connectedfrom UVLO pin to ground. This hiccup cycle will repeat untilthe output overload condition is removed.

In applications with low output inductance and high input volt-age, the switch current may overshoot due to the propagationdelay of the current limit comparator and control circuitry. Ifan overshoot should occur, the sample-and-hold circuit willdetect the excess re-circulating diode current. If the sample-and-hold pedestal level exceeds the internal current limitthreshold, the buck switch will be disabled and will skip PWMcycles until the inductor current has decayed below the cur-rent limit threshold. This approach prevents current runawayconditions due to propagation delays or inductor saturationsince the inductor current is forced to decay before the buckswitch is turned on again.

30165123

FIGURE 10. Current Limit and Ramp Circuit

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Maximum Duty CycleEach conduction cycle of the buck switch is followed by aforced minimum off-time of 400ns to allow sufficient time forthe re-circulating diode current to be sampled. This forced off-time limits the maximum duty cycle of the controller. Theactual maximum duty cycle will vary with the operating fre-quency as follows:

DMAX = 1 - f x 400 x 10-9

where f is the oscillator frequency in Hz

30165126

FIGURE 11. Maximum Duty Cycle vs Frequency

Limiting the maximum duty cycle will limit the maximum boostratio (VOUT/VIN) while operating in buck-boost mode. Forexample, from Figure 11, at an operating frequency of 500kHz, DMAX is 80%. Using the buck-boost transfer function.

With D= 80%, solving for VOUT results in,

VOUT = 4 x VIN

With a minimum input voltage of 5 volts, the maximum pos-sible output voltage is 20 volts at f = 500 kHz. The buck-booststep-up ratio can be increased by reducing the operating fre-quency which increases the maximum duty cycle.

Soft-StartThe soft-start feature allows the regulator to gradually reachthe initial steady state operating point, thus reducing start-upstresses and surges. The internal 10 µA soft-start currentsource gradually charges an external soft-start capacitor con-nected to the SS pin. The SS pin is connected to the positiveinput of the internal error amplifier. The error amplifier controlsthe pulse-width modulator such that the FB pin approximatelyequals the SS pin as the SS capacitor is charged. Once theSS pin voltage exceeds the internal 1.23V reference voltage,the error amp is controlled by the reference instead of the SSpin. The SS pin voltage is clamped by an internal amplifier ata level of 150 mV above the FB pin voltage. This feature pro-vides a soft-start controlled recovery in the event a severeoverload pulls the output voltage (and FB pin) well below nor-mal regulation but doesn’t persist for 256 clock cycles.

Various sequencing and tracking schemes can be imple-mented using external circuits that limit or clamp the voltagelevel of the SS pin. The SS pin acts as a non-inverting inputto the error amplifier anytime SS voltage is less than the 1.23Vreference. In the event a fault is detected (over-temperature,VCC under-voltage, hiccup current limit), the soft-start ca-pacitor will be discharged. When the fault condition is nolonger present, a new soft-start sequence will begin.

HO OutputThe LM25118 contains a high side, high current gate driverand associated high voltage level shift. This gate driver circuitworks in conjunction with an internal diode and an externalbootstrap capacitor. A 0.1 µF ceramic capacitor, connectedwith short traces between the HB pin and HS pin is recom-mended for most circuit configurations. The size of the boot-strap capacitor depends on the gate charge of the externalFET. During the off time of the buck switch, the HS pin voltageis approximately -0.5V and the bootstrap capacitor is chargedfrom VCC through the internal bootstrap diode. When oper-ating with a high PWM duty cycle, the buck switch will beforced off each cycle for 400ns to ensure that the bootstrapcapacitor is recharged.

Thermal ProtectionInternal Thermal Shutdown circuitry is provided to protect theintegrated circuit in the event the maximum junction temper-ature is exceeded. When activated, typically at 165°C, thecontroller is forced into a low power reset state, disabling theoutput driver and the bias regulator. This protection is provid-ed to prevent catastrophic failures from accidental deviceoverheating.

Application InformationThe procedure for calculating the external components is il-lustrated with the following design example. The designationsused in the design example correlate to the final schematicshown in Figure 18. The design specifications are:

• VOUT = 12V

• VIN = 4V to 42V

• F = 300 kHz

• Minimum load current (CCM operation) = 600 mA

• Maximum load current = 3A

R7 = RT

RT sets the oscillator switching frequency. Generally speak-ing, higher operating frequency applications will use smallercomponents, but have higher switching losses. An operatingfrequency of 300 kHz was selected for this example as a rea-sonable compromise for both component size and efficiency.The value of RT can be calculated as follows:

therefore, R7 = 18.3 kΩ

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FIGURE 12. Inductor Current Waveform

INDUCTOR SELECTION

L1

The inductor value is determined based upon the operatingfrequency, load current, ripple current and the input and out-put voltages. Refer to Figure 12 for details.

To keep the circuit in continuous conduction mode (CCM), themaximum ripple current IRIPPLE should be less than twicethe minimum load current. For the specified minimum load of0.6A, the maximum ripple current is 1.2A p-p. Also, the mini-mum value of L must be calculated both for a buck and buck-boost configurations. The final value of inductance willgenerally be a compromise between the two modes. It is de-sirable to have a larger value inductor for buck mode, but thesaturation current rating for the inductor must be large forbuck-boost mode, resulting in a physically large inductor. Ad-ditionally, large value inductors present buck-boost modeloop compensation challenges which will be discussed in er-ror amplifier configuration section. For the design example,the inductor values in both modes are calculated as:

Where:

VOUT is the output voltage

VIN1 is the maximum input voltage

f is the switching frequency

IRIPPLE is the selected inductor peak to peak ripple current(1.2 A selected for this example)

VIN2 is the minimum input voltage

The resulting inductor values are:

L1 = 28 µH, Buck Mode

L1 = 9.8 µH Buck-Boost mode

A 10 µH inductor was selected which is a compromise be-tween these values, while favoring the buck-boost mode. Aswill be illustrated in the compensation section below, the in-ductor value should be as low as possible to move the buck-boost right-half-plane zero to a higher frequency. The ripplecurrent is then rechecked with the selected inductor value us-ing the equations above,

IRIPPLE(BUCK) = 3.36A

IRIPPLE(BUCK-BOOST) = 1.17A

Because the inductor selected is lower than calculated for theBuck mode, the minimum load current for CCM in buck modeis 1.68 A at maximum VIN.

With a 10 µH inductor, the worst case peak inductor currentscan be estimated for each case, assuming a 20% inductorvalue tolerance.

For this example, the two equations yield:

I1(PEAK) = 5.43A

I2(PEAK) = 13.34A

An acceptable current limit setting would be 6.7A for buckmode since the LM25118 automatically doubles the currentlimit threshold in buck-boost mode. The selected inductormust have a saturation current rating at least as high as thebuck-boost mode cycle-by-cycle current limit threshold, in thiscase at least 13.5A. A 10 µH 15 amp inductor was chosen forthis application.

R13 = RSENSE

To select the current sense resistor value, begin by calculat-ing the value of RSENSE for both modes of operation.

R13(BUCK) = 23 mΩFor the buck-boost mode, RSENSE is given by:

R13(BUCK-BOOST) = 18.7 mΩA RSENSE value of no more than 18.7 mΩ must be used toguarantee the required maximum output current in the buck-boost mode. A value of 15 mΩ was selected for componenttolerances and is a standard value.

R13 = 15 mΩ

C15 = CRAMP

With the inductor value selected, the value of C3 necessaryfor the emulation ramp circuit is:

With the inductance value (L1) selected as 10 µH, the calcu-lated value for CRAMP is 333 pF. A standard value of 330 pFwas selected.

C9 - C12 = OUTPUT CAPACITORS

In buck-boost mode, the output capacitors C9 - C12 mustsupply the entire output current during the switch on-time. Forthis reason, the output capacitors are chosen for operation inbuck-boost mode, the demands being much less in buck op-eration. Both bulk capacitance and ESR must be considered

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to guarantee a given output ripple voltage. Buck-boost modecapacitance can be estimated from:

ESR requirements can be estimated from:

For our example, with a ΔVOUT (output ripple) of 50 mV,

CMIN = 141 µF

ESRMAX = 3.8 mΩIf hold-up times are a consideration, the values of input/outputcapacitors must be increased appropriately. Note that it isusually advantageous to use multiple capacitors in parallel toachieve the ESR value required. Also, it is good practice toput a .1 µF - .47 µF ceramic capacitor directly on the outputpins of the supply to reduce high frequency noise. Ceramiccapacitors have good ESR characteristics, and are a goodchoice for input and output capacitors. It should be noted thatthe effective capacitance of ceramic capacitors decreaseswith dc bias. For larger bulk values of capacitance, a low ESRelectrolytic is usually used. However, electrolytic capacitorshave poor tolerance, especially over temperature, and theselected value should be selected larger than the calculatedvalue to allow for temperature variation. Allowing for compo-nent tolerances, the following values of Cout were chosen forthis design example:

Two 180 µF Oscon electrolytic capacitors for bulk capaci-tance

Two 47 µF ceramic capacitors to reduce ESR

Two 0.47 µF ceramic capacitors to reduce spikes at the out-put .

D1

Reverse recovery currents degrade performance and de-crease efficiency. For these reasons, a Schottky diode ofappropriate ratings should be used for D1. The voltage ratingof the boost diode should be equal to VOUT plus some mar-gin. Since D1 only conducts during the buck switch off time ineither mode, the current rating required is:

IDIODE = IOUT x (1-D) Buck Mode

IDIODE = IOUT Buck-Boost Mode

D4

A Schottky type re-circulating diode is required for allLM25118 applications. The near ideal reverse recovery char-acteristics and low forward voltage drop are particularly im-portant diode characteristics for high input voltage and lowoutput voltage applications. The reverse recovery character-istic determines how long the current surge lasts each cyclewhen the buck switch is turned on. The reverse recoverycharacteristics of Schottky diodes minimize the peak instan-taneous power in the buck switch during the turn-on transition.The reverse breakdown rating of the diode should be selectedfor the maximum VIN plus some safety margin.

The forward voltage drop has a significant impact on the con-version efficiency, especially for applications with a low outputvoltage. “Rated” current for diodes vary widely from variousmanufacturers. For the LM25118 this current is user se-lectable through the current sense resistor value. Assuming

a worst case 0.6V drop across the diode, the maximum diodepower dissipation can be high. The diode should have a volt-age rating of VIN and a current rating of IOUT. A conservativedesign would at least double the advertised diode rating sincespecifications between manufacturers vary. For the referencedesign a 100V, 10A Schottky in a D2PAK package was se-lected.

C1 - C5 = INPUT CAPACITORS

A typical regulator supply voltage has a large sourceimpedance at the switching frequency. Good quality input ca-pacitors are necessary to limit the ripple voltage at the VINpin while supplying most of the switch current during the buckswitch on-time. When the buck switch turns on, the currentinto the buck switch steps from zero to the lower peak of theinductor current waveform, then ramps up to the peak value,and then drops to the zero at turn-off. The RMS current ratingof the input capacitors depends on which mode of operationis most critical.

The RMS current demand on the input capacitor(s) is at themaximum value when the duty cycle is at 50%.

Checking both modes of operation we find:

IRMS(BUCK) = 1.5 Amps

IRMS(BUCK-BOOST) = 4.7 Amps

Therefore C1 - C5 should be sized to handle 4.7A of ripplecurrent. Quality ceramic capacitors with a low ESR should beselected. To allow for capacitor tolerances, four 2.2 µF, 100Vceramic capacitors will be used. If step input voltage tran-sients are expected near the maximum rating of the LM25118,a careful evaluation of the ringing and possible spikes at thedevice VIN pin should be completed. An additional dampingnetwork or input voltage clamp may be required in these cas-es.

C20

The capacitor at the VCC pin provides noise filtering and sta-bility for the VCC regulator. The recommended value of C20should be no smaller than 0.1 µF, and should be a good qual-ity, low ESR, ceramic capacitor. A value of 1 µF was selectedfor this design. C20 should be 10 x C8.

If operating without VCCX, then

fOSC x (QCBuck + Boost) + ILOAD(INTERNAL)

must be less than the VCC current limit.

C8

The bootstrap capacitor between the HB and HS pins sup-plies the gate current to charge the buck switch gate at turn-on. The recommended value of C8 is 0.1 µF to 0.47 µF, andshould be a good quality, low ESR, ceramic capacitor. A valueof 0.1 µF was chosen for this design.

C16 = CSS

The capacitor at the SS pin determines the soft-start time, i.e.the time for the reference voltage and the output voltage, toreach the final regulated value. The time is determined from:

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and assumes a current limit>Iload + ICout

For this application, a C16 value of 0.1 µF was chosen whichcorresponds to a soft-start time of about 12 ms.

R8, R9

R8 and R9 set the output voltage level, the ratio of these re-sistors is calculated from:

For a 12V output, the R8/R9 ratio calculates to 9.76. The re-sistors should be chosen from standard value resistors and agood starting point is to select resistors within power ratingsappropriate for the output voltage. Values of 309Ω for R9 and2.67 kΩ for R8 were selected.

R1, R3, C21

A voltage divider can be connected to the UVLO pin to set aminimum operating voltage VIN(UVLO) for the regulator. If thisfeature is required, the easiest approach to select the dividerresistor values is to choose a value for R1 between 10 kΩ and100 kΩ, while observing the minimum value of R1 necessaryto allow the UVLO switch to pull the UVLO pin low. This valueis:

R1 ≥ 1000 x VIN(MAX)

R1 ≥ 75k in our example

R3 is then calculated from

Since VIN(MIN) for our example is 5V, set VIN(UVLO) to 4.0V forsome margin in component tolerances and input ripple.

R1 = 75k is chosen since it is a standard value

R3 = 29.332k is calculated from the equation above. 29.4kwas used since it is a standard value.

Capacitor C21 provides filtering for the divider and the off timeof the “hiccup” duty cycle during current limit. The voltage atthe UVLO pin should never exceed 15V when using an ex-ternal set-point divider. It may be necessary to clamp theUVLO pin at high input voltages.

Knowing the desired off time during “hiccup” current limit, thevalue of C21 is given by:

Notice that tOFF varies with VIN

In this example, C21 was chosen to be 0.1 µF. This will setthe tOFF time to 956 µs with VIN = 12V.

R2

A 1M pull-up resistor connected from the EN pin to the VINpin is sufficient to keep enable in a high state if on-off controlis not used.

SNUBBER

A snubber network across the buck re-circulating diode re-duces ringing and spikes at the switching node. Excessiveringing and spikes can cause erratic operation and increasenoise at the regulator output. In the limit, spikes beyond themaximum voltage rating of the LM25118 or the re-circulatingdiode can damage these devices. Selecting the values for thesnubber is best accomplished through empirical methods.First, make sure the lead lengths for the snubber connectionsare very short. Start with a resistor value between 5 and 20Ohms. Increasing the value of the snubber capacitor resultsin more damping, however the snubber losses increase. Se-lect a minimum value of the capacitor that provides adequateclamping of the diode waveform at maximum load. A snubbermay be required for the boost diode as well. The same em-pirical procedure applies. Snubbers were not necessary inthis example.

Error Amplifier Configuration

R4, C18, C17

These components configure the error amplifier gain charac-teristics to accomplish a stable overall loop gain. One advan-tage of current mode control is the ability to close the loop withonly three feedback components, R4, C18 and C17. Theoverall loop gain is the product of the modulator gain and theerror amplifier gain. The DC modulator gain of the LM25118is as follows:

The dominant, low frequency pole of the modulator is deter-mined by the load resistance (RLOAD) and output capacitance(COUT). The corner frequency of this pole is:

For this example, RLOAD = 4Ω, DMIN = 0.294, and COUT = 454µF, therefore:

fP(MOD) = 149 Hz

DC Gain(MOD) =3.63 = 11.2 dB

Additionally, there is a right-half plane (RHP) zero associatedwith the modulator. The frequency of the RHP zero is:

fRHPzero = 7.8 kHz

The output capacitor ESR produces a zero given by:

ESRZERO = 70 kHz

The RHP zero complicates compensation. The best designapproach is to reduce the loop gain to cross zero at about30% of the calculated RHP zero frequency. The Type ll erroramplifier compensation provided by R4, C18 and C17 placesone pole at the origin for high DC gain. The 2nd pole should

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be located close to the RHP zero. The error amplifier zero(see below) should be placed near the dominate modulatorpole. This is a good starting point for compensation.

Components R4 and C18 configure the error amplifier as aType II configuration which has a DC pole and a zero at

C17 introduces an additional pole used to cancel high fre-quency switching noise. The error amplifier zero cancels themodulator pole leaving a single pose response at thecrossover frequency of the loop gain if the crossover frequen-cy is much lower than the right half plane zero frequency. Asingle pole response at the crossover frequency yields a verystable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossoverfrequency) of 2.0 kHz was selected (about 30% of the right-

half-plane zero frequency). The error amplifier zero (fz)should be selected at a frequency near that of the modulatorpole and much less than the target crossover frequency. Thisconstrains the product of R4 and C18 for a desired compen-sation network zero to be less than 2 kHz. Increasing R4,while proportionally decreasing C18 increases the error ampgain. Conversely, decreasing R4 while proportionally increas-ing C18 decreases the error amp gain. For the design exam-ple C18 was selected for 4.7 nF and R4 was selected to be10 kΩ. These values set the compensation network zero at149 Hz. The overall loop gain can be predicted as the sum (indB) of the modulator gain and the error amp gain.

If a network analyzer is available, the modulator gain can bemeasured and the error amplifier gain can be configured forthe desired loop transfer function. If a network analyzer is notavailable, the error amplifier compensation components canbe designed with the guidelines given. Step load transienttests can be performed to verify acceptable performance. Thestep load goal is minimal overshoot with a damped response.

30165148

FIGURE 13. Modulator Gain and Phase

30165149

FIGURE 14. Error Amplifier Gain and Phase

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FIGURE 15. Overall Loop Gain and Phase

The plots shown in Figures 13, 14 and 15 illustrate the gainand phase diagrams of the design example. The overall band-width is lower in a buck-boost application due the compen-sation challenges associated with the right-half-plane zero.For a pure buck application, the bandwidth could be muchhigher. The LM5116 datasheet is a good reference for com-pensation design of a pure buck mode regulator.

Bias Power Dissipation ReductionBuck or Buck-boost regulators operating with high input volt-age can dissipate an appreciable amount of power whilesupplying the required bias current of the IC. The VCC regu-lator must step-down the input voltage VIN to a nominal VCClevel of 7V. The large voltage drop across the VCC regulator

translates into high power dissipation in the VCC regulator.There are several techniques that can significantly reduce thisbias regulator power dissipation. Figures 16 and 17 depict twomethods to bias the IC, one from the output voltage and onefrom a separate bias supply. In the first case, the internal VCCregulator is used to initially bias the VCC pin. After the outputvoltage is established, the VCC pin bias current is suppliedthrough the VCCX pin, which effectively disables the internalVCC regulator. Any voltage greater than 4.0V can supplyVCC bias through the VCCX pin. However, the voltage ap-plied to the VCCX pin should never exceed 15V. The voltagesupplied through VCCX must be large enough to drive theswitching MOSFETs into full saturation.

30165151

FIGURE 16. VCC Bias from VOUT 4V < VOUT < 15V

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FIGURE 17. VCC Bias with Additional Bias Supply

PCB Layout and Thermal

ConsiderationsIn a buck-boost regulator, there are two loops where currentsare switched very fast. The first loop starts from the input ca-pacitors, and then to the buck switch, the inductor, the boostswitch then back to the input capacitor. The second loop startsfrom the inductor, and then to the output diode, the outputcapacitor, the re-circulating diode, and back to the inductor.Minimizing the PC board area of these two loops reduces thestray inductance and minimizes noise and the possibility oferratic operation. A ground plane in the PC board is recom-mended as a means to connect the input filter capacitors tothe output filter capacitors and the PGND pins of theLM25118. Connect all of the low current ground connections(CSS, RT, CRAMP) directly to the regulator AGND pin. Connectthe AGND and PGND pins together through topside copperarea covering the entire underside of the device. Place sev-eral vias in this underside copper area to the ground plane ofthe input capacitors.

The highest power dissipating components are the two powerMOSFETs, the re-circulating diode, and the output diode. The

easiest way to determine the power dissipated in the MOS-FETs is to measure the total conversion losses (PIN - POUT),then subtract the power losses in the Schottky diodes, outputinductor and any snubber resistors. An approximation for there-circulating Schottky diode loss is:

P = (1-D) x IOUT x VFWD.

The boost diode loss is:

P = IOUT x VFWD.

If a snubber is used, the power loss can be estimated with anoscilloscope by observation of the resistor voltage drop atboth turn-on and turn-off transitions. The LM25118 packagehas an exposed thermal pad to aid power dissipation. Select-ing diodes with exposed pads will aid the power dissipation ofthe diodes as well. When selecting the MOSFETs, pay carefulattention to RDS(ON) at high temperature. Also, selecting MOS-FETs with low gate charge will result in lower switching loss-es.

See Application Notes AN-1520 and AN-2020 for thermalmanagement techniques for use with surface mount compo-nents.

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Notes

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