Data/Frame Memory PE 0 PE 1 PE 2 PE 3 PE N Control Instruction Memory Interconnect The SIMD...
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Transcript of Data/Frame Memory PE 0 PE 1 PE 2 PE 3 PE N Control Instruction Memory Interconnect The SIMD...
Data/Frame Memory
PE 0
PE 1
PE 2
PE 3
PE N
… …ControlInstruction Memory
Interconnect
The SIMD Concept
Embedded Computer Architecture
5KK73 TU/e Henk CorporaalBart Mesman
SIMD: XETAL and IMAP
Xetal-IIPhilips, NXP, TU/e
XETAL-II
SRAM8051
ZigBee
CPLD
Xetal-II
• 600 mW
• 90 nm CMOS
• 53.5 GOPS (arithmetic only) @ 84MHz
Best computationalefficient programmable silicon in 2007
[Kleihorst, et al.2007]
GPO
Out
I2C
GPIProgram
(16k x 56b)Data
(2k x 16b)
Linear Processor Array(320 PEs)
Sequential I/O Memory(2 lines x 320 words)
DIP DOPFrame Memory(2048 lines x 320 words)
IME
M (2
40 k
b)
OM
EM
,LU
T (2
40 k
b)
In
Xetal-II Processor
PE 0 … ...
AGU
Frame Memory(2k entries)
PE 1 PE 319PE 1
Neighborhood Communication Network
All PEs access the same line of the Frame Memory
Xetal-II Memory Access
Integrated Memory Array Processor IMAP (NEC)
IMAP-CEIMAP-CE
IMAP-1
IMAP-VISION
1990 1995 2000 2005 2010
1
0.1
10
100
40MHz, 32PE/Chip
15MHz, 8PE /Chip
Peak Performance(GOPS)
100MHz, 128PE/Chip4-Way VLIW ,50GOPS
0.18um, 2 ~ 4Watt
IMAP-240MHz, 64PE/Chip
IMAPCARIMAPCAR
100MHz, 128PE/Chip4-Way VLIW+MAC, 100GOPS(-40℃ ~ 85 ), 0.13 um, ℃<2Watt
1000
IMAP Series Processors (NEC)
ISSCC’03
ISSCC’95
Year
11.0mm
11.0
mm
PE8 PE8 PE8 PE8 PE8
PE8 PE8 PE8 PE8 PE8
PE8 PE8 PE8
PE8 PE8 PE8
CP
EXTIFDPLL
IMAP-CE(32.7M Tr, 0.18um)
(PE8: eight PEs integration block)
CAMP’97
[Shorin Kyo, et al.2005]
IMAPCAR Block Diagram and Features
Video IN
Video OUTP$,D$,STK RAM
EMEM
Host Processor
Control Processor (CP)
4 Way VLIW PE
4 Way VLIW PE
4 Way VLIW PE
SR0 SR1SR2
IMEM
IMEM
IMEMExte
rnal
Mem
. I/F
12.8 GByte/s0.8 GByte/s
0
1
127
SR3
128
EMEM
EMEM
EMEM
ADD MUL RDU
24 x 8b General Purpose Registers
To/Fr other PEs
To/Fr IMEM
LSU COMM
To/Fr CP
LOG
4) 128 individual RAM blocks
1) 128 4-Way VLIW PEs2) < 2W @ 100MHz3) 130nm CMOS
ALUx1,MULx1,LOGx1,LSUx1
PE 0 … ...AGU
Ring-Connected Shift-Register Network
PE 1AGUPE 127AGU
8bit x 2K 8bit x 2K 8bit x 2K
IMAPCAR Memory Access: local addressing support
Each PE could access different lines of the MemoryRequires separate memory module per PE
IMAPCAR2: XC core
(NEC)
XC Core: SIMD/MIMD
90nm CMOS, 108MHz
[Shorin Kyo, et al.2009]
XC Core: SIMD Mode
XC Core: MIMD Support
4 SIMD PE -> 1 MIMD FPU
Xetal-Pro
TU/e : 2010
PE 0 … ...AGU
Frame Memory(2k entries)
PE 1 PE 319PE 1
Neighborhood Communication Network
Scratchpad Memory (32 entries)
Xetal-Pro Memory Access
All PEs access the same line of the Scratchpad Memory or Frame Memory
Characteristics:
1) 320 single-issue PEs
2) 80GOPS @ 125MHz
3) 65nm CMOS
4) 1pJ/op at sub-
threshold