Dataflow Verilog

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Dataflow Verilog. Motivation. Structural design can be cumbersome Lots of typing 32-bit busses & logic Structural designs are static At least in Verilog (not so for VHDL) Little or no parameterization possible. A Dataflow MUX – Version 1. module mux21(q, sel, a, b); input sel, a, b; - PowerPoint PPT Presentation

Transcript of Dataflow Verilog

A New Kind of AlgebraLots of typing
32-bit busses & logic
Little or no parameterization possible
ECEn 224 Winter 2002
input sel, a, b;
endmodule
ECEn 224 Winter 2002
input sel, a, b;
endmodule
ECEn 224 Winter 2002
%
Similar to C
assign q = ((a<4’b1101) && ((c&4’b0011)!=0)) ? 1’b0:1’b1;
Use &&, ||, ! for 1-bit quantities (results of comparisions)
Use &, |, ~ for bit-by-bit logical operations
Pseudo-code (not real Verilog):
q <= ‘0’;
wire z;
assign z = &x; // Same as z = x[3] & x[2] & x[1] & x[0]
ECEn 224 Winter 2002
wire[31:0] m, n;
assign x = 4’b1100;
assign y = 4’b0101;
assign w = {4’b1101, y}; // w is 8’b11010101
assign t = {2{x}}; // same as {x, x}
assign m = {{4{x}}, {2{q}}};
// m is 32’b11001100110011001100010111000101
ECEn 224 Winter 2002
This a valid 2:1 MUX statement:
But the following is not:
Why?
assign q = (~sel & a) | (sel & b);
wire[3:0] a, b, q;
wire sel;
ECEn 224 Winter 2002
More On Matching Wire Widths
This is an acceptable substitute:
It turns the sel and ~sel values into 4-bit versions for AND-ing and OR-ing
A more elegant version:
wire sel;
wire[3:0] a, b, q;
wire sel;
ECEn 224 Winter 2002
module decode24(q, a);
output[3:0] q;
input[1:0] a;
endmodule
Can you see how to make a 3:8 or 4:16 decoder in the same fashion?
ECEn 224 Winter 2002
input sel;
endmodule
Key Ideas:
The predicate must evaluate to true or false (1 or 0)
The parts getting assigned must be all same widths.
0
1
a
b
s
q
16
16
16
parameter WID = 16;
endmodule
When instantiating, the default value of 16 can be overridden:
mux21n M1(q, sel, a, b); // Instance a 16-bit version
mux21n #(4) M0(q, sel, a, b); // Instance a 4-bit version
Does this work for a 1-bit MUX?
ECEn 224 Winter 2002
© 2003-2008 BYU
Using Parameterization
Careful planning often allows you to write one design which can be reused
Reuse is a common goal in design
Simplifies your work
ECEn 224 Winter 2002
© 2003-2008 BYU
Parameterization Exercise
Design a 4:1 MUX that works with any size operands (arbitrary bit-width)
Either:
Structurally instance 3 of these to make a 4:1 MUX
or
ECEn 224 Winter 2002
parameter WID=16;
input[1:0] sel;
output[WID-1:0] q;
endmodule
If the mux21n cells are parameterizable for bit-width this works…
If not, it doesn’t work…
ECEn 224 Winter 2002
Cascaded ?: operators form an if-then-else structure
Note how sel can be compared to bit patterns (2’b00) or to numbers (1)
module mux41(q, sel, a, b, c, d);
parameter WID=16;
input[1:0] sel;
output[WID-1:0] q;
(sel==1) ? b:
Combinational Circuits
You can use this as a DFF for your design.
Figure out how to parameterize it for arbitrary input/output widths
Remainder of behavioral design not covered in this class…
ECEn 224 Winter 2002
Must structurally instance all storage elements (flip flops)
Behavioral Design
A number of nuances with respect to timing semantics
Not recommended beyond simple FF’s for this class
You will learn full range of behavioral design in later courses
ECEn 224 Winter 2002
&Bitwise AND2As in C
|Bitwise OR2As in C
^Bitwise XOR2As in C
Reduction&Red. AND1Multi-bit input
>>Right shift2Fill with 0's