Data Formats - Keysight · 2005. 5. 3. · Agilent Technologies 2001 Data Formats i Contents Data...

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echnologies 2001 Data Formats

tents Data FormatsData FormatsData FormatsData Formats

1 The Board FileObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

Overview..........................................................................................Modifying or Viewing the Data in the board File .....................

Board File Overview........................................................................Where Does the Board File Come From?..................................Programs that use the board and board.o Files ..........................

BCF Syntax Structure ......................................................................Special Symbols.........................................................................Comments ..................................................................................Numerals ....................................................................................Identifiers (Reference Designators and Node Names) ..............Duplicate Entries........................................................................

Board File Structure.........................................................................Include .......................................................................................Heading ......................................................................................Global Options...........................................................................Device Options ..........................................................................Family Options ..........................................................................Card Options ..............................................................................Fixed Node Options ...................................................................GP Relay Options ......................................................................

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ontents

Library Options..........................................................................Override .....................................................................................Device Definitions .....................................................................FET ............................................................................................Jumper........................................................................................Undefined...................................................................................Nodes .........................................................................................Pin_Map.....................................................................................Unconnected Pin ........................................................................Connections ...............................................................................Dangling Pins.............................................................................Devices.......................................................................................Critical Pins................................................................................Internal Structure .......................................................................Cross Checked Devices .............................................................Cross Checked Nodes ................................................................Disabling Information (Preconditioning)...................................Boundary Scan Chains...............................................................End .............................................................................................

Sample Board File ...........................................................................

2 The board_xy FileObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

Overview..........................................................................................Modifying/ Viewing the Data in the board_xy File...................

What is a board_xy File? .................................................................Programs that Use the board_xy File...............................................

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ontents

board_xy File Syntax .......................................................................Scale...........................................................................................Units...........................................................................................Include .......................................................................................Placement...................................................................................Outline .......................................................................................Tooling.......................................................................................Keepout ......................................................................................Node...........................................................................................Other ..........................................................................................Group .........................................................................................Devices.......................................................................................End .............................................................................................

Sample board_xy File ......................................................................

3 The Testorder FileObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

Introduction......................................................................................Modifying/Viewing the Data in the testorder File.....................

Testorder Syntax ............................................................................. Statement List ...........................................................................Testplan Generation On/Off ......................................................

Sample Testorder File ......................................................................

4 The Wirelist FileObjectives ..................................................................................

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ontents

Prerequisites...............................................................................Required Tools and Materials....................................................

Overview..........................................................................................Viewing the Data in the wirelist File .........................................

The Wirelist Syntax .........................................................................global .........................................................................................end global...................................................................................ground ........................................................................................end ground .................................................................................relay ...........................................................................................end relay.....................................................................................strapping.....................................................................................tie ...............................................................................................end strapping..............................................................................unused ........................................................................................end unused .................................................................................test ..............................................................................................device .........................................................................................end device ..................................................................................clock...........................................................................................asru module................................................................................timing module ............................................................................stimulus module .........................................................................functional ...................................................................................include........................................................................................subtest ........................................................................................end subtest..................................................................................wire ............................................................................................group ..........................................................................................end group ...................................................................................

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ontents

serial...........................................................................................interface .....................................................................................end interface...............................................................................

Sample Wirelist File ........................................................................

5 The Fixture FilesObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

Overview..........................................................................................Modify the Fixture File from Agilent Fixture Consultant .........Modify the Fixture File from Agilent IPG Test Consultant ......Modify the Fixture File Manually .............................................

What is a Fixture File?.....................................................................Fixture Description Block..........................................................Board Description Block ...........................................................Protected Unit Description Block ..............................................

Programs that Use the Fixture File ..................................................Fixture File Syntax...........................................................................

The Fixture Description Block ..................................................The Board Description Block ....................................................Protected Unit Description Block ..............................................End .............................................................................................

Sample Fixture File..........................................................................Fixture Defaults File ........................................................................Sample Fixture Defaults File ...........................................................

The Options Sections .................................................................

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ontents

Keepout ......................................................................................Default Placement......................................................................Dividing Lines ...........................................................................Comments ..................................................................................

User-Modifiable Fixture Components .............................................Fixture Components Files Syntax....................................................

Fixture Kit Component File Syntax...........................................Comments ..................................................................................

Sample Fixture Components Files ...................................................Standard and Advanced probe Spacing ...........................................

6 Log Record FormatObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

What are Log Records?....................................................................About Log Record Prefixes .............................................................Hierarchy of Log Records................................................................Interpreting the Log Records ...........................................................

A Note About Truncated Records .............................................A Note About Process Steps ......................................................A Note About User-Defined Log Records ................................

How Log Records are Formatted.....................................................Special Characters......................................................................Rules of Formatting ...................................................................

Descriptions of the Log Records .....................................................Record @A-CAP: capacitor ......................................................

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ontents

Record @A-DIO: diode.............................................................Record @A-FUS: fuse...............................................................Record @A-IND: inductor ........................................................Record @A-JUM: jumper..........................................................Record @A-MEA: measure.......................................................Record @A-NFE: nfetr..............................................................Record @A-NPN: npn...............................................................Record @A-PFE: pfetr ..............................................................Record @A-PNP: pnp................................................................Record @A-POT: potentiometer ...............................................Record @A-RES: resistor..........................................................Record @A-SWI: switch ...........................................................Record @A-ZEN: zener ............................................................Record @AID: identify board causing real-time alarm.............Record @ALM: identify real-time alarm ..................................Record @ARRAY: digitizer results analysis ............................Record @BATCH: identify a batch of boards...........................Record @BLOCK: identify a test block....................................Record @BS-O: list of open pins ..............................................Record @BS-S: list of shorted pins ...........................................Record @BTEST: describe a board test ....................................Record @BT-DIAG: results of a backtrace test ........................Record @BT-FAULT: list of predicted faults...........................Record @BT-FD: identify failing test & describe fault data.....Record @BT-NOD: list of nodes and their test types ...............Record @CCHK: Connect Check Test......................................Record @DPIN: list of device pins for a single device .............Record @D-PLD: results of PLD programming -- success or fRecord @D-T: test digital..........................................................Record @GRP: group record.....................................................Record @INDICT: indict record ...............................................

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Record @LIM2: high & low limits of analog test .....................Record @LIM3: nominal high/low ...........................................Record @M-CL: MAGICCLUSTER record.............................Record @NETV: network verification record...........................Record @NODE: list of nodes ..................................................Record @PCHK: Polarity Check Test.......................................Record @PF: pinsfailed.............................................................Record @PIN: list of pins..........................................................Record @PRB: (partial) results of probing (failures)................Record @RACT: describe a repair action .................................Record @REP: describe a repair event......................................Record @RETEST: indicate a log clear for retest.....................Record @RPT: messages logged by report ...............................Record @S-PROC: describe process in serial test ....................Record @TJET: TestJet Test .....................................................Record @TS: test shorts ............................................................Record @TS-D: destination nodes shorted to source node .......Record @TS-O: opens found while shorts testing ....................Record @TS-P: phantoms found while shorts testing...............Record @TS-S: results of shorts testing from a source node ....

7 The Board Defaults FilesObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

Overview..........................................................................................The board_defaults File ...................................................................The edge_

board_defaults File .......................................................................

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ontents

8 Part Description LanguageObjectives ..................................................................................Prerequisites...............................................................................Required Tools and Materials....................................................

About Part Description Language....................................................Overview....................................................................................Structure of Part Description Language.....................................Examples of Part Description Libraries.....................................How Child Devices Inherit Traits From Parent Devices ...........A Shortcut for Denoting Non-Testable Devices........................Restrictions on Nested Entries ...................................................

Reference Description of PDL.........................................................Additional Features for Manually Created PDL Files ...............capacitor.....................................................................................connector....................................................................................diode...........................................................................................external pins ...............................................................................fet ...............................................................................................fuse.............................................................................................inductor ......................................................................................Internal node ..............................................................................jumper ........................................................................................pin library...................................................................................potentiometer .............................................................................resistor........................................................................................switch .........................................................................................transistor.....................................................................................zener...........................................................................................

© Agilent T 1-1

In this


1111 The Board File

chapter... � Overview, 1-2

� Board File Overview, 1-4

� BCF Syntax Structure, 1-6

� Board File Structure, 1-12

� Sample Board File, 1-78

ObjectivesWhen you finish reading this chapter, you should be able to:

� Understand the Board Files syntax structure and the file structure, including the syntax of the keywords

PrerequisitesThere are no prerequisites associated with using this chapter.

Required Tools and MaterialsThere are no required tools or materials associated with using this chapter.

© Agilent T 1-2

Chapter 1

Overv the board file from Agilent Board ant.

fy entry forms.

ile board file by clicking the left mouse on Final Compile/Verify.

hapter 2, Agilent Board Consultant in Test opment Tools for more information on ying entry forms.

the board file from Agilent IPG Test ant.

the left mouse button on Edit.

the mouse pointer to select View/Edit board

est Consultant opens a BT-BASIC window ads the board file into the BT-BASIC pace for you to edit.

the board file manually.

a BT-BASIC window.

the board test directory.


: The Board File

iew This chapter describes the structure of the Board Configuration Format (BCF) syntax of the board file. The board file contains a description of the devices on the board to be tested, their interconnections, and the test and fixture options.

NOTEThere are optional board file statements that are not described in this chapter. These statements are available with optional software packages such as the Agilent PanelTest option. For information about such statements, refer to the documentation in the optional package.

Modifying or Viewing the Data in the board File

NOTEYou should not edit board test files with shell editors such as vi. These editors do not update the file's header information, such as the time-stamp, that Agilent 3070 programs use. Instead, use the BT-BASIC editor to edit board test files.

1 Modify Consult

a Modi

b Compbutton

NOTESee CDevelmodif

2 Modify Consult

a Click

b Drag File.

IPG Tand loworks

3 Modify

a Open

b msi to

© Agilent T 1-3

Chapter 1


: The Board File

c Generate a board source file from the board.o object file if the board source file doesn�t exist. Type:list object "board.o" to board

d Load the board file. Type:load “board”

e Edit the board file.

f Save the board file. Type:re-store "board"

This chapter gives you an overview of the board file, an explanation of the syntax structure, a description of the file structure including the syntax of the keywords, and ends with a sample board file.

The information in the board file is created from the entry forms of Board Consultant.

NOTEBoard Consultant is described in Chapter 3, Creating Board Information in Test and Fixture Development.

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Chapter 1

Board ation not translated into the board file must nually entered using Board Consultant.

oard Consultant to create and edit the entire file. (Board Consultant is explained in

er 3, Creating Board Information in Test xture Development.)

late a 3065 BCF file with the translate statement.

ally create the file using the structure and x described in this chapter. If you manually your board file, we recommend that you e check board statement to check the x before you compile the file.


: The Board File

File Overview The board file contains the electrical description of a circuit board. This includes the information in Table 1-1.

Where Does the Board File Come From?There are four methods to produce the board file.

� If you used the CAD Format Translator (CFT) to translate an X-Y data file, CFT outputs data into the board file for you. CFT can translate device and connectivity information and material list information. If material list information is not translated by CFT, default values from the board_defaults file will be used instead. Any

informbe ma

� Use Bboard

Chaptand Fi

� Transboard

� Manusyntacreateuse thsynta

Table 1-1 Information in board file

Information Description

fixture options fixture parameters for the Fixture Generation Software

device options test parameters for Agilent IPG

component values and tolerances

device specifications for IPG

connectivity information

topology information for IPG

© Agilent T 1-5

Chapter 1

tains any topology information, CFT will output Use Board Consultant to read the board file the board file, then you can use Board rd_xy files. Completing the board and n Chapter 3, Creating Board Information

ard.o file to generate device tests.

re Generation Software read the board.o file entered in the Critical Pins Form of Board oard Consultant. This information is passed on .o file for any general purpose relay

xy.o file.


: The Board File

Programs that use the board and board.o Files

Table 1-2 Programs that use the board and board.o files

Name Description

Board Consultant

Used to edit the board file. If you use an _xy data file that conthe topology information into the board and board_xy files. and edit and complete the file. If you do not use CFT to createConsultant to create and complete the entire board and boaboard_xy files is part of the data capture process described iin Test and Fixture Development.

Check Board

Reads and verifies the syntax of the board file.

IPG Uses device, topology, and test option information from the bo

Fixture Generation Software

The Board Placement and Probe Select programs of the Fixtuto find the fixture options and any critical pins. Critical pins areConsultant; Fixture Options are part of the Global Options of Bto fixture.o. Module Pin Assignment also reads the boardassignments.

Board_xy Compiler

Uses the topology and fixture options to generate the board_

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Chapter 1

BCF SStruct

hapter 3, Creating Board Information in nd Fixture Development for recommended naming and pin numbering conventions.

mbolso sets of special characters that you cannot umbers and device names in the board file:

cters that have special meaning in BCF.

cters that have special meaning in the shell.

t of special characters, BCF special and their meanings are described in Table

BCF special characters

Description

Separates the identifier for a device and pin.

Used as a delimiter, same as a space.

Used to terminate a statement.

Used to separate a parent device from a child device and panelized test.

Used to separate a parent device from a child device and panelized test.


: The Board File

yntax ure

This section is provided to help you understand the Board Configuration Format (BCF) syntax of the board file. Each keyword of the syntax is described in the next section.

The BCF syntax is divided into these categories:

� Special Symbols

� Comments

� Identifiers

� Numerals

� Keywords

A BCF file is an ASCII file that is compiled by a 3070 Family system and contains a description of the topology of the board to be tested.

You can use upper or lower case characters in the BCF syntax. The case that you use is preserved in the board file; however, the device names in the board.o and board.l files will be lower case. Any device names retrieved from board.o, such as in the test statement in the testplan, will be lower case. Note that quotes on reference designators are optional.

NOTESee CTest anode

Special SyThere are twuse in part n

� Chara

� Chara

The first secharacters, 1-3.

Table 1-3

Character

.

,

;

%

:

© Agilent T 1-7

Chapter 1

! comment

re legal BT-BASIC constants with a f 20 characters. The suffixes in Table 1-4 with numerals and must follow the numeral ce.

to Chapter 2, Syntax Conventions and itions in Board Test Fundamentals for more ation on numeric constants.

Suffixes allowed with numerals

Description Exponent

Mega 106

kilo 103

milli 10-3

micro 10-6

nano 10-9

pico 10-12


: The Board File

The second set of special characters, shell characters, are:

* . " ' ` [ ] < > | & $ \

/ blank ; ? ^ ( ) :

# - (in first character position)

Do not use these characters in part numbers and device names. The underscore (_) works well in place of the period (.).

Do not use the tilde (~) in device names, node names, or failure messages.

CommentsA comment begins with an exclamation mark (!) and continues to the end of a physical line. For example:resistor

R1 10 10 10 f; ! commentR2 10 10 10 f message; ! comment

NumeralsNumerals amaximum oare allowedwith no spa

NOTEReferDefininform

" Used to delineate a string.

! Indicates a comment; terminates at the end of the line.

** Used as a default value placeholder.

Table 1-3 BCF special characters (continued)

Character Description

Table 1-4

Suffix

M

k

m

u

n

p

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Chapter 1

70_ROOT/standard. The Pin_Map can also e board file. The pin name mapping table is ore thoroughly under Pin_Map in the next mapping takes place only once for both the oard_xy files.

re not case-sensitive. BCF syntax keywords

ingse, global, test, GP relay, and fixture optionsnd of the device options messages_Map tablend of a Pin_Maponent descriptions

name for unconnected pins connectionse connectionsal pins checkingling informationnd of a BCF file

nt description keyword marks the beginning omponent descriptions. The description can veral elements (component name, value,

etc.) which must be separated by at least one pins of a component are defined by the


: The Board File

Identifiers (Reference Designators and Node Names)An identifier is the name of a device, pin, or node that you are entering into Agilent Board Consultant. Identifiers of devices and pins are called reference designators. Identifiers for nodes are called node names. Board Consultant accepts:

� Node names up to 40 characters long

� Device designators up to 48 characters long

� Pin names up to 8 characters long

� Path names up to 1024 characters long

Identifiers are not case-sensitive; the upper and lowercase of a letter is considered the same letter. Reference designators and node names can be optionally listed with quotes (e.g. �U101�). Note that you must use quotes if the identifier contains any special characters (e.g. "U 101"). We recommend not using special characters in identifier names.

You can use a Pin_Map to translate device pin names. This is useful when your CAD data file uses pin names other than what Board Consultant accepts. For example, your CAD data file may have specified transistor pins as 1, 2, and 3, instead of E, B, and C as required by Board Consultant. In this case, you can use a Pin_Map to translate the 1, 2, and 3 to E, B, and C. The Pin_Map can be placed in the board_defaults file and can reside in the local board directory, or under

$AGILENT30

be part of thdescribed msection. Pinboard and b

KeywordsKeywords aindicate:

� Head� Devic� The e� Node� A Pin� The e� Comp� Node� Node� Devic� Critic� Cross� Disab� The e

A componeof a list of cconsist of setolerances, space. The

© Agilent T 1-9

Chapter 1

in the board file which is missing. The ults file can be located under the local

tory or under the 70_ROOT/standard directory. CFT looks

he local board directory and, if a ults file does not exist, it then looks under T3070_ROOT/standard directory which oard_defaults file. The Pin_Map table the board_defaults file or the board file. file can be pin-mapped only once. After the s pin-mapped a flag will be set to identify has already been pin-mapped. Programs the board file first look for a Pin_Map table file. If a Pin_Map table does not exist in the

these programs look in the board_defaults n_Map table.

ywords are summarized in Table 1-6 and detail in the next section of this chapter.

BCF keywords

Description

Indicates a capacitor description.

s Indicates card preference for resource assignment.

s Lists the device.pins connected to each node.

Indicates a connector description.


: The Board File

Connections keyword, or the Devices keyword, or both. For example:capacitorC101 10.00p 10.00 10.00 F PN"0203-0098";

The component description keywords can appear in any order, however, they must precede the connections and the devices keywords.

Each component description must follow the same syntax rules as its associated Board Consultant entry.

There are two BCF configuration tools that you can use to translate component information from a CAD data file that is incomplete or does not match the syntax. The two tools are described in Table 1-5.

The CAD Format Translator (CFT) reads the board_defaults file for default values to complete

informationboard_defa

board direc$AGILENT30

first under tboard_defa

the $AGILENcontains a bmay exist inThe board board file ithat the filewhich read in the boardboard file, file for a Pi

The BCF keexplained in

Table 1-5 BCF configuration tools

Tool Description

board_defaults Fills in information missing in the board file by using the defaults contained in the board_defaults file.

pin name mapping (keyword is Pin_Map)

Uses the Pin_Map table to translate pin names into names required by the 3070 Family.

Table 1-6

Keyword

capacitor

card option

connection

connector

© Agilent T 1-10

Chapter 1

Lists the power supply nodes and the nodes that cannot or should not be driven in library tests. These are specified in the Power Node Options Form of Board Consultant.

Indicates a fuse description.

Lists general purpose relay connections.

ons Specifies test and fixture information.

Includes a heading on the forms list file.

Includes the contents of the specified file at this point in the board file.

Indicates an inductor description.

Describes the internal elements of a device package such as a resistor pack.

Indicates a jumper description.

ons Lists the path names of all library directories that contain library tests of devices on the board to be tested.

BCF keywords (continued)

Description


: The Board File

critical pins Lists device pins that require short wire lengths for sensitive or high speed tests.

cross checked devices

Records devices that have been cross-checked in Board Consultant.

cross checked nodes

Records nodes that have been cross-checked in Board Consultant.

devices Lists the node connected to each device.pin.

device options Specifies test information for a device.

diode Indicates a diode description.

disabling information

Specifies disabling and conditioning information for a device or node. This is also referred to as preconditioning.

end Marks the end of a BCF file, a PIN_MAP table, or the device options.

family options The voltage reference levels for the logic families.

FET Indicates a field effect transistor description.

Table 1-6 BCF keywords (continued)

Keyword Description

fixed nodeoptions

fuse

gp relay options

global opti

heading

include

inductor

internal structure

jumper

library opti

Table 1-6

Keyword

© Agilent T 1-11

Chapter 1

Entriesore, entries are made using the same an error will result. The following example eptable and will generate an error:

10k 10 10 f;20k 10 10 f "message";


: The Board File

Duplicate If two, or midentifiers, is NOT acc

"R1""R1"

node library Indicates a node-based library/cluster description.

nodes Lists all nodes with failure messages, and all nodes that are not listed under Devices or Connections.

override Changes one or more device options.

pin library Pin-based library/cluster description.

pin_map Marks the start of a Pin_Map table.

potentiometer Potentiometer description.

resistor Indicates a resistor description.

switch Indicates a switch description.

transistor Indicates a transistor description.

unconnected pin

Specifies how unconnected pins are labeled.

undefined Lists devices referenced by a CONNECTION statement, but which have not been defined by a device definition.

zener Indicates a zener description.

Table 1-6 BCF keywords (continued)

Keyword Description

© Agilent T 1-12

Chapter 1

BoardPin_Map on page 1-63

CTED Unconnected Pin on page 1-65

IONS Connections on page 1-66

PINS Dangling Pins on page 1-67

Devices on page 1-67

PINS Critical Pins on page 1-67

E

Internal Structure on page 1-68

Cross Checked Devices on page 1-68

Cross Checked Nodes on page 1-68

ION

Disabling Information (Preconditioning) on page 1-68

End on page 1-77

Board file modules (continued)

See Section


: The Board File

File Structure A board file can contain the modules in Table 1-7.

Table 1-7 Board file modules

Module See Section

INCLUDE Include on page 1-13

HEADING Heading on page 1-13

GLOBAL OPTIONS

Global Options on page 1-14

DEVICE OPTIONS Device Options on page 1-21

FAMILY OPTIONS Family Options on page 1-25

CARD OPTIONS Card Options on page 1-28

FIXED NODE OPTIONS

Fixed Node Options on page 1-29

GP RELAY OPTIONS

GP Relay Options on page 1-30

LIBRARY OPTIONS

Library Options on page 1-32

OVERRIDE Override on page 1-32

Device Definitions

Device Definitions on page 1-33

NODES Nodes on page 1-62

PIN_MAP

UNCONNEPIN

CONNECT

DANGLING

DEVICES

CRITICAL

INTERNALSTRUCTUR

CROSS CHECKEDDEVICES

CROSS CHECKEDNODES

DISABLINGINFORMAT

END

Table 1-7

Module

© Agilent T 1-13

Chapter 1

nodes (if any)ay options (if any)y options (if any)e definitionsl pins (if any)ctions/devicesal structure (if any)

l, include statement allows the contents of file to be inserted at this point in the board e statements can be nested to any depth; this incorporating standard options and ns into new board files. When the new file e information from the included file rt of the new file. The included filename can or an absolute pathname. The filename losed in quotes. For example:DE "/board/std_options";

g keyword enables you to include a heading d file listing, board.l. The heading can be racters in length, must be enclosed in

is terminated by a semicolon. For example:

ifier Board Configuration File";


: The Board File

NOTEAgilent Multiple Board Versions includes a VERSIONS section and versions parameters throughout the board file that are not included in this chapter; see Chapter 5, Multiple Board Versions in Optional Board Test Applications for details.

You can specify a listing format for the board file. Use the bcf list format field of the Global Options Entry Form of Board Consultant to specify the listing formats in Table 1-8.

A board file, capable of enabling test and fixture generation, must include at least:

� global options� device options� family options (if any)� card options (if any)

� fixed � gp rel� librar� devic� critica� conne� intern

IncludeThe optionaa specified file. includis useful forconfiguratiois stored, thbecomes pabe a relativemust be enc

INCLU

HeadingThe headinon the boarup to 80 chaquotes, and

HEADING"Ampl

Table 1-8 bcf list format field options

Option Description

device Specifies a device format listing.

node Specifies a node format listing.

both The format to include devices and nodes.

© Agilent T 1-14

Chapter 1

options are used by the Fixture Generation d IPG. These are the global options that are ; the default values can be changed in the ults file.

Default Example

EXPRESS Fixture TypeEXPRESS;

FULL Fixture SizeBANK1;


: The Board File

Global OptionsThe Global Options module contains test and fixture information. This information is described in Table 1-9 on page 1-14. If a value is not specified for an option, the value specified in the board_defaults file is used.

The global software anused in BCFboard_defa

Table 1-9 Global options

Option Description Syntax

Fixture Type <type>

The type of fixture. <type> can be:� SIMPLATE� EXPRESS� NO-WIRE� CASSETTE� XG-50� XG-50

CASSETTE� QuickPress� JOT

Fixture Size <size>

The fixture size. <size> can be:� BANK1� BANK2� FULL

© Agilent T 1-15

Chapter 1

OFF Top ProbesAllowed ON;

8 Heavy ProbeForce 8;

4 Light ProbeForce 4;

800 MechanicalDensityThreshold 65;

Default Example


: The Board File

Top Probes Allowed <status>

Specifies if probes are allowed in the top side of the Agilent Express Cassette fixture.

<status> can be:� ON� OFF

Heavy Probe Force <force>

The pressure (in ounces) exerted by a heavy weight probe. The probe pressure is used in calculating the maximum probe density on the board.

<force> is a <numeric constant>

Light Probe Force <force>

The pressure (in ounces) exerted by a light weight probe. The probe pressure is used in calculating the maximum probe density on the board.

<force> is a <numeric constant>

Mechanical Density Threshold <value>

Maximum density (in ounces per square inch) for mechanically operated fixtures. This is used to calculate the maximum allowed probes per square inch.

<value> is a <numeric constant>

Table 1-9 Global options (continued)

© Agilent T 1-16

Chapter 1

104 Vacuum DensityThreshold 50;

autofile 2062;

COMBINATIONAL Test StrategyCOMBINATIONAL;

MANUAL WireWrappingAUTO;

Default Example


: The Board File

Vacuum Density Threshold <value>

Maximum density (in ounces per square inch) for vacuum operated fixtures. This is used to calculate the maximum allowed probes per square inch.

<value> is a <numeric constant>

Autofile <code> A numeric code to automatically identify the fixture that is loaded on the testhead. The range of autofiles is 11 to 4094.

<code> is a <numeric constant>

Test Strategy <strategy>

The test strategy being used to test the board. The strategy chosen will affect the defaults for node accessibility.

<strategy> can be:� COMBINATIONAL� EDGE

CONNECTOR ONLY

WireWrapping <method>

Method of wirewrapping to be performed on the fixture. Use AUTO for semi or fully automatic wirewrapping. Use WIRELESS for PCB-type fixtures.

<method> can be:� MANUAL� AUTO� WIRELESS� SEMI AUTO

© Agilent T 1-17

Chapter 1

OFF Metric UnitsON;

100m Common LeadResistance0.100;

1u Common LeadInductance 10u;

OFF CapacitanceCompensationON;

Default Example


: The Board File

Metric Units <status>

Indicates if metric units should be used in the reports and files written by the Fixture Generation Software.


Common Lead Resistance <ohms>

The typical resistance in the probe and trace to the device under test. The range of acceptable values is 0.1m ohm to 100 ohms. The default is 0.1 ohms.

<ohms> is a <numeric constant>

Common Lead Inductance <henries>

The typical inductance in the probe and trace to the device under test. The range of acceptable values is 0.1n Henry to 1m Henry. The default is 1u Henry.

<henries> is a <numeric constant>

Capacitance Compensation <status>

Specifies whether or not to use capacitance compensation for small capacitors.

© Agilent T 1-18

Chapter 1

42 IPG DigitalResistanceThreshold 50

1 PreconditioningLevels 2;

Default Example


: The Board File

IPG Digital Resistance Threshold <ohms>

The minimum threshold for determining a digital device short. The default value is 42 ohms.


Precondition Levels <n>

The number of levels that Agilent IPG should repeat the preconditioning process of devices that can affect the device under test. Multiple levels allow for additional preconditioning for devices that are not directly connected to the DUT, but affect the outputs of other preconditioned devices. Default is for one level.

<n> is an <integer constant greater than 0>

© Agilent T 1-19

Chapter 1

zero AdditionalBoard Voltage20;

OFF Use DriveThruON

Default Example


: The Board File

Additional Board Voltage <n>

Specifies the MAXIMUM applied or generated voltage on the DUT from a source other than the Agilent 3070 DUT power supplies. This includes on board power supplies, external power sources, fixture electronics, and dc-to-dc converters.

<n> is an <integer constant between zero and 100>

Use Agilent DriveThru Test <status>

Use DriveThru Test, a Dynamic Test Access technique that allows you to test digital devices through resistors. enabled. If the DriveThru feature is installed and enabled, status is set to ON. If you do not wish to use DriveThru test techniques, status can be set to OFF.

<status> can be:

ON

OFF

© Agilent T 1-20

Chapter 1

10K DriveThruImpedance 10000

OFF Boundary ScanOverdrive ON

OFF Boundary ScanDisable ON

Default Example


: The Board File

DriveThru Impedance Threshold <ohms>

Maximum impedance of devices that can be tested through using DriveThru Test. This threshold can be applied to resistors, capacitors, and inductors. The default setting is 10K Ohms.


Boundary Scan Overdrive <status>

You can turn boundary-scan overdrive on if you have the Advanced Boundary-Scan software on your system. Turning overdrive on allows overdriving of the TDI/TDO pins of a boundary-scan device that is part of a chain of boundary-scan devices.

<status> can be:

ON

OFF

Boundary Scan Disables <status>

Enables automatic Boundary Scan Disabling. If Boundary Scan Disable is turned on, Boundary Scan Overdrive is automatically set to OFF.

<status> can be:

ON

OFF

© Agilent T 1-21

Chapter 1

OFF Boundary ScanOverride ON

OFF

100

Default Example


: The Board File

Device OptionsThe device options described in Table 1-10 on page 1-22 affect how tests are generated for each component. IPG uses these options to develop component tests. These options remain in effect for all component tests unless overridden, with the OVERRIDE keyword, for an individual component. These are the device options that are used in BCF; the default values can be changed in the board_defaults file.

Boundary Scan Chain Override <status>

Allows manual additions of chain descriptions to the board file. Also includes chain descriptions in the listing of the board file.

<status> can be:

ON

OFF

Ground Bounce Suppression <status>

Powered Shorts Shorting Radius <mils (.001 in) int.>

© Agilent T 1-22

Chapter 1

Default Example

5 ToleranceMultiplier 5.0;

ON Remote Sensing ON;


: The Board File

Table 1-10 Device options


Tolerance Multiplier <value>

Indicates how accurate a test you want IPG to write. The lower the value of tolerance multiplier the more accurate a test is generated. More accurate tests may require more resources and more test execution time.

<value> is a <numeric constant from 0.1 to 10>

Remote Sensing <status>

Specifies whether or not IPG should use remote sensing where needed. Remote sensing requires no additional probes but uses more testhead resources.

© Agilent T 1-23

Chapter 1

10 fuse threshold 3.0;

1m Diode Current 1m;

1m Zener Current 0.5m;

Default Example


: The Board File

Fuse Threshold <ohms>

The resistance value, in ohms, used to determine the presence of a fuse. If the measured value is less than, or equal to, the specified threshold, the fuse is considered present and the test passes.


Diode Current <amps>

Maximum value of current, in amps, flowing through the diode while its voltage is being measured.

<amps> is a <numeric constant>

Zener Current <amps>

Maximum value of current, in amps, flowing through the zener while its voltage is being measured.

<amps> is a <numeric constant>

Table 1-10 Device options (continued)

© Agilent T 1-24

Chapter 1

t

ACCURATE Adjust ACCURATE;

Default Example


: The Board File

Adjust <status>

The test adjust option for variable device tests. This keyword can specify: no operator adjustment, adjustment every time, or adjustment only when needed.

<status> can be:� NONE (Never allow the

operator to adjust the device.)

� ACCURATE (Require the operator to adjust the device every time and respond with the YES or NO keypad.)

� FAST (Require the operator to adjust the device and respond with YES or NO, only if the initial device measuremenfails.)

© Agilent T 1-25

Chapter 1

no family options to be specified, include ILY OPTIONS keyword followed by a

For example:Y OPTIONS;

option is described Table 1-11.

.)

OFF Upstream DisableON;

OFF Upstream ConditionON;

Default Example


: The Board File

Family OptionsFamily Options specify the reference level voltage values to be used for the logic families present on the board under test. Each option must be terminated with a semi-colon (;).

If there are only the FAMsemicolon.

FAMIL

Each family

Upstream Disable <status>

Specifies whether or not IPG should try to disable devices that must be overdriven for digital device tests.

<status> can be:� OFF (IPG does not try to

disable upstream devices� ON (IPG tries to disable

upstream devices.)

Upstream Condition <status>

Specifies whether or not IPG should try to set upstream devices to the state specified in the device test. If Upstream Disable is also turned on, IPG tries to disable the device first, if the device cannot be disabled, IPG then tries to condition the device.

<status> can be:� OFF (IPG does not try to

condition upstream devices.)

� ON (IPG tries to conditionupstream devices.)

© Agilent T 1-26

Chapter 1

Example

ing constant> TTL

ic constant Drive High 3.5;

ic constant Drive Low 0.8;

ic constant Receive High 2.0;

ic constant Receive Low 0.8;

ic constant> Edge Speed 100;


: The Board File

Table 1-11 Family options


<Family-id> Name of the logic family being defined. The name must correspond to a logic family named in a device library.

<Family-id> is a <str

Drive High <value> The voltage used to drive a node to a logic 1.

<value> is a <numerfrom -3.5 to 5>

Drive Low <value> The voltage used to drive a node to a logic 0.


Receive High <value> The lowest voltage that can be considered a logic 1.


Receive Low <value> The highest voltage that can be considered a logic 0.


Edge Speed <value> The edge transition speed in volts per microsecond rounded to the nearest increment of 25. The range of edge speed is 25 to 275 volts/uSec.

<value> is a <numer

© Agilent T 1-27

Chapter 1

Open Input Default 0;

Load NONE;

Example


: The Board File

Open Input Default <level>

The logic level that an unconnected input pin assumes. Valid values are 0, 1, or X for don't care.

<level> can be:� 0� 1� X

Load <value> The load to be placed on outputs. There can be no load, a pull up resistor, or a pull down resistor.

<value> can be:� NONE� UP� DOWN

Table 1-11 Family options (continued)

© Agilent T 1-28

Chapter 1

CARD OPTIONS

Description

> Name of the logic family. The name must correspond to a logic family named in the family options.

Only Hybrid Card resources should be assigned. This is the default if no preference for a logic family is specified.

Only ChannelPlus Card resources should be assigned.

Preference of Hybrid Card resources over ChannelPlus Card resources. Semicolons as separators indicate a preference.

Preference of ChannelPlus Card resources over Hybrid Card resources. Semicolons as separators indicate a preference.

No card preference for selection of resources. Commas as separators indicate equal preference.

No card preference for selection of resources. Commas as separators indicate equal preference.


: The Board File

Card OptionsThe card options specify which card or cards the fixturing software uses to assign resources for a particular logic family in digital testing. If no card options are specified, the fixturing software assigns HybridPlus Card resources only. The Card Options are described in Table 1-12 on page 1-28.

Example 1-1 CARD OPTIONS syntax

CARD OPTIONS<Family-id>

<preference list>

<Family-id> is a <string constant>

<preference list> can be:HYBRID;CHANNEL;HYBRID; CHANNEL;CHANNEL; HYBRID;HYBRID, CHANNEL;CHANNEL, HYBRID;

Example:CARD OPTIONS

TTLCHANNEL; HYBRID;

CMOSHYBRID, CHANNEL;

Table 1-12

Option

<Family-id

HYBRID;

CHANNEL;

HYBRID; CHANNEL;

CHANNEL;HYBRID;

HYBRID, CHANNEL;

CHANNEL,HYBRID;

© Agilent T 1-29

Chapter 1

FIXED NODE OPTIONS

Description

Name of the node.

An integer that specifies the DUT power supply.

A numeric constant that specifies the output voltage of the power supply. The voltage is specified in volts.

A numeric constant that specifies the maximum current output of the specified power supply. The current is specified in amps.

Indicates that no DUT supply should be connected to the node.

> Name of the logic family associated with the node. The name should correspond to a logic family named in a device library. ALL refers to all families.

Can be 1, 0, or X to indicate the logic level.


: The Board File

Fixed Node OptionsFixed Node Options can have two sections: a list of the power supply nodes and a list of the fixed nodes. Fixed nodes are any nodes that cannot or should not be driven in library tests. Each fixed node must have a logic level specified for all families connected to it. Each node connected to a power supply, and any fixed nodes must be listed here. A fixed node can be a node connected to a power node through a jumper or very small resistor. You must specify one ground node; you cannot specify more than one ground node. The Fixed Node Options are described in Table 1-13 on page 1-29.

Example 1-2 FIXED NODE OPTIONS syntax

Power Nodes Section Syntax:<node-id> No_Supply<node-id> supply <number> at <voltage>

volts, <current> amps;

Fixed Nodes Section Syntax:<node-id> Family <Family-id> is <value>;

Example of Fixed Node Options:FIXED NODE OPTIONS

VCC Family TTL is 1;V+ Family ALL is 1;GND Family ALL is 0;VCC Supply 1 at 5.0 volts, 1.2 amps;GND Ground;

Table 1-13

Option

<node-id>

<number>

<voltage>

<current>

No_Supply

<Family-id

<value>

© Agilent T 1-30

Chapter 1

GPRELAY OPTIONS syntax

TIONSe_id>;erence list>;e_id> <options>;erence list>;e_id> <options>, <second node_id>;erence list>;

and <second node_id) are <string

can be:

e list> can be:;

; ACCESS;CONTROL;

, ACCESS;CONTROL;

RELAY OPTIONSGP "U1-2", "U1-3";

CONTROL; ACCESS;GP N10 is HIGH,N11;

CONTROL, ACCESS;GP EXT1 is HIGH;

ACCESS;


: The Board File

GP Relay OptionsThe GP Relay Options Form assigns general purpose (GP) relays to pairs of nodes or individual nodes. GP relays are located on the Control Card and the AccessPlus Card. If you have both cards in your board configuration file, then you can specify a card preference for assigning GP relays. The fixturing software will consider your preference when assigning the GP resources. If no preference is specified, the system assigns GP relays from the Control Card first. The GP Relay Options are described in Table 1-12 on page 1-28.

Example 1-3

GPRELAY OPGP <nod

<prefGP <nod

<prefGP <nod

<pref

<node_id>constants>

<options>is HIGHis LOW

<preferencCONTROLACCESS;CONTROLACCESS;CONTROLACCESS,

Example:

GP

© Agilent T 1-31

Chapter 1

e node.

node.

e name must be preceded by a comma.

ned.

ccessPlus Card GP relay. This is the default if parators indicate a preference.

r a Control Card GP relay. Semicolons as

mas as separators indicate equal preference.

mas as separators indicate equal preference.


: The Board File

Table 1-14 GPRELAY OPTIONS

Option Description

<node_id> Name of a node.

is HIGH Assigns the high contact of the GP relay pair to th

is LOW Assigns the low contact of the GP relay pair to the

<second node_id> Name of the second node of a node pair. The nod

CONTROL; Only Control Card GP relays should be assigned.

ACCESS; Only AccessPlus Card GP relays should be assig

CONTROL; ACCESS; A preference of a Control Card GP relay over an Ano card preference is specified. Semicolons as se

ACCESS; CONTROL; A preference of an AccessPlus Card GP relay oveseparators indicate a preference.

CONTROL, ACCESS; No card preference for selection of GP relay. Com

ACCESS, CONTROL; No card preference for selection of GP relay. Com

© Agilent T 1-32

Chapter 1

nce Multiplier

te Sensing

hold

Current

t

Current

eam Condition

eam Disable


: The Board File

Library OptionsLibrary Options contains an ordered list of directories that Agilent IPG searches to locate library tests on each device. List custom library directory pathnames first to guarantee that they override any standard libraries. This also decreases the amount of time for IPG to find custom libraries.

Example 1-4 LIBRARY OPTIONS syntax:

LIBRARY OPTIONS<library pathname>

<library pathname> Specifies the pathname ofthe library to be searched. Quotes areoptional.

Example:LIBRARY OPTIONS

custom_lib“$AGILENT3070_ROOT/library/ttl"“$AGILENT3070_ROOT/library/cmos";

OverrideUse the OVERRIDE keyword to change one or more device options for a specific component; include only the options you wish to change. The override statement must be placed immediately after the device definition line for that component. The device options that can be overridden are:

� Tolera

� Remo

� Thres

� Diode

� Adjus

� Zener

� Upstr

� Upstr

© Agilent T 1-33

Chapter 1

1 PN"74ls174"; ! This is apack part description library.

OVERRIDETolerance Multiplier 5;Diode Current 2m;

finitionsnitions supply information about the devices d. Each component has its own device

omponents of identical type are grouped er the keyword for that type of device. Each ition contains information such as the name t component, its value (if there is one), r high and low values (where applicable), other measurement parameters. Device can also have part number and message message entries are failure messages which on the report device if the device fails.

nent entry under a device definition ust be terminated by a semi-colon (;).

s (") are optional on reference designators. rence designator identifies a device or a

e.pin. For more information, see Identifiers rence Designators and Node Names) on 1-8.


: The Board File

Example 1-5 OVERRIDE syntax

OVERRIDE <option> <new value>

<option> can be:Tolerance MultiplierRemote SensingThresholdDiode CurrentAdjustZener CurrentUpstream DisableUpstream Condition

<new value> must be a legal parameter for thedevice type.

Examples:CAPACITOR

"C1" .01u 10 5 f;OVERRIDE Tolerance Multiplier 1.0;

DIODE"CR1" 800m 300m;

OVERRIDE Remote Sensing ON;FUSE

"F1" 3OVERRIDE Threshold 1.5;

POTENTIOMETER"P1" 10K 10 10 "Input

Offset Adjust";OVERRIDE Adjust Accurate;

PIN LIBRARYU101 PN"74ls174";

OVERRIDE Upstream Disable OFF;

DPdiode

Device DeDevice defion the boardefinition. Ctogether unddevice definor id for thatolerances oand variousdefinitions entries. Theare reported

Each compokeyword m

NOTEQuoteA refedevic(Refepage

© Agilent T 1-34

Chapter 1

e capacitor is to be tested with Agilent eck and not to be tested with an analog pacitor test. If you specify Polarity Check, so indicate which pin (1 or 2) is the negative PACITOR syntax is shown in Example 1-6. are described in Table 1-15.


: The Board File

The device definition keywords are:� CAPACITOR� CONNECTOR� DIODE� FET� FUSE� INDUCTOR� JUMPER� NODE LIBRARY� PIN LIBRARY� POTENTIOMETER� RESISTOR� SWITCH� TRANSISTOR� ZENER

Each keyword is described in this section.

NOTEMultiple Board Versions includes version labels and not placed (NP) parameters in the device definitions that are not included in the following sections; see Chapter 5, Multiple Board Versions in Optional Board Test Applications for details.

CapacitorThe CAPACITOR keyword indicates a list of capacitor entries. The entries must include the capacitor name, its capacitance, plus and minus tolerances, and the capacitor type (fixed or variable). The capacitor part number and failure message are optional. You can also

specify if thPolarity Chin-circuit cayou must alpin. The CAThe options

© Agilent T 1-35

Chapter 1

ent>;

of the capacitor

n time";


: The Board File

Example 1-6 CAPACITOR syntax

CAPACITOR<device> <value> <+tol> <-tol> <type>;<device> <value> <+tol> <-tol> <type> <options>;<device> <value> <+tol> <-tol> <type> <component>;<device> <value> <+tol> <-tol> <type> <options> <compon

<device> is a <string constant>

<value>, <+tol>, <-tol> are <numeric constants>

<type> can be:FV

<options> can be:PC <#>NTPC <#> NT<#> is an integer that indicates the negative terminal

<component> can be:PN<part number><failure message>

PN<part number> <message><part number> & <failure message> are <string constants>

Examples:CAPACITOR

C1 10p 10 10 NT F;"C4" 0.01n 10 5 V PN"0667-9384" "varies integratio

© Agilent T 1-36

Chapter 1

ly specified. The Connector options are Table 1-16.

capacitor value; both are positive numbers.

larity Check and an analog in-circuit capacitor <#> NT specifies that the device will be tested

um, no spaces allowed, must be in quotes).

aracters maximum, must be in quotes).


: The Board File

ConnectorThe CONNECTOR keyword indicates a list of connector entries. After the CONNECTOR keyword, you can enter any number of connectors by specifying the connector name and an optional failure message. Each entry is terminated by a semicolon. IPG does not generate tests for connectors. The connector must be specified as Not Tested (NT). If the connector is not specified as NT a warning is issued and NT is

automaticaldescribed in

Table 1-15 CAPACITOR options

Option Description

<device> Name of the capacitor (48 characters maximum).

<value> Value of the capacitor.

<+tol> and <-tol> The plus and minus tolerances as percentages of the

F The capacitor value is fixed.

V The capacitor value is variable.

<options> PC <#> Indicates that the device will be tested with Potest; NT specifies that the device will not be tested; PCwith Polarity Check only.

PN<part number> The part number of the capacitor (24 characters maxim

<failure message> Failure message associated with the capacitor (40 Ch

© Agilent T 1-37

Chapter 1

CONNECTOR options

Description

Name of the connector (48 characters maximum).

Specifies no test or TestJet test.

er> The part number of the device (24 characters maximum).

Failure message associated with the connector (maximum 40 characters).


: The Board File

Example 1-7 CONNECTOR syntax

CONNECTOR<device> <test>;<device> <test> <part number>;<device> <test> <failure message>;<device> <test> <part number> <failure

message>;

<test> can be:NTTJ


<part number> is a <string constant>

<failure message> is a <string constant>

Examples:CONNECTOR

A1 NT;"J5" TJ"J5 located on top edge";

Table 1-16

Option

<device>

NT or TJ

<part numb

<failure message>

© Agilent T 1-38

Chapter 1

tages, and an optional failure message or

is terminated by a semicolon. The Diode described in Table 1-17 on page 1-39.

>


: The Board File

DiodeThe DIODE keyword indicates a list of diode entries. The diode descriptions include: the diode name, its high

and low volnote.

Each entry options are

Example 1-8 DIODE syntax

<device> <hi-value> <lo-value>;<device> <hi-value> <lo-value> <options>;<device> <hi-value> <lo-value> <component>;<device> <hi-value> <lo-value> <options> <component>;


<hi-value> & <lo-value> are <numeric constants>

<options> can be:NT

<component> can be:PN<part number><failure message>PN<part number> <failure message><part number> & <failure message> are <string constants

Examples:DIODE

"D1" .8 .4;D2 .8 .4 NT;"D3" .8 .4 PN"1801-9016";D4 .8 .4 "part of bridge rectifier";"D5" .8 .4 NT PN"1801-9016";

© Agilent T 1-39

Chapter 1

d bias voltage.

bias voltage.

, no spaces allowed, must be in quotes).

haracters maximum, must be in quotes).


: The Board File

FETThe FET keyword indicates a list of FET entries. The device description includes: FET name, high and low resistance limits, type, and an optional failure message.

Each entry is terminated by a semicolon. The FET options are described in Table 1-18 on page 1-41.

Table 1-17 DIODE options

Option Description

<device> Name of the diode (48 characters maximum).

<hi-value> The upper test limit, in volts, for the diodes forwar

<lo-value> The lower test limit, in volts, for the diodes forward

NT The device will not be tested.

PN<part number> Part number of the diode (24 characters maximum

<failure message> A failure message associated with the diode (40 c

© Agilent T 1-40

Chapter 1

;

>

7";


: The Board File

Example 1-9 FET syntax

<device> <hi-res> <lo-res> <type>;<device> <hi-res> <lo-res> <type> <options>;<device> <hi-res> <lo-res> <type> <component>;<device> <hi-res> <lo-res> <type> <options> <component>


<hi-res> & <lo-res> are <numeric constants>

<type> can be:NP

<options> can be:NT


Examples:FET

"Q1" 200 100 N;Q2 200 100 P NT;"Q4" 200 100 P "Q4 is located at B

© Agilent T 1-41

Chapter 1

no spaces allowed, must be in quotes).

racters maximum, must be in quotes).


: The Board File

FuseThe FUSE keyword indicates a list of fuse entries. The device description includes: the fuse name, its maximum allowed current for testing, and optionally its part number or failure message. The Fuse options are described in Table 1-19 on page 1-43.

Table 1-18 FET options

Option Description

<device> Name of the FET (48 characters maximum).

<hi-res> The high resistance limit in ohms.

<lo-res> The low resistance limit in ohms.

N Specifies an N-channel FET.

P Specifies a P-channel FET.

NT The device is not tested.

PN<part number> Part number of the FET (24 characters maximum,

<failure message> Failure message associated with the FET (40 cha

© Agilent T 1-42

Chapter 1

>


: The Board File

Example 1-10 FUSE syntax

<device> <max-current>;<device> <max-current> <options>;<device> <max-current> <component>;<device> <max-current> <options> <component>;


<max-current> is a <numeric constant>

<options> can be:NT


Examples:FUSE

"F1" 1.5;F2 1.25 NT "fuse for +5 V supply";

© Agilent T 1-43

Chapter 1

no spaces allowed, must be in quotes).

racters maximum, must be in quotes).


: The Board File

InductorThe INDUCTOR keyword indicates a list of inductor entries. The device description includes: the inductor name, its inductance, plus and minus tolerances, its series resistance, the inductor type (fixed or variable).

It can optionally include the part number, or a failure message. Each entry is terminated by a semicolon. The Inductor options are described in Table 1-20 on page 1-45.

Table 1-19 FUSE options

Option Description

<device> Name of the fuse (48 characters maximum).

<max-current> Maximum value of current in amps.

NT Device is not tested.

PN<part number> Part number of the fuse (24 characters maximum,

<failure message> Failure message associated with the fuse (40 cha

© Agilent T 1-44

Chapter 1

;component>;

>

1A" "Tuning inductor"


: The Board File

Example 1-11 INDUCTOR syntax

<dev> <val> <+tol> <-tol> <series-R> <type>;<dev> <val> <+tol> <-tol> <series-R> <type> <options>;<dev> <val> <+tol> <-tol> <series-R> <type> <component><dev> <val> <+tol> <-tol> <series-R> <type> <options> <

<dev> is a <string constant>

<val>, <+tol>, <-tol> & <series-R> are <numeric constants>

<type> can be:FV

<options> can be:NT


Examples:INDUCTOR

L1 10p 5 5 10 F;"L2" 10u 5 5 10 V NT PN"34921

© Agilent T 1-45

Chapter 1

ctor, as a percentage of its value; both are

inductor.


characters maximum, must be in quotes).


: The Board File

JumperThe JUMPER keyword indicates a list of jumper entries. The device description includes: the jumper name, if it is closed or open, and optionally its part number, or a failure message or both. The Jumper options are described in Table 1-21 on page 1-47.

Table 1-20 INDUCTOR options

Option Description

<dev> Name of the inductor (48 characters maximum).

<val> The value of the inductor, in Henries.

<+tol> and <-tol> Specify the plus and minus tolerances of the induspecified as positive numbers.

<series-R> The value of the series resistance, in ohms, of the

F The inductor is fixed.

V The inductor is variable.


PN<part number> Part number of the inductor (24 characters maxim

<failure message> Failure message associated with the inductor (40

© Agilent T 1-46

Chapter 1

>

stalled later";


: The Board File

Example 1-12 JUMPER syntax

<device> <type>;<device> <type> <options>;<device> <type> <component>;<device> <type> <options> <component>;


<type> can be:O or OPENC or CLOSED

<options> can be:NT


Examples:JUMPER

"JMP1" CLOSED;JMP2 O NT;"JMP3" OPEN NT PN"123-456" "Jumper in

© Agilent T 1-47

Chapter 1

m, no spaces allowed, must be in quotes).



: The Board File

Node LibraryThe NODE LIBRARY keyword indicates a list of node-oriented library entries. The device description includes the device name. To specify that no test should be generated for the device set the no test (NT) flag. You can optionally include the device's library path name and a failure message. The part number of the device is only optional if you set the no test flag. Other options include setting the status of flags such as safeguard off and backtrace on. The Node Library options are described in Table 1-22 on page 1-48.

Table 1-21 JUMPER options

Option Description

<device> Name of the jumper (48 characters maximum).

O or OPEN The jumper is open.

C or CLOSED The jumper is closed.


PN<part number> Part number of the jumper (24 characters maximu

<failure message> Failure message associated with the jumper (40 c

© Agilent T 1-48

Chapter 1

re <string constants>

";

acters maximum).

e.


: The Board File

Example 1-13 NODE LIBRARY syntax

<device>;<device> <options>;<device> <component>;<device> <options> <component>;


<options> can be:NTNS

BT<component> can be:

PN<part number>PN<path/part_number>PN<part number> <failure message>PN<path/part_number> <failure message><part number>, <path/part_number> & <failure message> a

Example:NODE LIBRARY

filter PN"custom_lib/filter"NSBT"functional devicewhole NSBT"functional device";

Table 1-22 NODE LIBRARY options

Option Description

<device> Name of the node-oriented library device (48 char


NS Safeguard information is not needed for this devic

© Agilent T 1-49

Chapter 1

ry (used only for InterconnectPlus tests) is y BSDL<bsdl_id>. The Pin Library options d in Table 1-23 on page 1-51.

can be any combination of <options>, <part er>, <interconnect test>, and <failure ge>, but they must appear in the order

n in the syntax description.

, no spaces allowed, must be in quotes). If not evice name.

be in quotes).



: The Board File

Pin LibraryThe PIN LIBRARY keyword indicates a list of pin-oriented library entries. The device description includes a device name. A no test (NT) flag can be set to specify that no test should be generated for the device. However, for boundary-scan devices, if TAPONLY and NT are specified, the device can still be used as part of a test for a boundary-scan-part chain. You can optionally include the device's part number, its library path name and a failure message. If the no test (NT) flag is not set, a part number must be entered or a syntax error will occur. Other options include setting the status of flags such as safeguard off and backtrace on.

If you have purchased InterconnectPlus software, you can specify additional parameters for the InterconnectPlus tests. InterconnectPlus tests can have two different files: a VCL library and a BSDL library. The VCL library is identified by PN<part_id>. The

BSDL libraidentified bare describe

NOTETherenumbmessashow

BT Backtracing will be used for this device.

PN<part number> Part number of the device (24 characters maximumspecified, the part number is assumed to be the d

PN<path/part_number> The path for library for the specified device (must

<failure message> Failure message associated with the device (40 c

Table 1-22 NODE LIBRARY options (continued)

Option Description

© Agilent T 1-50

Chapter 1

<failure message>;

>

stants>


: The Board File

Example 1-14 PIN LIBRARY syntax

PIN LIBRARY<device>;<device> <options>;<device> <options> PN<part number>;<device> <options> PN<part number> <interconnect test>;<device> <options> PN<part number> <interconnect test>


<options> can be: <option><option> <option><option> <option> ... <option><option> can be:NTNSBTTJLIBCC

<part number> can be:<part number><path/part_number><part_number>, <path/part_number> are <string constants<interconnect test> can be:TS"1149_1" <scan_type> BSDL<bsdl_id> PKG<pkg_type>TS"1149_1" <scan_type> LIB BSDL<bsdl_id> PKG<pkg_type><scan_type> can be:TAPONLYINTERCONNECTONLYSCAN

<bsdl_id> can be:<bsdl_filename><path/bsdl_filename><bsdl_filename> & <path/bsdl_filename> are <string con

<pkg_type> is a <string constant>

<failure message> is a <string constant>

© Agilent T 1-51

Chapter 1

ILED";A FAILED";

bsdl" PKG"dip22"" PKG"DW_PACKAGE"

tests are not generated).

evice.

vice.

his is used for boundary scan and TestJet.

ximum, no spaces allowed, must be in quotes).

ld is optional if the device is not tested.

r the InterconnectPlus test.


: The Board File

Example:PIN LIBRARY

U28 PN"74wb989";AND2 PN"7400" "AND2 located at A-3";RP1 NT PN"/net/parts/library/852-93444" "RP1 FACHA PN"/net/cluster/library/line"NSBT"ChannelU21 PN"su812" TS"1149_1" SCAN LIB BSDL "su812U1 NT PN"8374" TS"1149_1" TAPONLY BSDL"74ct8374

Table 1-23 PIN LIBRARY options

Option Description

<device> Name of the device (48 characters maximum).

NT The device is not tested (VCL and boundary-scan

NS Safeguard information is not needed for the VCL d

BT Backtracing will be used for the VCL functional de

TJ The device will be tested with TestJet.

LIB The device will also be tested with a library test. T

CC The device will be tested with Connect Check.

PN<part number> Part number of the VCL device (24 characters maThis field is optional if the device is not tested.

PN<path/part_number> The library path name for the VCL device. This fie

TS"1149_1" Specifies that test standard 1149_1 will be used fo

© Agilent T 1-52

Chapter 1

can-part chain, but no interconnect or connect ).

t test for the boundary-scan-part chain; no

pathname.



: The Board File

PotentiometerThe POTENTIOMETER keyword indicates a list of potentiometer entries. The device description includes: the potentiometer name, its resistance, plus and minus tolerances, and optionally its part number, or a failure message, or both. The Potentiometer options are described in Table 1-24 on page 1-54.

TAPONLY The device might be used as part of a boundary-stests will be generated (Test Access Points ONLY

INTERCONNECTONLY Pins on the device can be used in the interconnecconnect tests are generated.

SCAN Interconnect and connect tests will be generated.

<bsdl_id> Part number of the device library file and optional

<pkg_type> The package type of the device.

<failure message> Failure message associated with the device (40 c

Table 1-23 PIN LIBRARY options (continued)

Option Description

© Agilent T 1-53

Chapter 1

>


: The Board File

Example 1-15 POTENTIOMETER syntax

<device> <value> <+tol> <-tol>;<device> <value> <+tol> <-tol> <options>;<device> <value> <+tol> <-tol> <component>;<device> <value> <+tol> <-tol> <options> <component>;


<value>, <+tol> & <-tol> are <numeric constants>

<options> can be:NT


Examples:POTENTIOMETER

"R109" 10k 50 50;R2 1000 10 10 "located at P11";"R63" 100 5 5 NT"part of voltage divider";

© Agilent T 1-54

Chapter 1

m).

oth are specified as positive numbers.

aximum, no spaces allowed, must be in

r (40 characters maximum, must be in quotes).


: The Board File

ResistorThe RESISTOR keyword indicates a list of resistor entries. The device description includes: the resistor name, its resistance, plus and minus tolerances, the resistor type (fixed or variable), and optionally its part number and failure message. The Resistor options are described in Table 1-25 on page 1-56.

Table 1-24 POTENTIOMETER options

Option Description

<device> Name of the potentiometer (48 characters maximu

<value> The value of the potentiometer.

<+tol> and <-tol> Plus and minus tolerances of the potentiometer; b


PN<part number> Part number of the potentiometer (24 characters mquotes).

<failure message> Failure message associated with the potentiomete

© Agilent T 1-55

Chapter 1

ent>;

>

"DO NOT adjust resistor";


: The Board File

Example 1-16 RESISTOR syntax

<device> <value> <+tol> <-tol> <type>;<device> <value> <+tol> <-tol> <type> <options>;<device> <value> <+tol> <-tol> <type> <component>;<device> <value> <+tol> <-tol> <type> <options> <compon


<value>, <+tol> & <-tol> are <numeric constants>

<type> can be:FV

<options> can be:NT


Examples:RESISTOR

"R1" 10k 5 5 F;R2 10M 25 25 V PN"09837-88394";"R3" 10M 25 25 V NT PN"09837-88394"

© Agilent T 1-56

Chapter 1

ons are described in Table 1-26 on

tor; both are specified as positive numbers.




: The Board File

SwitchThe SWITCH keyword indicates a list of switch entries. The device description includes: the switch name, the common-pin, the contact-pin if the switch is closed, and optionally its part number, or a failure message, or both. The common-pin and contact-pin are assumed to be shorted together. Using OFF in place of the contact-pin implies that the switch is open. The switch entry shows only the common pin shorted to one other pin (<contact pin>), or the common pin open (OFF). The

Switch optipage 1-58.

Table 1-25 RESISTOR options

Option Description

<device> Name of the resistor (48 characters maximum).

<value> The value of the resistor, in ohms.

<+tol> and <-tol> Specify the plus and minus tolerances of the resis

F The resistor is fixed.

V The resistor is variable.


PN<part number> Part number of the resistor (24 characters maximu

<failure message> Failure message associated with the resistor (40 c

© Agilent T 1-57

Chapter 1

ional)

>

n 2.ntacts.nd not tested.


: The Board File

Example 1-17 SWITCH syntax

<device> <common-pin> <contact>;<device> <common-pin> <contact> NT;<device> <common-pin> <contact> <component>;<device> <common-pin> <contact> NT <component>;

<device> & <common-pin> are <string constants> (quotes opt

<contact> can be:<contact-pin>OFF

<contact-pin> is a <string constant> (quotes optional)


Examples:SWITCH

"SW1"12; ! Switch 1 closed pin 1 to piSW2 1 OFF; ! Switch 2 open, no closed coSW3 1 2 NT "Channel Selector";! Switch 3 closed a

© Agilent T 1-58

Chapter 1




: The Board File

TransistorThe TRANSISTOR keyword indicates a list of transistor entries. The device description includes: the transistor name, its high and low beta values, its type (npn or pnp), and optionally a part number, or a failure message, or both. The Transistor options are described in Table 1-27 on page 1-60.

Table 1-26 SWITCH options

Option Description

<device> Name of the switch (48 characters maximum)

<common-pin> The COMMON pin in the switch.

<contact-pin> The CONTACT pin in the switch.

OFF The switch is OFF; the contacts are open.


PN<part number> Part number of the switch (24 characters maximu

<failure message> Failure message associated with the switch (40 ch

© Agilent T 1-59

Chapter 1

t>;

>

p";cuit";


: The Board File

Example 1-18 TRANSISTOR syntax

TRANSISTOR<device> <hi-beta> <lo-beta> <type>;<device> <hi-beta> <lo-beta> <type> <options>;<device> <hi-beta> <lo-beta> <type> <component>;<device> <hi-beta> <lo-beta> <type> <options> <componen


<hi-beta> & <lo-beta> are <numeric constants>

<type> can be:NP

<options> can be:NT


Examples:TRANSISTOR

"Q1" 200 50 N;Q2 200 50 P "Q2 located at C5";"Q3" 200 50 N PN"1854-0056" "pre-am"Q4" 250 50 P NT "Not Tested in-cir

© Agilent T 1-60

Chapter 1

ta.


characters maximum, must be in quotes).


: The Board File

ZenerThe ZENER keyword indicates a list of zener entries. The device description includes: the zener name, its voltage, plus and minus tolerances, and optionally a part number, or failure message, or both. The Zener options are described in Table 1-28 on page 1-61.

Table 1-27 TRANSISTOR options

Option Description

<device> Name of the transistor (48 characters maximum).

<hi-beta> and <lo-beta> Specify the high and low limits for the transistor be

N The transistor is an NPN.

P The transistor is a PNP.


PN<part number> Part number of the transistor (24 characters maxim

<failure message> Failure message associated with the transistor (40

© Agilent T 1-61

Chapter 1

>

r, as a percentage of the zener's value; both


: The Board File

Example 1-19 ZENER syntax

ZENER<device> <voltage> <+tol> <-tol>;<device> <voltage> <+tol> <-tol> <options>;<device> <voltage> <+tol> <-tol> <component>;<device> <voltage> <+tol> <-tol> <options> <component>;


<voltage>, <+tol> & <-tol> are <numeric constants>

<options> can be:NT


Example:ZENER

"CR50" 5.6 5 5 "located at A7";

Table 1-28 ZENER options

Option Description

<device> Name of the zener (48 characters maximum).

<voltage> The breakdown voltage, in volts, of the zener.

<+tol> and <-tol> Specify the plus and minus tolerances of the zeneare specified as positive numbers.

© Agilent T 1-62

Chapter 1

ts all nodes that are not listed under Devices ons.

1 NODES syntax:

_id>_id>

Specifies the name of the node.

C "Main Power Bus";"Aux Power Bus";

AS "Converter Reference Level";

, no spaces allowed, must be in quotes).



: The Board File

UndefinedThis is a temporary block for devices which have not been defined by a device definition. Undefined devices must be resolved before the board file can be compiled.

Example 1-20 UNDEFINED syntax:

UNDEFINED<device name> NT

<device name> Specifies the name of thedevice which has been referenced in aconnection statement, but has not beendefined by a device definition.

Example:UNDEFINED

U11 NT;CR4 NT;

NodesNODES lisor Connecti

Example 1-2

NODES<node<node

<node_id>

Examples:NODES

VCV+BI


PN<part number> Part number of the zener (24 characters maximum

<failure message> Failure message associated with the zener (40 ch

Table 1-28 ZENER options (continued)

Option Description

© Agilent T 1-63

Chapter 1

ames on both systems. For example, the ENT3070_ROOT factory default value is p3070. In this document, only path names the environment variable are used. If you use actual path names, refer to older versions documentation. Please see The Root tory Environment Variable in nistering Agilent 3070 UNIX Systems for r information.

P keyword indicates a pin name mapping in naming conventions required by board he board compiler are shown in Table 1-29.

PIN_MAP keywords

Pin

Must match the library pin names (e.g., 1, 2, 3)

1, 2

1, 2

1, 2

ap 1, 2

1, 2

ter 1, W(iper), 2


: The Board File

Pin_MapYou can use a Pin_Map to translate device pin names. This is useful when your CAD data file used pin names other than what Agilent Board Consultant accepts. For example, your CAD data file may have specified transistor pins as 1, 2, and 3, instead of E, B, and C as required by Board Consultant. In this case, use a Pin_Map to translate the 1, 2, and 3 to E, B, and C. The Pin_Map can be placed in the board_defaults file which can reside in the local board directory, or under $AGILENT3070_ROOT/standard. The Pin_Map can also be part of the board file. If no pin name mapping table exists, and the pin names are invalid, the compiler generates an error for each invalid pin name. These errors are included in the list file (board.l) when you compile the board file with the list option. Pin mapping occurs only once for the board file. Either the board compiler or the check board program performs this operation. Pin mapping is not allowed to occur more than once because the original pin map could recursively re-map the pins to an invalid state.

NOTEWith Agilent 3070 software revision 3070 04.00pa, an environment variable was created so that files can be easily transferred between UNIX® and MS Windows® controllers, which have different file systems. The environment variable, $AGILENT3070_ROOT, replaces the upper

path n$AGIL

/var/husingmust of theDirecAdmifurthe

The PIN_MAtable. The pforms and t

Table 1-29

Keyword

Pin Library

Capacitor

Fuse

Inductor

Jumper/Str

Resistor

Potentiome

© Agilent T 1-64

Chapter 1


: The Board File

The maximum length of the input name is 80 characters. The new pin name must be 8 characters or less. An error results if the pin mapping leads to an error in pin name uniqueness. Also, an error results for all devices in which the device type was unknown and therefore, the device could not be mapped. These devices are included in the compiler list file (board.l).

The names must be separated by one or more blanks and each pin map entry is terminated by a semicolon. More than one original pin name can be mapped to the same new pin name.

NOTEEach PIN_MAP entry must be terminated by a semicolon.

Diode A(node), C(athode)

Zener A(node), C(athode)

Transistor E(mitter), B(ase), C(ollector)

FET S(ource), G(ate), D(rain)

Connector Flexible

Switch Flexible

Table 1-29 PIN_MAP keywords (continued)

Keyword Pin

© Agilent T 1-65

Chapter 1

N 2;TENTIOMETER3 W;ODE1 A;+ A;2 C;- C;ANSISTOR1 E;2 B;3 C;TN-Source S;N-Gate G;N-Drain D;

ted PinNNECTED PIN keyword specifies a symbol t is deliberately left unconnected. Any

d pins must be declared before the devices tions sections of the board file. Fixture not report these pins as errors.

3

cted pin NC;


: The Board File

Example 1-22 PIN_MAP syntax

PIN_MAP<device type>

<old pin-id> <new pin-id>;<old pin-id> <new pin-id>;

. . .<device type>

<old pin-id> <new pin-id>;<old pin-id> <new pin-id>;

. . .END

<old pin-id> & <new pin-id> are <stringconstants>

<device type> can be:CAPACITORCONNECTORDIODEFETFUSEINDUCTORJUMPERPIN LIBRARYPOTENTIOMETERRESISTORSWITCHTRANSISTORZENER

EAXAMPLEPIN_MAP

CAPACITORP 1;

PO

DI

TR

FE

END

UnconnecThe UNCOfor a pin thaunconnecteand connecverify does

Example 1-2

unconne

© Agilent T 1-66

Chapter 1

4

CTED PIN NC;IONS

1.11.21.301.10;

01.61.6

01.71.7

01.81.8001.1;101.2;201.3;

01.5;

01.9;ING PINS01.4;


: The Board File

ConnectionsThe CONNECTIONS keyword starts a list of the device pins that are connected to each node. It is the complement of the DEVICES keyword. The board file can contain CONNECTIONS or DEVICES or both. The last segment of the CONNECTIONS block lists the known unconnected pins. An unconnected pin is a pin that is defined as having no connections to it. The unconnected pins list is defined by the UNCONNECTED PIN keyword. Another list of pins, called DANGLING PINS (no connection to anything) can be appended to the end of the CONNECTIONS block. Dangling pins are pins discovered by the compiler that were not defined as unconnected or connected pins.

Example 1-2

UNCONNECONNECT

VCCRPRPRPU1

DATA0U1RP

DATA1U1RP

DATA2U1RP

inputU1

inputU1

inputU1

GNDU1

NCU1

DANGLU1

© Agilent T 1-67

Chapter 1

G PIN) shows an empty string ("") for its

5

VCCVCCVCCVCCDATA0DATA1DATA2DATA3;

NC"" ! A dangling pin

sAL PINS keyword starts a list of the device uire short wire length due to sensitive or

measurements.

6

L PINS12


: The Board File

Dangling PinsDangling pins are pins that are not defined as being connected or unconnected. Dangling pins can appear in both the CONNECTIONS and DEVICES blocks. If a board translator, such as translate cad cannot find a connection definition for a pin, this pin is defined as dangling. The DANGLING PINS category in the CONNECTIONS block lists all the device.pins that are not defined in the CONNECTIONS block. A dangling pin in the DEVICES block appears as a pair of empty quotes (""). Dangling pins are treated as unconnected pins. For examples, see both Device Definitions on page 1-33 and Connections on page 1-66.

DevicesThe DEVICES keyword starts a list of the nodes connected to each device pin. It is the complementary representation of CONNECTIONS. The board file can contain the DEVICES list, or the CONNECTIONS list, or both.

The device pin and the node name are separated by a period (.). All pin.node combinations must be separated by at least one blank, and each device pin.node set is terminated by a semicolon.

Pins that are defined as unconnected show the UNCONNECTED PIN id for their nodes. Any pin that was not defined as connected or unconnected

(DANGLINnode.

Example 1-2

DEVICESRP1

1.2.3.4.5.6.7.8.

R21.2.

Critical PinThe CRITICpins that reqhigh speed

Example 1-2

CRITICAU102.Y1.3;

© Agilent T 1-68

Chapter 1

cked Devicese Cross Checked Devices list to record have been crosschecked in Board It is not intended to be entered manually.

cked Nodese Cross Checked Nodes list to record nodes en cross-checked in Board Consultant. It is to be entered manually.

Information (Preconditioning)formation specifies the conditioning or a device, pin, or node on the board for a test tests. Conditioning and disabling are s preconditioning. Preconditioning sets a r device to some specific state, and holds it nimize its effect on the device under test.

to Chapter 2, Vector Control Language ) in Test Methods: Digital for more ation about preconditioning.

ning information is listed in the G INFORMATION block.


: The Board File

Internal StructureInternal structure describes the parent-child hierarchy of composite devices. Composite devices can be device packages such as resistor packs, switch packs, etc. or clusters of devices. Each parent device must list all of its child devices using the Internal Structure description. A parent device must be a PIN LIBRARY or NODE LIBRARY component. A child device can be any type of component, including PIN LIBRARY or NODE LIBRARY. The hierarchy can be continued to any depth, but the final children must be non-composite, that is, they can have not children. The internal structure keyword is repeated for each parent device.

Example 1-27

INTERNAL STRUCTURE filter;U101;U102;U103;U104;

NOTESee Chapter 3, Creating Board Information in Test and Fixture Development for instructions on entering internal devices with Board Consultant.

Cross CheBCF uses thdevices thatConsultant.

Cross CheBCF uses ththat have benot intended

Disabling Disabling indisabling ofor group ofreferred to apin, node, othere, to mi

NOTERefer(VCLinform

PreconditioDISABLIN

© Agilent T 1-69

Chapter 1

ce list>list>

list>st>

list>

Preconditioningcify to disable or condition a node or a list

a node-oriented device. Preconditioning about each node is defined in the device's vice Node Preconditioning options are Table 1-30 on page 1-71.


: The Board File

Example 1-28 Disabling information syntax

condition nodes <node list> on <node library> for <devicondition pins <pin list> on <pin library> for <devicecondition device <library> for <device list>disable nodes <node list> on <node library> for <devicedisable pins <pin list> on <pin library> for <device lidisable device <library> for <device list>set <node-id> to <state> for <device list>set <node-id> to <state> family <family-id> for <device

The order of the statements specifies the order in which the operations are done. For example, refer to the ordering of the following statements:

disable device U1 for U3disable device U2 for U3disable device U4 for U3

Disabling will occur for U1 first, followed by U2, and finally disabling U4, for testing device U3.

If you are adding a DISABLING INFORMATION block, it must be located as the last block in the board file, before the END statement. The DISABLING INFORMATION block uses the previous definitions listed in the DEVICES, NODES, and CONNECTIONS blocks.

Each of these preconditioning statements is described in the following sections.

Device NodeYou can speof nodes ofinformationtest. The Dedescribed in

© Agilent T 1-70

Chapter 1

list>st>

nts>


: The Board File

Example 1-29 Device node preconditioning syntax

condition nodes <node list> on <node library> for <devicedisable nodes <node list> on <node library> for <device li

<node list> can be:<node-id><node-id>, <node-id><node-id>, <node-id>, . . . <node-id>

<device list> can be:ALL

ALL BUT <device>, <device>, . . . <device><device><device>, <device><device>, <device>, . . . <device>

<node-id>, <device>, and <node library> are <string consta

Examples:disable nodes lda on custom_devcondition nodes out1, out2, out3 on U1 for U2, U3disable nodes "out1" on "U1" for U5, U6

© Agilent T 1-71

Chapter 1

for the device under test.

oning for testing.

conditioning.

e will be preconditioned for the device under


: The Board File

Device Pin PreconditioningYou can specify to disable or condition a pin or a list of pins of a pin-oriented device. Preconditioning information about each pin is defined in the device's test. The Device Pin Preconditioning options are described in Table 1-31 on page 1-73.

Table 1-30 Device node preconditioning options

Option Description

<node-id> Node of a node library that will be preconditioned

<device> A digital device under test that requires preconditi

ALL All devices tested require preconditioning.

ALL BUT All devices tested, except those listed, require pre

<node library> Digital device defined as a node library. This devictest.

© Agilent T 1-72

Chapter 1

t>

s>


: The Board File

Example 1-30 Device pin preconditioning syntax

condition pins <pin list> on <pin library> for <device lisdisable pins <pin list> on <pin library> for <device list>

<pin list> can be:<pin-id>

<pin-id>, <pin-id><pin-id>, <pin-id>, . . . <pin-id>



<pin-id>, <device>, and <pin library> are <string constant

Examples:disable pins 1,9 on custom_devcondition pins 1,2,3 on U1 for U2, U3disable pins "1", "2" on "U1" for U5, U6

© Agilent T 1-73

Chapter 1

itioned for the device under test.

conditioning for testing.

conditioning.

brary. This device will be preconditioned for the


: The Board File

Board-Level Device PreconditioningYou can specify to disable or condition an entire device, located anywhere on the board, for the device under test. The preconditioning information is defined in the device's test. The Board-Level Device Preconditioning options are described in Table 1-32 on page 1-74.

Table 1-31 Device pin preconditioning options

Option Description

<pin-id> Specifies a pin of a pin library that will be precond

<device> This is a digital device under test that requires pre

ALL All devices tested require preconditioning.


<pin library> The digital device that has been defined as a pin lidevice under test.

© Agilent T 1-74

Chapter 1

l Preconditioning of Individual Nodes a specific node, located anywhere on the pecified state for the device under test. The l Preconditioning of Individual Nodes described in Table 1-33 on page 1-75.

Board-level device preconditioning options

Description

Device under test requires preconditioning for testing.

All devices tested require preconditioning.

All devices tested, except those listed, require preconditioning.

Digital device that has been defined as either a pin library or a node library. This device will be preconditioned for the device under test.


: The Board File

Example 1-31 Board-level device preconditioning syntax

condition device <library> for <devicelist>

disable device <library> for <device list>



<device> and <library> are <string constants>

Examples:disable device U1 for U2, U3condition device U5 for U2disable device "U1" for "U2", "U3"

Board-LeveYou can setboard, to a sBoard-Leveoptions are

Table 1-32

Option

<device>

ALL

ALL BUT

<library>

© Agilent T 1-75

Chapter 1

st>

itioned for the device under test.

e state of the node.

ode.


: The Board File

Example 1-32 Board-level preconditioning of individual nodes syntax

set <node-id> to <state> for <device list>set <node-id> to <state> family <family-id> for <device li



<family-id> and <device> are <string constants>

<state> can be:1

0T

Examples:set "en_out" to "1" family TTL for U1, U2, U3set en_out to 0 for U4set "LGB" family CMOS to T for U5, U6

Table 1-33 Board-level preconditioning of individual nodes options

Option Description

<node-id> Specifies a node on the board that will be precond

<state> The state that the node will be set to. T toggles th

ALL All devices tested require preconditioning of the n

© Agilent T 1-76

Chapter 1

can Override turned on the global options d to list the board object file (board.o).

conditioning.

.

)


: The Board File

Boundary Scan ChainsThis section lists the boundary scan chains. To make this section appear in the board file, you need to have

Boundary Sand you nee

Example 1-33 BOUNDARY SCAN CHAINS syntax

BOUNDARY SCAN CHAINS<name of chain>

<tap signal list>DEVICES

<device list>;

<device list> can be:<device>

<device>, <device><device>, <device>, . . . <device>

Example:BOUNDARY SCAN CHAIN

u1_u4TDI C_TDITDO C_TDOTCK C_TCKTMS C_TMSDEVICES

u1, u2, u3, u4;


<family-id> Name of the logic family associated with the node

Table 1-33 Board-level preconditioning of individual nodes options (continued

Option Description

© Agilent T 1-77

Chapter 1


: The Board File

EndThe End keyword marks the end of the board file, the pin mapping table, and the device options. It has no parameters. If more commands follow the End keyword, they are ignored by the system.

© Agilent T 1-78

Chapter 1

Sampl


: The Board File

e Board File Example 1-34

HEADING"This is an example of a 3070 Family BCF syntax";

GLOBAL OPTIONSFixture Type EXPRESS;Fixture Size BANK2;Top Probes Allowed OFF;Heavy Probe Force 8;Light Probe Force 4;Mechanical Density Threshold 800;Vacuum Density Threshold 104;Autofile 2395;Test Strategy COMBINATIONAL;WireWrapping AUTO;Metric Units OFF;Common Lead Resistance 0.1;

!(ohms) from probe to component.Common Lead Inductance 1u;

!(Henries) from probe to component.Capacitance Compensation ON;IPG Digital Resistance Threshold 50;

!(ohms)Preconditioning Levels 2;Additional Board Voltage 20;Boundary Scan Overdrive OFF;Boundary Scan Disable ON;Boundary Scan Chain Override ON;

DEVICE OPTIONSTolerance Multiplier 5.0;Remote Sensing ON;Fuse Threshold 3.0;Diode Current 1m;Zener Current .5m;Adjust ACCURATE;Upstream Disable ON;Upstream Condition OFF;

ENDFAMILY OPTIONS

TTL

© Agilent T 1-79

Chapter 1

ignal";


: The Board File

Drive High3.5;Drive Low 0.2;Receive High 2.0;Receive Low 0.8;Edge Speed 100;Open Input Default X;Load NONE;

FIXED NODE OPTIONSgnd Family ttl is 0;vcc1 Family ttl is 1;gnd GROUND;vcc1 Supply 1 At 5 Volts, 0.5 Amps;

GPRELAY OPTIONSGP "U102-7", "gnd";

CONTROL; ACCESS;LIBRARY OPTIONS

custom_lib/standard/library/ttl/standard/library/cmos;

CARD OPTIONSTTL

CHANNEL; HYBRID;UNCONNECTED PIN NC;CAPACITOR

C101 2.2u 10 10 f "C101 failed";OVERRIDE Tolerance Multiplier 1.0;

C102 10u 10 10 f "C102 failed";OVERRIDE Tolerance Multiplier 1.0;

CONNECTORCONN101 NT "Ground connector";

DIODELED101 800m 300m "Monitors output pulses";

JUMPERJ101 Closed "Jumper 101 failed";

NODE LIBRARYpulse_width BT NS "Measure pulse width of the output s

PIN LIBRARYU101 PN"74ls02" "quad NOR gate";U102 PN"ne555" "P101 must be centered";

POTENTIOMETERP101 50k 10 10 "Clock Frequency Adjust";

RESISTORR101 10k 5 5 f "Time constant for one-shot";

© Agilent T 1-80

Chapter 1


: The Board File

R102 2.2k 5 5 f;R103 1k 5 5 f;

OVERRIDE Remote Sensing On;R104 10k 10 10 f "Reference for timer";

OVERRIDE Tolerance Multiplier 1.0;R105 47 5 5 f "Pull-up";

SWITCHS101 1 2 "Clock signal switch";

TRANSISTORQ101 100 40 n "2n4401";

NODESVCC1 "Main Power Bus";GND "Ground";

PIN_MAPCAPACITOR

P 1N 2;

DIODE1 A2 C;

POTENTIOMETER3 W;

TRANSISTOR1 E2 B3 C;

ENDCONNECTIONS

"c101-2"C101.2R101.2U101.5U101.6;

clock1S101.1U102.3;

gndC102.2CONN101.1CONN101.2CONN101.3CONN101.4CONN101.5

© Agilent T 1-81

Chapter 1


: The Board File

CONN101.6CONN101.7CONN101.8Q101.EU101.7U102.1;

input1S101.2U101.3;

"led101-c"J101.2LED101.C;

output1J101.1Q101.CR103.2;

"r102-2"Q101.BR102.2;

"r105-2"LED101.AR105.2;

"u101-1"C101.1U101.1;

"u101-4"R102.1U101.2U101.4;

"u102-2"C102.1P101.WU102.2U102.6;

"u102-7"P101.1R104.2U102.7;

vcc1R101.1R103.1R104.1R105.1

© Agilent T 1-82

Chapter 1


: The Board File

U101.14U102.4U102.8;

NCU101.8U101.9U101.10U101.11U101.12U101.13U102.5P101.2;

DEVICESC101

1."u101-1"2."c101-2";

C1021."u102-2"2.gnd;

CONN1011.gnd2.gnd3.gnd4.gnd5.gnd6.gnd7.gnd8.gnd;

LED101A."r105-2"C."led101-c";

J1011.output12."led101-c";

U1011."u101-1"2."u101-4"3.input14."u101-4"5."c101-2"6."c101-2"7.gnd8.NC

© Agilent T 1-83

Chapter 1


: The Board File

9.NC10.NC11.NC12.NC13.NC14.vcc1;

U1021.gnd2."u102-2"3.clock14.vcc15.NC6."u102-2"7."u102-7"8.vcc1;

P1011."u102-7"2.NCW."u102-2";

R1011.vcc12."c101-2";

R1021."u101-4"2."r102-2";

R1031.vcc12.output1;

R1041.vcc12."u102-7";

R1051.vcc12."r105-2";

S1011.clock12.input1;

Q101B."r102-2"C.output1E.gnd;

CRITICAL PINSs101.1

© Agilent T 1-84

Chapter 1


: The Board File

q101.C;DISABLING INFORMATION

SET "u101-1" TO 1 FOR ALL;SET "u101-4" TO 0 FAMILY TTL FOR u102;CONDITION PINS 2,4,5 ON u101 for ALL;DISABLE DEVICE u102 for u101;

BOUNDARY SCAN CHAINSu1_u4

TDI C_TDITDO C_TDOTCK C_TCKTMS C_TMSDEVICES

u1, u2, u3, u4;END

© Agilent T 2-1

In this


2222 The board_xy File

chapter... � Overview, 2-2

� What is a board_xy File?, 2-4

� Programs that Use the board_xy File, 2-7

� board_xy File Syntax, 2-9

� Sample board_xy File, 2-27


� Understand the structure and syntax of the board_xy file



© Agilent T 2-2

Chapter 2

Overv / Viewing the Data in the board_xy File

t edit board test files with shell editors such These editors do not update the file's header ation, such as the time-stamp, that Agilent

programs use. Instead, use the BT-BASIC to edit board test files.

the board_xy File from Board Consultant.

fy entry forms.

ile board_xy file by clicking on Final ile/Verify.

hapter 2, Agilent Board Consultant in Test opment Tools for more information on ying entry forms.


: The board_xy File

iew This chapter describes the structure and syntax of the board_xy file. This file contains X-Y data, such as device pin and probe locations, of the circuit board to be tested.

NOTEUsing the board_xy file in the test generation process and to customize your test fixture files is described in Chapter 3, Creating Board Information in Test & Fixture Development.

The Fixture Generation Software uses the X-Y data from the board_xy.o file to produce the fixture.o file.

The test generation (IPG) step of the test generation process uses the node and location specifications of the board_xy.o file.

NOTEOptional board_xy file statements are not described in this chapter. These statements are available with optional software packages such as the PanelTest option. For information about such statements, refer to the documentation in the optional package.

Modifying

NOTEDo noas vi. inform3070editor

1 Modify

a Modi

b CompComp

NOTESee CDevelmodif

© Agilent T 2-3

Chapter 2


: The board_xy File

2 Modify the board_xy File from IPG Test Consultant.

a Click Edit.

b Select View/Edit board_xy File.

IPG Test Consultant opens a BT-BASIC window and loads the board_xy file into the BT-BASIC workspace for you to edit.

3 Modify the board_xy File manually.

a Open a BT-BASIC window.

b msi to the board test directory.

c Generate a board_xy source file from the board_xy.o object file if the board_xy source file doesn�t exist. Type:

list object "board_xy.o" to "board_xy"

d Load the board_xy file. Type:load "board_xy"

e Edit the board_xy file.

f Save the board_xy file. Type:re-store "board_xy"

© Agilent T 2-4

Chapter 2

What iFile?

NATESS

NATESS

xy file may specify the data listed in Table


: The board_xy File

s a board_xy The board_xy file contains X-Y data of the circuit board to be tested. This data includes X-Y coordinates of the device pins, board outline, keepout areas, and tooling pin holes. X-Y locations of device.pins are listed in the OTHER section. X-Y locations that are associated with a node are listed in the NODE section. Also included in the board_xy file are probe type and location attributes. This data is in a special format used by the 3070 family of board test systems. You can use data from a CAD system, or from a digitize process. CamCAD translates X-Y location information into the format used by the 3070 Family, and stores that data in the <file>.brd and <file>.bxy files. You must then rename the <file>.brd and <file>.bxy files to board and board_xy, respectively.

NOTECamCAD is explained in Chapter 3, Creating Board Information in Test & Fixture Development.

The following outline of a board_xy file shows the keywords used in the file. Some of the keywords are optional.

SCALEUNITSINCLUDEPLACEMENT

OUTLINETOOLINGKEEPOUTNODE

ALTEREXTRA

OTHERALTEREXTRA

GROUPDEVICESEND

The board_2-1.

© Agilent T 2-5

Chapter 2

extents, of the board. The coordinates of the rclockwise direction starting at the lower left

nd Y offsets from the fixture origin to the board rotation of the board.

be placed due to something (such as a device pout areas are specified as coordinates of the

scribes the area. The coordinates of the points wise direction starting at the lower left corner.

probed by the fixture.

he guided probe.

probed by the fixture, and are not accessible e specified as NO_ACCESS.

ing (not allowed for the SimPlate fixture).

s, 100 mil probes will be used even if 50 mil is


: The board_xy File

Table 2-1 board_xy data

Data Description

Board OUTLINE The points that define the corners, at the maximumpoints can be listed in either a clockwise or countecorner.

TOOLING hole locations

A list of all tooling hole locations.

Board PLACEMENT The position of the board on the test fixture as X aorigin. The placement specification also includes a

KEEPOUT areas Areas where no personality pins or probes shouldon the board) blocking that area of the fixture. Keeoutside points (at least three) of a polygon that decan be listed in either a clockwise or counterclock

NO_PROBE nodes and locations

Nodes and locations that cannot, or should not, be

NO_MANUAL nodes and locations

Nodes and locations that are not accessible with t

NO_ACCESS nodes and locations

Nodes and locations that cannot, or should not, bewith the guided probe. EXTRA locations cannot b

LONG probes Nodes that require long probes for dual-stage test

50MIL probes Specifies a 50 mil probe. In the case of long probespecified.

© Agilent T 2-6

Chapter 2

s due to sensitive or high-speed f an Express Cassette fixture cannot be

u can specify multiple MANDATORY locations be wired to the same personality pins. If Probe se another of the alternates and issue a notice.

echanical conflict such as density or considerations. You can specify more than one e from these preferred locations first before

sed for probe locations but will be passed on to sidered for use in the future.

top side of the board under test. Nodes which be specified as CRITICAL.

rs are available. These locations are physically

nd bottom sides of the board under test.

r. Groups must be labeled MANDATORY.


: The board_xy File

CRITICAL nodes and locations

Nodes and locations that require short wire lengthmeasurements. Nodes probed from the top side ospecified as CRITICAL.

MANDATORY locations Forces the use of the location with this attribute. Yoon a node; all mandatory locations on a node will Select cannot use the mandatory location, it will u

PREFERRED locations This location should be used unless it causes a maccessibility. PREFERRED overrides all electrical location as PREFERRED. Probe Select will choosselecting an alternate location.

EXTRA locations Locations that are labeled as EXTRA will not be ufixture.o as alternates so that they can be con

TOP locations Probe locations that are only accessible from the are probed from the top side of the fixture cannot

UNRELIABLE locations Probe locations that should only be used if no otheunreliable.

BOTH locations Probe locations that are accessible from the top a

GROUP Groups of device.pins that are to be wired togethe

Table 2-1 board_xy data (continued)

Data Description

© Agilent T 2-7

Chapter 2

Prograthe bo

Y locations are not used for the SimPlate can use asterisks, **, in place of X-Y the board_xy file. See the syntax definition RNATES - (OTHER),

(OTHER), and GROUPS statements later in .

s listed in Table 2-2 create or use the nd board_xy.o files during the test and ration process.

he 3070 Family, and stores that data in the e <file>.brd and <file>.bxy files to

fixture using the board outline coordinates lacement in the board_xy file. If Board e it; otherwise, Board Placement will place the

oard information from board to determine the an influence the selection of probes and


: The board_xy File

ms that Use ard_xy File

The test and fixture generation process for the Agilent No-Wire Technology, XG-50, SimPlate Express, XG-50 Cassette, and the Express Cassette fixtures requires a board_xy file. You can optionally use a board_xy file to generate the fixture files and reports for the SimPlate fixture to specify nodes that cannot, or should not, be probed.

If you want to develop an edge connector only test or use Groups for special wiring, you must provide a board_xy file no matter which fixture you are using.

Because X-fixture, youlocations inof the ALTEEXTRAS -this chapter

The programboard_xy afixture gene

Table 2-2 Programs that use the board_xy file

Program Description

CamCAD Translates X-Y location information into the format used by t<file>.brd and <file>.bxy files. (You must rename thboard and board_xy, respectively.)

BOARD PLACEMENT

Determines the position (X-Y placement) of the board on thefrom the board_xy file. You can manually specify a board pPlacement finds a placement specified in board_xy it will usboard automatically.

PROBE SELECT

Uses location and probe information from board_xy, and bbest type of probe and probing location for each node. You clocations by editing the board_xy file.

© Agilent T 2-8

Chapter 2

s.

n copy to a plotter to verify the data in the


: The board_xy File

IPG Uses node accessibility information when writing device test

PLOT GENERATOR

Creates a file from the data in the board_xy file that you caboard_xy file.

Table 2-2 Programs that use the board_xy file (continued)

Program Description

© Agilent T 2-9

Chapter 2

boardSyntax

ify units as inches, and scale as 0.01. The UNITS values will be used when the

ile is compiled to convert all units to tenth board_xy.o file. If you don't specify any e of 1 will be used.

x:value>;= scale factor for the numericvalues read from the input file.

01;

keyword specifies the units of the X and Y . The SCALE and UNITS values will be the board_xy file is compiled to convert all h mils for the board_xy.o file. If you don't units, inches will be used.

x:unit>;

be:


: The board_xy File

_xy File This section describes the syntax of the board_xy file. The syntax of the board_xy file is not case sensitive and each line of information (not list headings) must end with a semicolon. Node and device.pin names cannot contain colons (:) or tildes (~). The board_xy syntax includes these keywords:

� SCALE� UNITS� INCLUDE� PLACEMENT� OUTLINE� TOOLING� KEEPOUT� NODE� ALTERNATES (NODE)� EXTRAS (NODE)� OTHER� ALTERNATES (OTHER)� EXTRAS (OTHER)� GROUP� DEVICES� END

ScaleThe SCALE keyword specifies a scale factor that the input coordinates will be multiplied by, to put them in the specified units. For example, if the input data is in hundredths of inches (500 = 5.00 inches), then you

would specSCALE andboard_xy fmils for thescale, a scal

Scale Syntascale <<value>

Example:scale .

UnitsThe UNITScoordinatesused when units to tentspecify any

Units SyntaUNITS <

<unit> can

inchesmilscmmm

© Agilent T 2-10

Chapter 2

Specifies the name of the file whose to be included in the board_xy file.

CEMENT keyword to instruct Board here to position the board on the fixture.

ore information, see Chapter 4, Generating and Fixture Files in Test & Fixture opment.

MENT keyword specifies the position of X and Y offsets from the fixture origin to

rigin. The PLACEMENT keyword also e rotation of the board. The placement n in the board_xy file must include all three X offset, Y offset, and rotation. The rotation rst, then the X and Y offsets. Placement described in Table 2-3.

nts>


: The board_xy File

Example:units inches;

IncludeThe INCLUDE keyword allows the contents of a specified file to be inserted at that point in the file. Include statements can be nested to any depth; this is useful for incorporating standard options and configurations into new board files. When the new file is stored, the information from the include file becomes part of the new file, and the link to the include file is lost. The include filename can be a relative or an absolute pathname. The filename must be enclosed in quotes.

Include Syntax:INCLUDE <filename>;

<filename> is a <string expression>

Example:INCLUDE "/board/std_options";

<filename>

contents are

PlacementUse the PLAPlacement w

NOTEFor mTestsDevel

The PLACEthe board asthe board ospecifies thspecificatioparameters is applied fioptions are

Example 2-1 PLACEMENT syntax

PLACEMENT <x_offset>, <y_offset> <rotation>;

<x_offset>, <y_offset>, and <rotation> are <numeric consta

Example:PLACEMENT 70362, -10198 90;

© Agilent T 2-11

Chapter 2

NE keyword specifies a series of points that orners, at the maximum extents, of the the bottom left corner of the board first; then ting the coordinates of the corners in either a r counterclockwise around the board.

need to list the origin again at the end; the tomatically completes the polygon. Circular es must be entered as polygons. Table 2-4 utline options.

OUTLINE syntax

d>, <y_coord>d>, <y_coord>d>, <y_coord>. , . . . .. , . . . .d>, <y_coord>;

& <y_coord> are <numeric constants>

00000, 00000, 120000000, 120000000, 110000110000;


: The board_xy File

Figure 2-1

OutlineThe OUTLIdefine the cboard. List continue lisclockwise o

You do not compiler auboard outlindescribes O

Example 2-2

OUTLINE<x_coor<x_coor<x_coor. . .. . .

<x_coor

<x_coord>

Example:OUTLINE

0,151560600,

Table 2-3 PLACEMENT options

Option Description

<x_offset> x_offset of the board origin with respect to the fixture origin.

<y_offset> y_offset of the board origin with respect to the fixture origin.

<rotation> Rotation of the board in degrees. The positive X axis is 0 degrees. See Figure 2-1.

© Agilent T 2-12

Chapter 2

NG keyword marks the beginning of a list of oles. This list is needed to avoid conflicts ality pins. Tooling options are described in

OUTLINE options

Description

x_coordinate of the outline point.

y_coordinate of the outline point.


: The board_xy File

Figure 2-2

ToolingThe TOOLIall tooling hwith personTable 2-5.

Example 2-3 TOOLING syntax

TOOLING<size> <x_coord>, <y_coord>;<size> <x_coord>, <y_coord>;<size> <x_coord>, <y_coord>;. . . . . . , . . . .. . . . . . , . . . .

<size> <x_coord>, <y_coord>;

<size>, <x_coord>, and <y_coord> are <numeric constants>

(0, 110000) (60000, 120000) (150000, 120000)

(60000, 110000)

(0, 0) (150000, 0)

Table 2-4

Option

<x_coord>

<y_coord>

© Agilent T 2-13

Chapter 2

t area. Keepout options are described in

2000 or 3750.

KEEPOUT options

Description

x_coordinate of the keepout point.

y_coordinate of the keepout point.

Designates a keepout area on the bottom probe plate. When no side is specified, bottom is the default.


: The board_xy File

Example:TOOLING

3750 2010,2000;3750 2000,13000;

KeepoutThe KEEPOUT keyword specifies a series of points that define a polygon (at least three non-collinear points) that describe an area of the board where no personality pins or probes can be placed. The points can be listed in either a clockwise or counterclockwise direction starting at any corner. The Fixture Generation Software reads this information from the board_xy file and places it in the fixture.o file. Each KEEPOUT keyword specifies

one keepouTable 2-6.

Table 2-5 TOOLING options

Option Description

<size> Diameter of the tooling pin hole. This value can be

<x_coord> x_coordinate of the tooling hole.

<y_coord> y_coordinate of the tooling hole.

Table 2-6

Option

<x_coord>

<y_coord>

BOTTOM

© Agilent T 2-14

Chapter 2

BOTH, 20000, 20000, 40000, 40000;

keyword identifies the node for which X-Y ons will be given as alternate locations to can specify some attributes of the node. The

ord marks the beginning of a list of all obe locations for that node which are

ith a node, but not with a device.pin. The s are described in Table 2-7.

NODE syntax

ode_id>ode_id> <attributes>

is a <string constant>

can be:>> <attribute>> <attribute> . . . <attribute>

e> can be:


: The board_xy File

Example 2-4 KEEPOUT syntax

KEEPOUT<x_coord>, <y_coord><x_coord>, <y_coord>. . . . , . . . .. . . . , . . . .

<x_coord>, <y_coord>;KEEPOUT <attribute>

<x_coord>, <y_coord><x_coord>, <y_coord>. . . . , . . . .. . . . , . . . .

<x_coord>, <y_coord>;

<attribute> can be:BOTTOMTOPBOTH<x_coord> & <y_coord> are <numeric

constants>

Example:KEEPOUT

20000400004000020000

NodeThe NODEprobe locatiprobe. You NODE keywalternate prassociated wNode option

Example 2-5

NODE <nNODE <n

<node-id>

<attributes><attribute<attribute<attribute<attributNO_PROBENO_MANUALNO_ACCESS

TOP Designates a keepout area on the top probe plate.

BOTH Designates a keepout area on both the top and bottom probe plates.

Table 2-6 KEEPOUT options (continued)

Option Description

© Agilent T 2-15

Chapter 2

(Node)NATES keyword, when used in conjunction keyword, declares possible probe locations ith that node, but not associated with a

Alternates options are described in Table 2-17.

This node requires a long probe for dual stage testing.

This node requires a short wire due to a sensitive or high speed measurement.

NODE options (continued)

Description


: The board_xy File

LONGCRITICAL

Example:NODE "HI-Z" NO_PROBENODE "NODE_A" NO_MANUALNODE "NODE_B" NO_ACCESSNODE "R1-2" CRITICALNODE "SW2-3" LONGNODE "SW3-4" CRITICAL LONGNODE "SW3-5" CRITICAL NO_MANUAL

Alternates -The ALTERwith NODEassociated wdevice.pin. 2-8 on page

Table 2-7 NODE options

Option Description

<node-id> Node name.

NO_PROBE Node should not, or cannot, be probed by the fixture even if the X-Y location information is available.

NO_MANUAL Node is not accessible with the guided probe.

NO_ACCESS Node should not, or cannot, be probed by the fixture, and is not accessible with the guided probe.

LONG

CRITICAL

Table 2-7

Option

© Agilent T 2-16

Chapter 2


: The board_xy File

Example 2-6 ALTERNATES syntax

ALTERNATES<alternate_info>;

. . .<alternate_info>;

<alternate_info> can be:<x_coord>, <y_coord>

<x_coord>, <y_coord> <options><x_coord> & <y_coord> are <numeric constants>

<options> can be:<side><size><status><side> <size><side> <status><size> <status><side> <size> <status>

<side> can be:TOPBOTH

<size> can be:50MIL

<status> can be:<probe access>NO_MANUAL<probe access> NO_MANUAL

<probe access> can be:

© Agilent T 2-17

Chapter 2

origin.

origin.

e board.

es of the board.

mil probe for that location. If the same location n if 50 mil is specified and a notice is issued.


: The board_xy File

NO_PROBENO_ACCESS

UNRELIABLEPREFERREDMANDATORYCRITICALEXTRA

Example:NODE Data0

ALTERNATES23400,56700 BOTH;34500,67800 MANDATORY;45600,78900 NO_PROBE;55600,78900 PREFERRED NO_MANUAL;65600,78900 NO_ACCESS;

Table 2-8 ALTERNATES options

Option Description

<x_coord> x_coordinate of the node with respect to the board

<y_coord> y_coordinate of the node with respect to the board

TOP Location is accessible only from the top side of th

BOTH Location is accessible from the top and bottom sid

50MIL Forces the use of a 50 mil probe instead of a 100 is specified as LONG, a 100 mil probe is used eve

NO_PROBE This location cannot, or should not, be probed.

NO_MANUAL Location is not accessible with the guided probe.

© Agilent T 2-18

Chapter 2

for future use. The Extras options are Table 2-9 on page 2-20.

ixture, and is not accessible with the guided

ions are available. These locations are

echanical conflict such as density or siderations. You can specify more than one m the preferred locations first. If a preferred other alternate location.

ou can specify multiple mandatory locations be wired to the same personality pins. You can t as mandatory. If Probe Select cannot use the cation and issue a notice.

r high-speed measurement.

d for probe locations but will be passed on to ered for use in the future.


: The board_xy File

Extras - (Node)The EXTRAS keyword, when used in conjunction with NODE keyword, declares extra probe locations associated with that node, but not associated with a device.pin. Extra locations are not used for probes, but are passed on to fixture.o as alternates to be

considered described in

NO_ACCESS Location should not, or cannot, be probed by the fprobe.

UNRELIABLE Location that should be used only if no other locatphysically unreliable.

PREFERRED This location should be used unless it causes a maccessibility; preferred overrides all electrical conlocation as preferred; Probe Select will choose frolocation cannot be used, Probe Select will use an

MANDATORY Forces the use of the location with this attribute. Yon a node; all mandatory locations on a node will force the use of a top side location by specifying imandatory location, it will use another alternate lo

CRITICAL Location requires a short wire due to a sensitive o

EXTRA Locations that are labeled as extra will not be usefixture.o as alternates so that they can be consid

Table 2-8 ALTERNATES options (continued)

Option Description

© Agilent T 2-19

Chapter 2


: The board_xy File

Example 2-7 EXTRAS syntax

EXTRAS<extra_info>;<extra_info>;

. . .<extra_info>;

<extra_info> can be: <x_coord>, <y_coord><x_coord>, <y_coord> <options>

<x_coord> & <y_coord> are <numeric constants>

<options> can be:<side><size><side> <size>NO_MANUAL


<size> can be: 50MIL

Example:NODE Data0

EXTRAS12300,45600;23400,56700 BOTH;34500,67800 TOP;45600,78900 50MIL;55600,78900 NO_MANUAL

© Agilent T 2-20

Chapter 2

ed with device.pins. The Alternates options d in Table 2-10 on page 2-22.

e board origin.

e board.

es of the board.



: The board_xy File

OtherThe OTHER keyword marks the beginning of a list of X-Y locations that are associated with a device.pin. The only items that can be included in this list are ALTERNATES and EXTRAS.

Other Syntax:OTHER

The OTHER keyword has no parameters.

Alternates - (Other)The ALTERNATES keyword, when used in conjunction with the OTHER keyword, marks the beginning of a list containing X-Y locations, and their accessibility, which

are associatare describe

Table 2-9 EXTRAS options

Option Description

<x_coord> <y_coord> X and Y coordinates of the node with respect to th

© Agilent T 2-21

Chapter 2

tions>


: The board_xy File


ALTERNATES<alternate_info>;

. . .<alternate_info>;

<alternate_info> can be:<x_coord>, <y_coord><x_coord>, <y_coord> <dev.pin><x_coord>, <y_coord> <options><x_coord>, <y_coord> <dev.pin> <op

<x_coord> and <y_coord> are <numeric constants><dev.pin> is a <string constant>

<options> can be:<side><size><status><side> <size><side> <status><size> <status><side> <size> <status><side> can be:TOPBOTH

<size> can be:50MIL

<status> can be:<probe access>NO_MANUAL<probe access> NO_MANUAL

<probe access> can be:

© Agilent T 2-22

Chapter 2

origin. For the SimPlate fixture you can specify oordinates.

.

e board.

e for that location. If the same location is l is specified and a notice is issued.

re.


: The board_xy File

NO_PROBENO_ACCESSUNRELIABLEPREFERREDMANDATORYCRITICALEXTRA

Example:OTHER

ALTERNATES10000, 20000 U101.1 NO_PROBE;10000, 21000;10000, 22000 U101.3 UNRELIABLE;10000, 23000 U101.4 NO_ACCESS;20000, 23000 U101.5 MANDATORY;

OTHERALTERNATES

7000, 9000 U5.1;** U6.1;


Option Description

<x_coord> <y_coord>

X andY coordinates of the node with respect to the boarda default location by using asterisks (**) for the X and Y c

TOP Location is accessible only from the top side of the board

BOTH Location is accessible from the top and bottom sides of th

50MIL Forces the use of a 50 mil probe instead of a 100 mil probspecified as LONG, a 100 mil probe is used even if 50 mi

NO_PROBE This location cannot, or should not, be probed by the fixtu

© Agilent T 2-23

Chapter 2

nd is not accessible with the guided probe.

vailable. These locations are physically

al conflict such as density or accessibility; can specify more than one location as cations first. If a preferred location cannot be

specify multiple MANDATORY locations on a ame personality pins. You can force the use of be Select cannot use the mandatory location, it

peed measurement.

probe locations but will be passed on to for use in the future.


: The board_xy File

Extras - (Other)The EXTRAS keyword, when used in conjunction with the OTHER keyword, marks the beginning of a list containing X-Y locations of extra device.pins and their accessibility. These locations will be passed on to fixture.o as alternates to be considered for probing locations in the future. The Extras options are described in Table 2-11 on page 2-25.

NO_ACCESS Location should not, or cannot, be probed by the fixture, a

UNRELIABLE Location that should be used only if no other location is aunreliable.

PREFERRED This location should be used unless it causes a mechanicPREFERRED overrides all electrical considerations. You PREFERRED; Probe Select will choose from preferred loused, Probe Select will use another alternate location.

MANDATORY Forces the use of the location with this attribute. You can node; all mandatory locations on a node are wired to the sa top side location by specifying it as MANDATORY. If Prouses another alternate location and issues a notice.

CRITICAL Location requires a short wire due to a sensitive or high-s

EXTRA Locations that are labeled as EXTRA will not be used for fixture.o as alternates so that they can be considered

Table 2-10 ALTERNATES options (continued)

Option Description

© Agilent T 2-24

Chapter 2


: The board_xy File

Example 2-9 EXTRAS syntax

EXTRAS<extra_info>;

. . .<extra_info>;

<extra_info> can be:<x_coord>, <y_coord><x_coord>, <y_coord> <options><x_coord>, <y_coord> <dev.pin><x_coord>, <y_coord> <dev.pin> <options><x_coord> & <y_coord> are <numeric constants><dev.pin> is a <string constant><options> can be:<side><size><side> <size>NO_MANUAL


<size> can be:50MIL

Examples:OTHER

EXTRAS10000, 20000 U101.1 TOP;10000, 21000;10000, 22000 U101.3 BOTH;10000, 23000 U101.4 NO_MANUAL;20000, 23000 U101.5 50MIL;

OTHEREXTRAS

4000, 5000 U7.1;** U8.1;

© Agilent T 2-25

Chapter 2

maximum separation for a COAX group is the maximum separation for a TWISTED inch. The Group options are described in

0 GROUP syntax

e type> MANDATORYn>, <dev.pin>;...n>, <dev.pin>;

can be:

e board origin. For the SimPlate fixture you can r the X and Y coordinates.

e board.

es of the board.



: The board_xy File

GroupThe GROUP keyword marks the beginning of a list, or lists, of device.pins that are to be wired in matched pairs. The GROUP keyword also specifies the type of wiring to be used. Device.pins of a group are separated by a comma (,). Groups are separated by a semicolon (;). Because the GROUP keyword specifies the type of wire to be used, only groups of the type specified can be listed under that keyword.

Groups must consist of two device.pins that are located on the bottom of the board. The board_xy compiler will determine if the distance between the device.pins specified in a group is too great for the wire type of that

group. The 0.5 inches; group is 1.0Table 2-12.

Example 2-1

GROUP <wir<dev.pi

<dev.pi

<wire type>

Table 2-11 EXTRAS options

Option Description

<x_coord> <y_coord> X and Y coordinates of the node with respect to thspecify a default location by using asterisks (**) fo

© Agilent T 2-26

Chapter 2

; top side devices are not listed. This is for for Board Graphics.

ESbottom;

0 bottom;

eyword marks the end of the board_xy file.

:


: The board_xy File

TWISTEDCOAX

<dev.pin> is a <string constant>

Examples:GROUP TWISTED MANDATORY

u1.1, u2.1;u2.2, u3.2;

GROUP COAX MANDATORYu1.4, u2.4;

DevicesThe DEVICES keyword marks the beginning of a list of devices that were designated as being on the bottom side

of the boardTestJet and

Example:DEVIC

u3u2

EndThe END k

End SyntaxENDTable 2-12 GROUP options

Option Description

TWISTED The grouped locations be wired with a twisted-pair cable.

COAX The grouped locations be wired with a coaxial cable.

© Agilent T 2-27

Chapter 2

SamplFile TES

, 20000 U101.1 NO_PROBE;, 21000 U101.2 MANDATORY;, 22000 U101.3 UNRELIABLE;, 23000 U101.4 NO_ACCESS;, 24000 U101.5 MANDATORY;, 25000 U101.6 MANDATORY;, 26000 U101.7 MANDATORY;, 27000 U101.8 MANDATORY;, 27000 U101.9 MANDATORY;, 26000 U101.10 MANDATORY;, 25000 U101.11;

12300 Y1.1 TOP;12500 U102.1 NO_MANUAL;13500 U102.2 BOTH;14500 U102.3 50MIL;TED MANDATORYU101.5;U101.7;MANDATORYU101.10;

tom;tom;tom;


: The board_xy File

e board_xy Listed below is a sample board_xy file:OUTLINE

0, 0150000, 0150000, 12000060000, 12000060000, 1100000, 110000;

TOOLING3750 2000, 2000;3750 2000, 108000;

KEEPOUT20000, 2000040000, 2000040000, 4000020000, 40000;

NODE "HI-Z" NO_PROBENODE BIAS

ALTERNATES32500, 76900;

NODE ClockALTERNATES

10490, 24980;10490, 24980 TOP;

NODE Data0ALTERNATES

12300, 45600;23400, 56700 BOTH;34500, 67800 NO_PROBE;44500, 78900 NO_ACCESS;

EXTRAS45600, 78900;55600, 88900 NO_MANUAL;

OTHERALTERNA

1000010000100001000010000100001000010000200002000020000

EXTRAS95600,96600,96600,96600,

GROUP TWISU101.2,U101.6,

GROUP COAXU101.9,

DEVICESU10 botU11 botU12 bot

END

© Agilent T 3-1

In this

echnologies 2002, 2003 Data Formats 06/2003

3333 The Testorder File

chapter... � Introduction, 3-2

� Testorder Syntax, 3-4

� Sample Testorder File, 3-9


� Understand the structure and syntax of the testorder file


Required Tools and MaterialsThere are no required tools and materials associated with this chapter.

© Agilent T 3-2

Chapter 3

Introd t the testorder file also to influence test s shown in Table 3-1.

Test generation commands

Description

Instructs IPG which tests to not re-generate during incremental runs. IPG will not re-generate tests that are labeled with the permanent keyword.

Instructs TPG which tests to include in the testplan. The optional testplangeneration on/off statement also instructs TPG whether or not to generate a new testplan.

Provides a list of tests for which to schedule generation and compilation. IPG Test Consultant will not schedule generation or compilation for any tests not listed in the testorder file.

t

Provides a list of tests for which resources need to be assigned. MPA will not assign resources to any tests not listed in the testorder file.

echnologies 2002, 2003 Data Formats

: The Testorder File

uction The testorder file contains a list of all tests that are a part of this board. The entry for each test includes the type of test (resistor, digital, mixed...), the name of the test, and optional test attributes such as permanent, nulltest, and power.

The testorder file is an output of IPG. You can, however, manually create or edit this file.

The testorder file is an input to: IPG, IPG Test Consultant, Testplan Generator (TPG), and Module Pin Assignment (MPA).

The tests in each category (analog in-circuit, digital...) will be executed in the order in which they are listed in the testorder file. However, the different categories of tests may be listed in different orders depending on how the file was generated.

You can edit the testorder file prior to generating the testplan to force a testing order. For instance, if the test for R1 would charge a capacitor which would cause the test for R2 to fail, you can force R2 to be tested prior to R1. To do this, edit the testorder file to list resistor R2 before resistor R1.

You can edigeneration a

Table 3-1

Command

IPG

Testplan Generator (TPG)

IPG Test Consultant

Module PinAssignmen(MPA)

© Agilent T 3-3

Chapter 3

he testorder file.

r describes the syntax of the testorder file n example file at the end.

nal testorder file statements (available with al software packages such as the PanelTest

n) are not described in this chapter. For ation about such statements, refer to the entation in the optional package.



Modifying/Viewing the Data in the testorder File

NOTEDo not edit board test files with shell editors such as vi. These editors do not update the file's header information, such as the time-stamp, that Agilent 3070 programs use. Instead, use the BT-BASIC editor to edit board test files.

1 Modify the testorder file from IPG Test Consultant.

a Click the left mouse button on Edit.

b Drag the mouse pointer to select View/Edit testorder File.

IPG Test Consultant opens a BT-BASIC window and loads the testorder file into the BT-BASIC workspace for you to edit.

2 Modify the testorder File manually.

a Open a BT-BASIC window.


c Load the testorder file. Type:get "testorder"

d Edit t

This chapteand shows a

NOTEOptiooptionOptioinformdocum

© Agilent T 3-4

Chapter 3

Testo t Listment list> statement consists of one ll test types. The Statement List options are Table 3-1 on page 3-2.

stalled on your system to use this statement.



rder Syntax The syntax of the testorder consists of two statements; the <statement list> statement, and the testplan generation on/off statement.

NOTEMultiple Board Versions adds skip statements and version parameters to the testorder file to control the testing of devices on the versions of a PC board. These statements and parameters are not included in this chapter; see Chapter 5, Multiple Board Versions in Optional Board Test Applications for details.

StatemenThe <statesyntax for adescribed in

Example 3-1 <statement list> syntax

<statement list>

<statement list> can be:<pins test statement><shorts test statement><analog test statement><digital test statement><boundary-scan test statement> ! InterconnectPlus must be in<functional test statement><analog powered test statement><mixed test statement><testjet test statement><polarity check test statement><connect check test statement>

© Agilent T 3-5

Chapter 3



<pins test statement> can be:test pins <test name>test pins <test name>; <options>

<shorts test statement> can be:test shorts <test name>test shorts <test name>; <options>

<analog test statement> can be:test capacitor <test name>test capacitor <test name>; <options>test diode <test name>test diode <test name>; <options>test fet <test name>test fet <test name>; <options>test fuse <test name>test fuse <test name>; <options>test inductor <test name>test inductor <test name>; <options>test jumper <test name>test jumper <test name>; <options>test potentiometer <test name>test potentiometer <test name>; <options>test resistor <test name>test resistor <test name>; <options>test switch <test name>test switch <test name>; <options>test transistor <test name>test transistor <test name>; <options>test zener <test name>test zener <test name>; <options>

<digital test statement> can be:test digital <test name>test digital <test name>; <options>

<boundary-scan test statement> can be:test scan connect <test name>

© Agilent T 3-6

Chapter 3



test scan connect <test name>; <options>test scan interconnect <test name>test scan interconnect <test name>; <options>test scan disable <test name>test scan disable <test name>; <options>test scan powered shorts <test name>test scan powered shorts <test name>; <options>

test scanworks memory access verify <test name>

<functional test statement> can be:test functional <test name>test functional <test name>; <options>

<analog powered test statement> can be:test analog powered <test name>test analog powered <test name>; <options>

<mixed test statement> can be:test mixed <test name>test mixed <test name>; <options>

<testjet test statement> can be:test testjet <test name>

<polarity check test statement> can be:test polarity <test name>

<connect check test statement> can be:test connect check <test name><test name> is a <string literal>

<options> can be:<option><option>, <option><option>, <option>, . . ., <option>

© Agilent T 3-7

Chapter 3



<option> can be:preshortspowerpermanentcharacterizecommentnulltestnobacktrace<mixed option><path name>

<mixed option> can be:digital, analog

digital, serialdigital, analog, serial

<path name> is a <string literal>

<text> can be:<string literal>

Examples:test jumper "j1"; preshortstest shorts "shorts"test capacitor "c1"; characterizetest capacitor "c2"; characterize, permanenttest resistor "r2"test resistor "r3"; commenttest analog functional "vr1"; powertest digital "u1"; nulltesttest digital "u2"test connect "u3"; permanenttest functional "u100"test functional "u101"; nobacktracetest analog functional "op_amp"; "special_directory"

© Agilent T 3-8

Chapter 3

pacitor "c2"; characterizeorts "shorts"ns "pins"



test mixed "d_to_a"; permanenttest mixed "u10"; digital, analog, serial, commenttest mixed "u11"; digital, serial

Testplan Generation On/OffYou can use the testplan generation on/off statement in the testorder file to instruct TPG whether or not to generate a testplan.

If you have made changes to your testplan and are running TPG incrementally, you might not want TPG to overwrite your testplan. Use the testplangeneration off statement to instruct TPG to not generate a new testplan.

If no testplan generation on/off statement is specified in the testorder file, the system assumes testplan generation on.

Example 3-2 testplan syntax

testplan generation ontestplan generation off

Example:testplan generation offtest mixed "d_to_a"; permanenttest analog functional "vr2"test analog functional "op_amp"; permanent

.

.

.test capacitor "c1"

test catest shtest pi

© Agilent T 3-9

Chapter 3

SamplFile



e Testorder Example 3-3 testorder file

testplan generation ontest mixed "d_to_a"; permanenttest mixed "ser_u5"; digital, serialtest scan interconnect "b_scan"test analog powered "op2"test analog powered "op_amp"; permanenttest functional "filter"test functional "u101"; nobacktracetest digital "u1"test digital "u2"test digital "u3"; nulltesttest analog powered "vr2"; powertest zener "vr1"test transistor "q1"test switch "sw1"; preshortstest resistor "r1"test resistor "r2"test resistor "r3"; commenttest potentiometer "rpot1"; preshortstest jumper "j1"; preshortstest inductor "l1"test fet "qf4test diode "cr1"test capacitor ".discharge"test capacitor "c1"test capacitor "c2"; characterizetest shorts "shorts"test pins "pins"

© Agilent T 4-1

In this


4444 The Wirelist FileThe Wirelist FileThe Wirelist FileThe Wirelist File

chapter... � Overview, 4-2� The Wirelist Syntax, 4-4� Sample Wirelist File, 4-24


� Understand the structure and syntax of the wirelist file



© Agilent T 4-2

Chapter 4

Overv e Data in the wirelist File

t edit board test files with editors such as vi. editors do not update the file's header ation, such as the time-stamp, that Agilent

programs use. Use the BT-BASIC editor to oard test files.

wirelist File from IPG Test Consultant the left mouse button on Edit.

the mouse pointer to select View/Edit wirelist

est Consultant opens a BT-BASIC window ads the wirelist file into the BT-BASIC pace.

wirelist File Manually a BT-BASIC window.

the board test directory.

rate a wirelist source file from the ist.o object file if the wirelist source esn�t exist. Type:st object "wirelist.o" to "wirelist"


: The Wirelist File

iew The wirelist.o file contains the fixture wire connections from nodes to the module interface pins. This file is an output of Module Pin Assignment (MPA) and is stored under the local board directory.

During fixture generation, MPA assigns nodes to module interface pins. These assignments are stored in the wirelist.o file. These assignments are listed as wires from the nodes to the brc location of the interface pins. Each listing includes the type of resource for the interface pin.

The wirelist.o file is structured in blocks. There is one wirelist test block for each test in the testorder file. Each block contains the wire assignments used for that test.

The fixture generation process creates only the object file, wirelist.o; it does not generate a source file. However, you can create a source file, wirelist, from the object file.

Viewing th

NOTEDo noTheseinform3070edit b

Viewing thea Click

b Drag File.

IPG Tand loworks

Viewing thea Open

b msi to

c Genewirel

file doli

© Agilent T 4-3

Chapter 4


: The Wirelist File

d Load the wirelist file. Type:get "wirelist"

If a wirelist source file already exists in the local board directory, MPA will update both the source and object files.

The syntax of the wirelist is explained in this chapter, and an example wirelist is provided at the end.

NOTEMPA is explained in Chapter 4, Generating Tests and Fixture Files in Test & Fixture Development.

© Agilent T 4-4

Chapter 4

The Wl

rouppingtrappingmodule

drounddnusedfacenterfacelus module

statement marks the beginning of a wirelist . There can be only one global block in a

ile; the global block is listed prior to any test

obal statement terminates the global block. nition of the end global statement in this


: The Wirelist File

irelist Syntax This section describes the syntax of the wirelist file.

ADVICEWe recommend you do not edit the wirelist file.

The multiplexing done by MPA in allocating resources for a test is relatively complex. Manually editing this file could cause problems later on in the board development process. If a modification is required on the board, use Fixture Consultant to make the changes, modify the specific test, or modify the information in Board Consultant. Then use IPG Test Consultant to update the board and fixture information. Let the software manage the system's resources.

The keywords used in the wirelist syntax are:� global� end global� relay� end relay� test� end test� device� end device� clock� timing module� functional� include� subtest� end subtest

� wire� seria� group� end g� strap� end s� asru� tie� groun� end g� unuse� end u� inter� end i� stimu

globalThe globalglobal blockwirelist fblocks.

The end gl

See the defichapter.

© Agilent T 4-5

Chapter 4

block lists brcs that will be switched to e beginning of powered test. These brcs are e second row on a hybrid double density pin

occupy the same locations as the extended located on the 20 MP/s hybrid high rd. Physically the switched ground brcs are mbered pins below pin 39 and the odd ins above pin 39. Only ground resource owed. Typically the ground block is used for tability. The ground block can only appear l section.

ground syntax

dre "GND" to 101102 groundre "GND" to 101104 groundre "GND" to 223177 groundre "GND" to 223175 groundroundbal

dound statement marks the end of a ground he ground statement in this chapter.


: The Wirelist File

Example 4-1 global syntax

global

Example:global

relaywire "R1-2" to 11818 generalwire "BB6-8" to 11819 general

end relayend global

end globalThe end global statement terminates a wirelist global block. The global statement marks the beginning of the global block. See the definition of the global statement in this chapter.

Example 4-2 end global syntax

end global

Example:global

relaywire "Node_1" to 11818 generalwire "Node_2" to 11819 general

end relayend global

groundThe groundground at thlocated in thcard. They ground pinsaccuracy cathe even nunumbered ptypes are allfixture adapin the globa

Example 4-3

ground

Example:global

grounwiwiwiwi

end gend glo

end grounThe end gr

block. See t

© Agilent T 4-6

Chapter 4

lay statement terminates the relay block. nition of the end relay statement in this

end relay syntax

re "Node_1" to 11818 generalre "Node_2" to 11819 generalelaybal


: The Wirelist File

relayThe relay statement marks the beginning of a wirelist relay block. A relay block contains wire statements for GP relay connections.

The end re

See the defichapter.

Example 4-4 relay syntax

relay

Example:global

relaywire "R1-2" to 11818 generalwire "BB6-8" to 11819 general

end relayrelay

wire "Node_3" to 10152 general using accesswire "Node_2" to 10151 general using access

end relayend global

end relayThe end relay statement terminates a wirelist relay block. The relay statement marks the beginning of the relay block. See the definition of the relay statement in this chapter.

Example 4-5

end relay

Example:global

relaywiwi

end rend glo

© Agilent T 4-7

Chapter 4

tie syntax

to <brc>

s a <numeric constant>n integer that identifies thebank-row-column position of amodule interface pin.

ng0442 to 10414206122 to 10622apping

ingrapping statement terminates a strapping

end strapping syntax

ing

pinge 10201 to 102101e 10217 to 102117trappingbal


: The Wirelist File

strappingThe strapping statement begins a block of information that describes externally hardwired connections between brc pins. The external connections are made either in the fixture or fixture adapter. Only one strapping block is allowed in the wirelist file and it must appear in the global section.

Example 4-6 strapping syntax

strapping

Example:global

strappingtie 10101 to 101101tie 10201 to 102101

end strappingend global

tieThe tie statement describes a hardwired connection between two brcs in the fixture or fixture adapter. Typically, tie connections are used to describe non-standard paths to card resources. Only brcs of double-density pin cards can be used and any of these brcs can only be specified once in a strapping block.

Example 4-7

tie <brc>

<brc> i<brc> A

Example:strappi

tie 1tie 1

end str

end strappThe end st

block.

Example 4-8

end strapp

Example:global

straptiti

end send glo

© Agilent T 4-8

Chapter 4

unused syntax

dre "U15_1" to 10102 nonere "VER_3" to 10104 nonenusedbal

dused statement terminates an unused wire he unused statement for more information.

atement marks the beginning of a wirelist d specifies the test type. It also specifies the

f there is one.

pe is specified, digital is assumed. The endent terminates the test block. See the

f the end test statement in this chapter. The are described in Table 4-1 on page 4-10.


: The Wirelist File

unusedThe unused statement begins an unused wiring block and ends with an end unused statement. Only one unused wiring block can exist in the wirelist and it must appear in the global section.

Probe Select, MPA, and other board compilers store wiring information here about wires that continue to exist in the fixture, but are not currently being used by any test in the wirelist. If the fixture is modified at a later time, such as for an Engineering Change Order (ECO), the fixture generation software tries reassigning personality pins and wires listed here before requesting a new personality pin be drilled. This process minimizes the need to redrill the fixture to add new personality pins or wires if resources already exist in the unused section.

CAUTION

✸Do not add or modify any information listed in the unused section. Because the fixture generation software modifies this section for its own use, any user modification could potentially get deleted or invalidate the fixture.

Note that wire statements in the unused block use the resource type none. This parameter specifies that no resource is assigned to the wire. All wires in the unused block must use this resource type.

Example 4-9

unused

Example:global

unusewiwi

end uend glo

end unuseThe end un

block. See t

testThe test sttest block antest name, i

If no test tytest statemdefinition oTest options

© Agilent T 4-9

Chapter 4


: The Wirelist File

Example 4-10 test syntax

test <test name>test <test name> <version label>test <test type> <test name>test <test type> <test name> <version label>test mixed <test name>; <mixed option>test mixed <test name>; <mixed option> <version label>

<test type> can be:digitalanalogmixedshortstestjetpolarityconnectcheck

<test name> is a string constant

<mixed option> can be:digital, analogdigital, serialdigital, analog, serial

Example:test analog "central_analog_components"

wire "R1-2" to 11422 iwire "R1-2" to 11431 bwire "BB6-8" to 11442 gwire "BB6-10" to 11451 l

end test

© Agilent T 4-10

Chapter 4

statement marks the beginning of a device a wirelist test block. The device statement

e device designator and mux card address. rd address includes: the side of the fixture, s, and port number. The end device rminates the device block. See the definition evice statement in this chapter. The Device

described in Table 4-2 on page 4-11.

option is specified, digital, analog is the


: The Wirelist File

The end test statement terminates a wirelist test block. The test statement marks the beginning of the test block. See the definition of the test statement in this chapter.

Example 4-11 end test syntax

end test


wire "R1-2" to 11422 iwire "R1-2" to 11431 bwire "BB6-8" to 11442 gwire "BB6-10" to 11451 l

end test

deviceThe deviceblock withinspecifies thThe mux camux addresstatement teof the end d

options are

Table 4-1 test options

Option Description

<test type> Type of test (digital, analog, mixed, shorts, testjet test. . .)

<test name> Test name.

<mixed option> In a mixed test, specifies the type of resources used. If nodefault.

<version label> Version for Multiple Board Versions.

© Agilent T 4-11

Chapter 4

rt <port number>

vice statement terminates a device block elist test block. The device statement marks

umber> Address of the mux card.

Number of the port on the mux card.

device options (continued)

Description


: The Wirelist File

Example 4-12 device syntax

device <device designator>; <side> mux <address number> po

<device designator> is a string expression

<side> can be:topbottom

<address number> is: <integer from 1 to 15>

<port number> is: <integer from 1 to 64>

Example:device "u150"; top mux 2 port 5

wire "gnd" to 22365 gwire "u150-1" to 22321 gwire "u150-2" to 22322 g

. . .end device

end deviceThe end de

within a wir

Table 4-2 device options

Option Description

<device designator>

Device under test.

<side> Side of the fixture�top or bottom.

<address n

<port>

Table 4-2

Option

© Agilent T 4-12

Chapter 4

be:ll

gital "U101"ionalmodule 0ock internal"U101-4" to 20221 drive

.

.

.t

leodule statement specifies which module master asru card used for the test. It allows

gnals to be routed between the master asru pin cards of any module. asru module can d with ASRU revision C cards and is valid

clock options

Description

Clock is generated internally.

Clock is generated externally.


: The Wirelist File

the beginning of the device block. See the definition of the device statement in this chapter.

Example 4-13 end device syntax

end device

Example:device "u150"; top mux 2 port 5

wire "gnd" to 22365 gwire "u150-1" to 22321 gwire "u150-2" to 22322 g

. . .end device

clockThe clock statement describes the type of clock used for a test. The clock statement is only valid within a wirelist test block. If no clock statement is present in the wirelist test block, it is assumed that no clock is needed. This statement is required for the digital, digital functional, and mixed test types. The clock statement must follow the functional and test statement, and precede any wire or subtest statements. The Clock options are described in Table 4-3 on page 4-12.

Example 4-14 clock syntax

clock <type>

<type> can internaexterna

Example:test di

functtiming

clwire

end tes

asru moduThe asru m

contains theSIGLAB siand hybrid only be use

Table 4-3

Option

<internal>

<external>

© Agilent T 4-13

Chapter 4

6 timing module syntax

ule <module number>

mber> is an <integer from 0 to 3>

gital "ram test"ionalg module 3internal

"D0" to 21441 drive"D0" to 21441 receive..."D3" to 21470 drive"D3" to 21470 receivet

oduleus module statement specifies the pin card

to ground for each module. It is only valid ectcheck test type.

odule statements must follow functional atements, and precede wire statements. The described in Table 4-4 on page 4-15.


: The Wirelist File

only for analog, analog functional, and mixed tests. The statement must follow any functional and test statements, and precede any wire or subtest statements.

<module number> represents the module that contains the master asru cards.

Example 4-15 asru module syntax

asru module <module number>

<module number> is: <integer from 0 to 3>

Example:test analog "r1"

asru module 1wire "r1.1" to 10968 swire "r1.2" to 11367 i

end test

timing moduleThe timing module statement specifies which module is the master timing module for the test. This statement is only valid for digital, digital functional, and mixed test types. The timing module statement must follow any functional and test statements, and precede any wire or subtest statements.

<module number> represents the module that provides the master timing for the test.

Example 4-1

timing mod

<module nu

Example:test di

functtiminclockwirewire

wirewire

end tes

stimulus mThe stimulto be wiredfor the conn

Stimulus m

and test stoptions are

© Agilent T 4-14

Chapter 4

d, in each module,


: The Wirelist File

Example 4-17 stimulus module syntax

stimulus module <module number> card <slot number><module number> is an <integer from 0 to 3><slot number> is an <integer>

Example:test connectcheck "connectcheck"

timing module 2bottom mux 1stimulus module 0 card 5! Which card to wire to grounstimulus module 1 card 3! for Connect Check tests.wire "+5V" to 22362 ccguardwire "+5V" to 22364 ccguardwire "+5V" to 22366 ccguardwire "+5V" to 22368 ccguardwire "ground" to 22370 ccgroundwire "ground" to 22372 ccgroundwire "ground" to 22374 ccgroundwire "ground" to 22376 ccgroundwire "ground" to 22378 ccgrounddevice "u101"

wire "~ccmux" to 20278 ccrefnodewire "ground" to 20262 ccrefretwire "node_1" to 21631 gwire "node_2" to 21645 g

.

.

.end device

end test

© Agilent T 4-15

Chapter 4

“clock” to 21937 receive frequencyt

e statement is used in the wirelist file to other file. The statement instructs the

read the code from that other file and treat it a part of the original file. The object code luded file is merged in the object code of the .

is the identifier of the wirelist file to be

9 include syntax

ile id>

is a string constant

de "wirelist/test_U100"

t statement marks the beginning, and e name, of a subtest within a wirelist test subtest name must not exceed 16 characters. t statement is only valid with analog, analog and mixed functional test types. This


: The Wirelist File

functionalThe functional statement modifies the test type, which is specified by the test statement, in a wirelist test block. The functional statement specifies analog functional, digital functional, or mixed functional test types. Note that the functional statement is optional for analog and digital test types, but is always required for mixed tests. The functional statement must follow the test statement, and precede any wire, clock, timing module, or subtest statements.

Example 4-18 functional syntax

functional

Example:test analog "y301"

functionalwire “gnd” to 21661 detector

wireend tes

includeThe includreference ancompiler toas if it werefrom the incoriginal file

<file id>

included.

Example 4-1

include <f

<file id>

Example:inclu

subtestThe subtesspecifies thblock. The The subtesfunctional,

Table 4-4 stimulus module options

Option Description

<module number> Module used for the Connect Check test.

<slot number> Slot number of the card to be wired to ground the Connect Check test.

© Agilent T 4-16

Chapter 4

f the subtest. See the definition of the tement in this chapter.

1 end subtest syntax

test

analog "central_analog_components"re "R1-2" to 11422 ire "R1-2" to 11431 bre "BB6-8" to 11442 gre "BB6-10" to 11451 lbtest "card 0"wire "BB6-3" to 11976 awire "BB6-3" to 11918 sd subtestbtest "card 1"wire "BB6-4" to 11976 awire "BB6-4" to 11917 sd subtestest

atement describes a wire for a test or subtest. tatement identifies a node and a brc that are

her. It also indicates the resource type used. is specified within a wirelist test block is t test and all subtests. A wire that is specified test is only used for that subtest. The

source is allowed only inside a block y the relay and end relay statements.


: The Wirelist File

statement can only be used within a wirelist test block, and must be terminated by the end subtest statement. The end subtest statement terminates the subtest. See the syntax description of the end subtest statement in this chapter.

Example 4-20 subtest syntax

subtest <subtest name>

<subtest name> is a string constant


wire "R1-2" to 11422 iwire "R1-2" to 11431 bwire "BB6-8" to 11442 gwire "BB6-10" to 11451 lsubtest "card 0"

wire "BB6-3" to 11976 awire "BB6-3" to 11918 s

end subtestsubtest "card 1"


end subtestend test

end subtestThe end subtest statement terminates a subtest in a wirelist test block. The subtest statement marks the

beginning osubtest sta

Example 4-2

end sub

Example:test

wiwiwiwisu

ensu

enend t

wireThe wire stEach wire swired togetA wire thatused for thawithin a subgeneral redelimited b

© Agilent T 4-17

Chapter 4

al compiler of tests which use the Card, to instruct MPA to assign brc�s in the

ad module. See in module <x> (DIGITAL).

OT add in module <x> syntax to wire x. Program errors will result.


: The Wirelist File

Each <brc> can be connected to one of two X-bus paths on double-density pin cards if the resource type used is s, i, l, a, b, aux, detector high, detector low, or source. One path is called the primary X-bus, which typically is the path used. The other path is called the alternate X-bus, which can be used if the primary X-bus path is not available. Each primary X-bus has one alternate. The following list shows the primary X-bus and its corresponding alternate in the form (primary, alternate): (X1, X3), (X2, X4), (X3, X5), (X4, X6), (X5, X7), (X6, X8), (X7, X1), (X8, X2). Specifying alternate changes the signal path from using the primary X-bus to using its alternate X-bus.

Adding via <group brc> to <via brc> in the wiring statement specifies an extended path using an external connection in the fixture or fixture adapter between two brcs. Both brcs must previously be defined in a tie statement. The extended signal path is as follows: <node> to <brc>, <brc> to <group brc>, <group brc> to external connection, external connection to <via brc>, <via brc> to pin card resource. The <group brc> must be in the same channel as the <brc> to use this extended path. If alternate is specified when the statement contains via <group brc> to <via brc>, the alternate X-bus applies only to the <via brc>, not <brc>. The Wire options are described in Table 4-5 on page 4-20.

The in module <x> syntax is used by the On-Board Programming (OBP) software in conjunction with the ControlXTP card. The in module <x> syntax is added

by the digitControlXTPsame testhe

CAUTION

✸Do Nsynta

© Agilent T 4-18

Chapter 4

brc>brc> in module <x>brc> alternatebrc> alternate in module <x>

ype>brc> using <card type>brc> alternate using <card type>


: The Wirelist File

Example 4-22 wire syntax

wire <node> to <brc> <resource>wire <node> to <brc> <resource> in module <x>wire <node> to <brc> <resource> alternatewire <node> to <brc> <resource> alternate in module <x>wire <node> to <brc> <resource> via <group brc> to <viawire <node> to <brc> <resource> via <group brc> to <viawire <node> to <brc> <resource> via <group brc> to <viawire <node> to <brc> <resource> via <group brc> to <viawire <node> to <brc> <resource> using <card type>wire <node> to <brc> <resource> alternate using <card twire <node> to <brc> <resource> via <group brc> to <viawire <node> to <brc> <resource> via <group brc> to <via

<node> is a string constant

<brc>, <group brc>, and <via brc> are numeric constants

<resource> can be:sigll on xlabglauxdetector highdetector lowsourcedrivedrive on receive busdynamicnonereceivereceive on drive busreceive <class>receive <class> on drive busserial1

© Agilent T 4-19

Chapter 4

ode> ... in module <x> statement


: The Wirelist File

serial2serial3serial4serial5serial6serial7serial8serial9serial10serial11serial12serial clockserial clock receiveclockclock receiveclock receive frequencyfast clocktriggerext <ext#>acc <acc#> <connection>generalgroundccguardccgroundccrefnodeccrefret

<x> can be: letter from A to Z - always at the end of specified wire <n

<card type> can be:accessanalogchannelcontrolhybrid

<ext#> can be: 1, 2, 3, 4, 5, 6, 7, or 8

<acc#> is a numeric constant

<class> can be:

© Agilent T 4-20

Chapter 4

types.

pes.pes.

For Connect Check, ~ccmux specifies that the

nterface pin connected to a node.


: The Wirelist File

fixed ! For digital and digital functional testinternal ! For digital functional test types.frequency ! For mixed and analog functional test tyinterval ! For mixed and analog functional test ty

<connection> can be:highhigh directlowlow shieldlow directlow shield direct

Examples:test digital "X"

timing module 1clock externalwire "X1" to 20606 triggerwire "X3" to 11867 triggerwire "X0" to 11876 clock receivewire "X4" to 21816 fast clockwire "X0" to 21401 drivewire "X1" to 21410 drivewire "X3" to 21430 drivewire "X2" to 21421 receivewire "X3" to 21430 receive

end test

Table 4-5 wire options

Option Description

<node_name> The name of the node specified in the board file. wire needs to be connected to the mux card.

<brc> The bank-row-column designation of the module i

© Agilent T 4-21

Chapter 4

associated with serial test card resources. oup statement terminates the group block.

3 group syntax

group id>

> is a string constant

group brc> allows the signal to be routed to an d to another resource of the same card or

ction, which routes the signal path to a <group pin card.

est or global block. Some resources can be rd. Available only to the L resource is an cified by adding on xl after the l resource source can be routed through the receive bus. gh the drive bus. Typically these types of

ons.efret resources are for an Connect Check

with the same letter are placed by the MPA dule (0 or 1 or 2 or 3).


: The Wirelist File

Please refer to the sample wirelist file in Sample Wirelist File on page 4-24 for additional examples of wire statements.

groupThe group statement marks the beginning of a wirelist group block. A group block contains all connection

informationThe end gr

Example 4-2

group <

<group id

<group brc> A brc located in the same channel as <brc>. The <external connection in the fixture which is then tieanother double-density pin card.

<via brc> This brc connects a resource to an external connebrc> on the same card or another double-density

<resource> The type of resource the wire connects to for the tspecified to use a different bus with the on keywoalternate bus called the XL-bus, which can be spesyntax. In digital or mixed signal tests, the drive reSimilarly, the receive resource can be routed throuassignments are used for fixture adapter applicatiThe ccguard, ccground, ccrefnode, and ccrtest.

in module <x> <x> can have a value from A to Z. All wires (brc)(Module Pin Assignment program) in the same mo

Table 4-5 wire options (continued)

Option Description

© Agilent T 4-22

Chapter 4

5 serial syntax

clock<class> using <count>

be:

ubusttl<#>

<1-6>a <numeric constant>

ckBOARD_CLKDR" to 12209 serial clockBOARD_CLKRC" to 12202 serial clock

ace statement marks the beginning of the rface block. The interface block contains used for fixture interfaces; this includes a statements and a pairs/end pairs block.

ire statements define the node-to-brc wires. Each wire statement has a resource . The pairs/end pairs block contains tie or pairs of brc�s.


: The Wirelist File

Example:group "stream1"serial sbus using 2wire "GND" to 12216 serial1wire "/1MBINIT*" to 12221 serial2end group

end groupThe end group statement terminates a wirelist group block.

Example 4-24 end group syntax

end group

Example:group "stream1"serial sbus using 2wire "GND" to 12216 serial1wire "/1MBINIT*" to 12221 serial2end group

serialThe serial statement defines all of the serial stream attributes of a group block's associated wire statements. This statement can only be specified within a group block and must follow the group statement.

Example 4-2

serialserial

<class> cansbus

<#> can be<count> is

Example:groupserial clo

wire "/wire "/

receiveend group

interfaceThe interfwirelist inteinformationlist of wire

The list of wmapping oftype of nonestatements f

© Agilent T 4-23

Chapter 4

"Node_2" to 10201 none

e 10101 to 10222e 10102 to 10221erface


: The Wirelist File

Example 4-26 interface syntax

interfacewire <node name> to <brc> nonepairs

tie <brc> to <brc>end pairs

end interface

<node name> is a <string expression><brc> is a <numeric expression>

Example:interface"

wire "Node_1" to 10200 nonewire "Node_2" to 10201 nonepairs

tie 10101 to 10222tie 10102 to 10221

end interface

end interfaceThe end interface statement terminates the wirelist interface block.

Example 4-27 end interface syntax

end interface

Example:interface"

wire "Node_1" to 10200 none

wirepairs

titi

end int

© Agilent T 4-24

Chapter 4

Sampl


: The Wirelist File

e Wirelist File Example 4-28 Sample wirelist file

globalrelay

wire "R1-2" to 11818 generalwire "BB6-8" to 11819 general

end relayrelay

wire "Node_3" to 10152 general using accesswire "Node_2" to 10151 general using access

end relaystrapping

tie 21021 to 210121tie 21023 to 210123tie 21001 to 210101tie 21041 to 210141tie 21043 to 210143

end strappingend globaltest analog "r20"

wire "R20-1" to 101117 swire "R20-2" to 101116 iwire "U20-2" to 101118 gwire "R17-2" to 10118 l on xlwire "R20-1" to 10117 a alternatewire "R20-2" to 10116 b alternate

end testtest analog "r21"

wire "R21-1" to 21025 s via 21021 to 210121wire "R21-2" to 20923 i

end testtest analog "r19"

asru module 1wire "R19-1" to 11001 s

© Agilent T 4-25

Chapter 4


: The Wirelist File

wire "R19-2" to 11312 iend testtest "X"

timing module 1clock externalwire "X0" to 21401 drivewire "X0" to 11876 clock receivewire "X1" to 21410 drivewire "X1" to 11873 triggerwire "X2" to 21421 receive fixedwire "X3" to 21430 drivewire "X3" to 21430 receive fixedwire "X3" to 11867 triggerwire "X4" to 21816 fast clock

end testtest digital "ram_test"

functionaltiming module 3clock internalwire "D0" to 21441 drivewire "D0" to 21441 receivewire "D1" to 21450 drivewire "D1" to 21450 receivewire "D2" to 21461 drivewire "D2" to 21440 receivewire "D3" to 21470 drivewire "D3" to 21470 receivewire "DATA_STROBE" to 21471 receive fixed

end testtest digital "jbc1"

timing module 3clock internalwire "CLK" to 21522 drive in module Awire "CLK_DISABLE" to 21521 drivewire "IN" to 21503 drive in module Awire "MOD" to 21502 drive in module A

© Agilent T 4-26

Chapter 4


: The Wirelist File

wire "OUT" to 21501 receive in module Aend test

test analog "central_analog_components"wire "R1-2" to 11422 iwire "R1-2" to 11431 bwire "BB6-8" to 11442 gwire "BB6-10" to 11451 lwire "CH1_H" to 22277 acc18 high directwire "CH1_L" to 22278 acc18 low directwire "GND" to 22228 acc13 lowwire "CONTR" to 22227 acc 13 highsubtest "card 0"


end subtestsubtest "card 1"


end subtestend testtest analog "side_analog_components"

wire "R19-2" to 11512 gwire "R19-1" to 11501 glwire "R20-1" to 11521 swire "R20-1" to 11530 awire "R20-2" to 11541 iwire "R20-2" to 11550 b

end testtest digital "ttl_logic"

timing module 2clock externalwire "U1-1" to 20201 drivewire "U1-1" to 20602 clock receivewire "U1-2" to 20221 drivewire "U1-2" to 20606 triggerwire "U1-3" to 20206 drive

© Agilent T 4-27

Chapter 4


: The Wirelist File

wire "U1-3" to 20207 receivewire "U1-5" to 20222 drivewire "U1-5" to 20202 receive

end testtest mixed "mixed"

functionaltiming module 0clock internalwire "R2-1" to 22201 ext1wire "R2-2" to 22313 ext2wire "U2-1" to 22227 drivewire "U2-7" to 22238 receivewire "DAC-OUT" to 22249 receive frequency

end testtest analog "analog_section_1"

functionalwire "ANA_FUNC.1" to 21601 detector lowwire "ANA_FUNC.2" to 21610 detector highwire "ANA_FUNC.3" to 21621 auxwire "ANA_FUNC.4" to 21630 receive intervalwire "ANA_FUNC.5" to 21641 receive interval

end testtest shorts "shorts"

wire "U9-1" to 21650 gwire "U9-2" to 21661 g

end testtest mixed "serial_6an"; digital, serial

functionaltiming module 1clock internalwire "DTR0-" to 20968 drivewire "RTS0-" to 21067 drivewire "SOUT0" to 21068 drivegroup "stream1"serial sbus using 2

wire "GND" to 12216 serial1

© Agilent T 4-28

Chapter 4

e


: The Wirelist File

wire "/1MBINIT*" to 12221 serial2end groupgroup "stream2"serial ttl4 using 331

wire "GND" to 12264 serial1wire "/3MBINIT*" to 12268 serial2wire "/4MBINIT*" to 12275 serial2

end groupgroupserial clock

wire "/BOARD_CLKDR" to 12209 serial clockwire "/BOARD_CLKRC" to 12202 serial clock receiv

end groupend testtest testjet "testjet"

timing module 3device "u50"; top mux 1 port 1

wire "gnd" to 22365 gwire "u50-1" to 22321 gwire "u50-2" to 22322 gwire "u50-3" to 22323 gwire "u50-4" to 22324 gwire "u50-5" to 22361 gwire "u50-6" to 22362 gwire "u50-7" to 22363 gwire "u50-8" to 22364 g

end devicedevice "u100"; bottom mux 2 port 1

wire "gnd" to 22365 gwire "u100-1" to 22321 gwire "u100-2" to 22322 gwire "u100-3" to 22323 gwire "u100-4" to 22324 gwire "u100-5" to 22361 gwire "u100-6" to 22362 gwire "u100-7" to 22363 g

© Agilent T 4-29

Chapter 4

ire to ground, in each module,ck tests.s connected to a

s connected tod node.

x card.rd ground node.


: The Wirelist File

wire "u100-8" to 22364 gend device

end testtest polarity "polarity"

timing module 1device "c1"; top mux 1 port 1

wire "node_1" to 22321 swire "node_1" to 22322 awire "node_2" to 22365 iwire "node_2" to 22366 b

end devicedevice "c2"; bottom mux 2 port 1

wire "node_3" to 22421 swire "node_3" to 22422 awire "node_4" to 22465 iwire "node_4" to 22466 b

end deviceend testtest connectcheck "connectcheck"

timing module 2bottom mux 1ground module 0 card 5 ! Which card to wground module 1 card 3 ! for Connect Chewire "+5V" to 22362 ccguard ! Four guard wirewire "+5V" to 22364 ccguard ! guarded node.wire "+5V" to 22366 ccguardwire "+5V" to 22368 ccguardwire "ground" to 22370 ccground ! Five guard wirewire "ground" to 22372 ccground ! the board grounwire "ground" to 22374 ccgroundwire "ground" to 22376 ccgroundwire "ground" to 22378 ccgrounddevice "u101"

wire "~ccmux" to 20278 ccrefnode! Wire to the muwire "ground" to 20262 ccrefret! Wire to the boawire "node_1" to 21631 g

© Agilent T 4-30

Chapter 4


: The Wirelist File

wire "node_2" to 21645 g...

end deviceend test

© Agilent T 5-1

In this teso prerequisites associated with this chapter.

ools and Materialso required tools or materials associated with hapter.

echnologies 2002, 2003 Data Formats 06/2003

5555 The Fixture Files

chapter... � Overview, 5-2� What is a Fixture File?, 5-4� Programs that Use the Fixture File, 5-8

� Fixture File Syntax, 5-10

� Sample Fixture File, 5-46

� Fixture Defaults File, 5-51

� Sample Fixture Defaults File, 5-53

� User-Modifiable Fixture Components, 5-57

� Fixture Components Files Syntax, 5-60

� Sample Fixture Components Files, 5-63

� Standard and Advanced probe Spacing, 5-66


� Describe the structure and syntax of the fixture file.

� Explain the use of the fixture defaults file.

� Understand and use fixture components files.

PrerequisiThere are n

Required TThere are nusing this c

© Agilent T 5-2

Chapter 5

Overv t edit board test files with editors such as vi. editors do not update the file's header ation, such as the time-stamp, that Agilent

programs use. Use the BT-BASIC editor to xture files.

ng sections explain how to modify the .

Fixture File from Agilent Fixture tge probe locations.

ck resources.

fy wiring.

ixture electronics.

Fixture File from Agilent IPG Test t Edit.

t View/Edit Fixture File.

est Consultant opens a BT-BASIC window ads the fixture file into the BT-BASIC pace for you to edit. If only the fixture.o


: The Fixture Files

iew This chapter describes the structure and syntax of the fixture, the fixture defaults files and the fixture component files.

NOTEThe fixture file is used by the Fixture Generation Software and is explained in Chapter 6, Completing and Debugging Tests in Test & Fixture Development.

The Fixture Generation Software produces the fixture.o file and the reports and files necessary to build a test fixture.

The fixture file can be initialized with a fixture defaults file, if desired. The probe attributes can be changed by making changes to the fixture component files.

NOTERefer to Fixture Defaults File on page 5-51 for more information.

The Fixture Generation Software creates only the object file, fixture/fixture.o; it does not generate a source file. However, you can create a source file, fixture/fixture, from the object file.

NOTEDo noTheseinform3070 edit fi

The followifixture files

Modify theConsultan

a Chan

b Unblo

c Modi

d Add f

Modify theConsultan

a Click

b Selec

IPG Tand loworks

© Agilent T 5-3

Chapter 5


: The Fixture Files

object file exists, Test Consultant automatically generates a fixture file from that object file.

Modify the Fixture File Manuallya Open a BT-BASIC window.


c Generate a fixture source file from the fixture.o object file if the fixture source file doesn�t exist. Type:

list object "fixture/fixture.o" to“fixture/fixture”

d Load the fixture file. Type:get “fixture/fixture”

If a fixture source file already exists in the fixture directory, the Fixture Generation Software updates both the source and object files.

© Agilent T 5-4

Chapter 5

What iFile?

re Typere Sizere Part Numberrobes Allowedty ThresholdProbe ForceProbe Force

ilec Unitsrapping

CLUDEACEMENTTLINEOLINGEPOUTDEALTERNATESHERALTERNATESOUPRD

DEMENTNENGUT


: The Fixture Files

s a Fixture The fixture file is made up of two or more blocks. The first block is the fixture description block; it contains information about fixture keepouts, holes, and other options that effect the fixture. The fixture description block is followed by one or more board description blocks. Board description blocks are not allowed within a fixture defaults file. Each board description block contains board_xy information, board placement, probe attributes, and node attributes for a board to be tested on the fixture. The last block is called the protected unit block. This optional block contains wiring and node information typically used to describe connections and attributes for fixture electronics or for other custom applications.

NOTEThe fixture file, fixture.o, is created by the fixture generation software, which is run by IPG Test Consultant, during board test development. For more information, see Chapter 4, Generating Tests and Fixture Files in Test & Fixture Development.

Example 5-1 shows an example fixture file with two boards and a protected area that can be used for fixture electronics:

Example 5-1

OPTIONSFixtuFixtuFixtuTop PDensiHeavyLightAutofMetriWireW

KEEPOUTINCLUDEHOLES

BOARDINPLOUTOKENO

OT

GREND BOABOARD

INCLUPLACEOUTLITOOLIKEEPO

© Agilent T 5-5

Chapter 5

RESNIT

scription Blockdescription block of the fixture file bal information about the fixture. This includes: fixture options, fixture keepout ixture holes. Fixture description block is listed at the beginning of the file.

ons are listed in the OPTIONS block. This information shown in Table 5-1.

E, EXPRESS, NO-WIRE, CASSETTE,

T.

1, BANK2, or FULL

se, it is not present. Options include QPT

, this number is automatically placed in the file

n be ON or OFF.


: The Fixture Files

NODEPINSPROBESALTERNATESWIRES

OTHERALTERNATES

GROUPEND BOARDPROTECTED UNIT

NODEPINSWIRES

OTHERPINS

WIEND U

END

Fixture DeThe fixture contains gloinformationareas, and finformation

Fixture optiincludes the

Table 5-1 Fixture description block


Fixture Type Type of fixture to be used. This option can be: SIMPLATXG-50, XG-50 CASSETTE, QUICKPRESS, or JO

Fixture Size Size of the fixture to be used. This option can be: BANK

Fixture Handler Identifies the type of fixture handling hardware; otherwi(QuickPress) or JOT.

Fixture Part Number

Exact type of fixture to be used. Unlike the other optionsby the software.

Top Probes Allowed

Indicates if top side probes can be used. This option ca

© Agilent T 5-6

Chapter 5

description contains information such as:

lacement of the board on the fixture.

-Y coordinates of the board outline vertices.

of tooling holes.

of nodes and their attributes.

of fixture components that have not been ed to any nodes.

re inch allowed on the board. A value of 80 square inch.

are to be used in the fixture.

re to be used in the fixture.

matic identification of the fixture.

his option can be ON or OFF.

re. This option can be AUTO, SEMI AUTO,

nnot be placed.

ure.


: The Fixture Files

Board Description BlockThe board description block contains information about each board to be tested on the fixture. If a fixture is used to test only one board, there will be only one board description in the file; if, however, the fixture is used to test more than one board, there will be a board description block for each board in the fixture file.

Each board

� The p

� The X

� A list

� A list

� A listassign

Density Threshold Specifies the maximum probe force in ounces per squawould limit the number of eight ounce probes to ten per

Heavy Probe Force

Probe force, in ounces, of the heavy weight probes that

Light Probe Force Probe force, in ounces, of the light weight probes that a

Autofile A numeric code that is wired into the test fixture for auto

Metric Units The fixture reports are to be printed with metric units. T

WireWrapping Type of wirewrapping that will be performed on the fixtuWIRELESS, or MANUAL.

KEEPOUT Defines an area of the fixture where pins and probes ca

HOLES Lists optional hardware holes in a probe plate of the fixt

Table 5-1 Fixture description block (continued)


© Agilent T 5-7

Chapter 5

to you to determine whether the pins you lid and that they do not conflict with any

as, tooling pins, or other obstructions.


: The Fixture Files

This information is read from the board_xy.o file, for each board, and is modified by the fixture generation software.

NOTEBoard description blocks are not allowed in fixture default files.

Protected Unit Description BlockThe protected unit description block is used to reserve personality pins and external nodes in the fixture for custom applications. Because all information in this block is protected, it will not be removed or modified by the fixture generation software. Typically, you use this block to describe nodes that will be used for fixture electronics or to describe other wiring in the fixture that must not change when IPG Test Consultant is run during board test development or an ECO. This block lets you:

� Describe external nodes used in custom fixture electronics. These nodes can be wired to probes or personality pins used by a board test. You can also specify wire lengths and color to be used.

� Reserve personality pins for custom electronics or other external functionality in the board test. Because these resources are reserved, the fixture generation software will not automatically re-assign them in board tests.

We leave it select are vakeepout are

© Agilent T 5-8

Chapter 5

Prograthe Fix

file. Alternatively, the Board Placement uses a oard Placement decides the X-Y placement of ordinates from the board_xy. board_xy file. If Board Placement finds a erwise, it will check the fixture default file . If the fixture default object does not exist,

ly.

xy file, node and electrical information from the the fixture component files to determine ch node. You can influence the selection of and the fixture component files.

detectors, drivers, and receivers, to the s to minimize wire lengths. It stores these object wirelist, wirelist.o, is maintained in list, type:to "wirelist"

.


: The Fixture Files

ms that Use ture File

Several programs retrieve and modify data from the fixture.o file during the fixture generation process.

Table 5-2 Programs that use the Fixture/Fixture Defaults files

Program Description

BOARD PLACEMENT Creates the fixture directory and the fixture.o fixture defaults file to create the fixture.o file. Bthe board on the fixture using the board outline coYou can manually specify board placement in the placement specified in board_xy it will use it; othobject, if it exists, and use the placement specifiedBoard Placement will place the board automatical

PROBE SELECT Uses probe location information from the board_boards file, and probe attribute information from the best type of probe and probing location for eaprobes and locations by editing the board_xy file

MODULE PIN ASSIGNMENT (MPA)

Assigns module card resources, such as sources,probes. MPA assigns resources close to the probeassignments in a file called wirelist.o. Only thethe local board directory. To create a source wire

list object "wirelist.o"

on the BT-BASIC command line and press Return

© Agilent T 5-9

Chapter 5

ire assignment information into the s and files necessary for building your test escriptions found in the fixture component files

fixture.

tinued)


: The Fixture Files

FIXTURE TOOLING Adds power supply wiring and places all pin and wfixture.o file. Fixture tooling creates the reportfixture. Fixture tooling will also use the probe drill dto annotate the drill files.

PLOT GEN Uses the fixture.o file to generate plots of the

Table 5-2 Programs that use the Fixture/Fixture Defaults files (con

Program Description

© Agilent T 5-10

Chapter 5

Fixtur escription block can contain keywords:

RDUDEEMENTINEINGOUT

E - (NODE)ES - (NODE)RNATES - (NODE)SFERS - (NODE)S - (NODE)R

- (OTHER)ES - (OTHER)RNATES - (OTHER)SFERS - (OTHER)S - (OTHER)

UPBOARD

ed unit description block can contain

ECTED UNITE - (NODE)S - (NODE)


: The Fixture Files

e File Syntax This section describes the syntax of the fixture file.

NOTEThe syntax of the fixture file is not case-sensitive.

Each line of information, except list headings, must end with a semicolon. Board, node, and device.pin names must not contain colons (:) or tildes (~). The fixture description block can contain these keyword list headings:

� OPTIONS� HOLES� KEEPOUT� INCLUDE� DEFAULT PLACEMENT

The OPTIONS block contains keywords: � Fixture Type� Fixture Size� Fixture Part Number� Top Probes Allowed� Heavy Probe Force� Light Probe Force� Density Threshold� Autofile� Wirewrapping� Metric Units

The board d

� BOA� INCL� PLAC� OUTL� TOOL� KEEP� NOD� PINS� PROB� ALTE� TRAN� WIRE� OTHE� PINS� PROB� ALTE� TRAN� WIRE� GRO� END

The protectkeywords:

� PROT� NOD� PINS� WIRE

© Agilent T 5-11

Chapter 5

Probe Force <force>;(8)Probe Force <force>;(4)

ty threshold <value>;ile <code>;rapping <type>; (MANUAL)c Units <status>; (OFF)

S keyword marks the beginning of a block tions for the fixture (See above). The yword contains no parameters.

tax:

e specifies the type of test fixture that you ight types of fixtures are available.

ter 6, Completing and Debugging Tests in Fixture Development describes each fixture

ture file syntax, the fixture types are ith one-word designations. The Fixture Type described in Table 5-3 on page 5-12.


: The Fixture Files

� OTHER� PINS - (OTHER)� WIRES - (OTHER)� END UNIT

The last line of the fixture file contains the END keyword, which indicates the end of fixture information.

The Fixture Description BlockThis block contains three sections: options, keepout, and holes. The options section describes attributes of the fixture. Typically, you enter all these parameters, except the Fixture Part Number, in Board Consultant or load them from the fixture defaults file. When Board Placement runs later, it reads the options from the fixture defaults file object, if it exits. If the fixture defaults file object is not present, it reads the options contained in the board file. These options are then placed in the fixture.o file. For any option not specified, the values shown in parentheses are used. The keepout and holes sections describe areas of the fixture to be used for custom applications. Typically you enter these attributes using Fixture Consultant.

The fixture description block is organized as follows:OPTIONS

Fixture Type <type>; (EXPRESS)Fixture Size <size>; (FULL)Fixture Handler <type>;(QPT)Fixture Part Number <number>;Top Probes Allowed <status>;(OFF)

HeavyLightDensiAutofWirewMetri

INCLUDEKEEPOUTHOLES

OptionsThe OPTIONof global opOPTIONS ke

Options SynOPTIONS

Fixture TypeFixture Typare using. E

NOTEChapTest &type.

For the fixspecified woptions are

© Agilent T 5-12

Chapter 5

specifies the area of the testhead that the cover. BANK1 implies that the fixture will be bank 1 of the testhead (over modules 0 and

plies that the fixture will be installed on e testhead (over modules 2 and 3). FULL the fixture will be installed on both banks 1 ring the full testhead.

ecifies the size of the fixture. BANK1 and alf-size fixtures, covering half the testhead. ll-size fixture, covering all four modules. t be used with the Express Cassette fixtures.

Fixture Size syntax

ze <size>;

be:

s QuickPress fixture.

JOT fixture.

Fixture Type options (continued)

Description


: The Fixture Files

Example 5-2 Fixture Type syntax

Fixture Type <type>;

<type> can be:SIMPLATEEXPRESSNO-WIRECASSETTEXG-50XG-50 CASSETTEQUICKPRESSJOT

Fixture SizeFixture Sizefixture will installed on1). BANK2 imbank 2 of thimplies thatand 2, cove

<size> SpBANK2 are hFULL is a fuFULL canno

Example 5-3

Fixture Si

<size> can BANK1BANK2FULL

Table 5-3 Fixture Type options

Option Description

SIMPLATE SimPlate fixture.

EXPRESS SimPlate Express fixture.

NO-WIRE Agilent No-Wire Technology fixture.

CASSETTE Express Cassette fixture.

XG-50 SimPlate XG-50 fixture.

XG-50 CASSETTE XG-50 Cassette fixture.

QuickPres

JOT

Table 5-3

Option

© Agilent T 5-13

Chapter 5

Heavy probe force syntax

e force <force>;a <numeric constant>

Force force specifies the force, in ounces, of the t probes to be used in the fixture.

ecifies the spring force of the probe, in

Light probe force Syntax

e force <force>;a <numeric constant>

esholdshold is the maximum amount of probe

es per square inch) allowed to probe the value specified for density threshold is used the maximum number of probes per square n probe the board. If you don't specify a shold, the system uses a value of 800 for fixtures such as the Express Cassette fixture f 104 for vacuum fixtures such as the ture.

e, suppose you are using probes which are . of force each and the density threshold is is means that you can have a maximum of


: The Fixture Files

Fixture Part NumberIdentifies the exact type of fixture to be used. Unlike the other options, the fixture part number is automatically placed in the file by the software. The Fixture Part Number options are accessible via Agilent�s website.

Top Probes AllowedTop Probes Allowed specifies whether top electrical probes are allowed in the fixture. This attribute has no effect on TestJet probes.

ON specifies that top probes are allowed (the fixture must have a top plate). OFF specifies that top probes are not allowed. If you don't specify this, the system will assume OFF.

Example 5-4 Top Probes Allowed syntax

Top Probes Allowed <status>;

<status> can be:ONOFF

Heavy Probe ForceHeavy probe force specifies the force, in ounces, of the heavy weight probes to be used in the fixture.

<force> Specifies the spring force of the probe, in ounces.

Example 5-5

Heavy prob<force> is

Light ProbeLight probelight weigh

<force> Spounces.

Example 5-6

Light prob<force> is

Density ThrDensity threforce (ouncboard. The to calculateinch that cadensity thremechanicalor a value oSimPlate fix

For examplrated at 8 ozset to 80. Th

© Agilent T 5-14

Chapter 5

if the fixture is to be wired with either, an r a semi-automatic machine. If the fixture d by hand, you need to specify MANUAL. If O, the fixture wiring report will be sorted by , and length of wire. Locations will be

X-Y coordinates. If you specify MANUAL, the ng report will be sorted to avoid having to hat are already covered by other wires. ill be specified in brc (bank-row-column),

WIRELESS tells Probe Select not to block ture tooling also produces a nets file that can roduce files for most auto-routing

pecifies the format of the fixture reports. s a fully automatic, or a semi-automatic ing system. MANUAL implies that the operator e location and apply the wire-wrap.

WireWrapping syntax

ng <option>;

n be:

TOS


: The Fixture Files

10 probes per square inch on the board. The probes per square inch value is calculated by Probe Select.

<value> Specifies the maximum force in ounces per square inch from the probes within that area to probe the board.

Example 5-7 Density Threshold syntax

Density Threshold <value>;<value> is a <numeric constant>

AutofileAutofile specifies the identification number that should be wired into the fixture for auto-identification. This allows the correct board program(s) to be loaded when the operator loads the fixture.

<code> This is the identification number of the fixture, it is an integer value in the range from 11 to 4094. If you do not specify an autofile, Fixture Tooling will automatically assign a unique one.

Example 5-8 Autofile syntax

Autofile <code>;<code> is an <integer>

WireWrappingThe WIREWRAPPING keyword describes the technology used to wire the fixture. You need to specify AUTO or

Semi Auto

automatic, owill be wireyou use AUTcolor, gaugespecified infixture wiriwire areas tLocations wformat.

Specifying P-Pins. Fixbe used to pequipment.

<option> SAUTO impliewire-wrappmust find th

Example 5-9

WireWrappi

<option> caAUTOMANUALSEMI AUWIRELES

© Agilent T 5-15

Chapter 5

Specifies the name of the file whose to be included in the fixture file.

1 INCLUDE syntax

ilename>;

is a <string expression>

"/board/std_options";

ixture) T keyword specifies a series of points that ygon (at least three non-colinear points). n identifies an area of the fixture where no pins or probes can be placed. The points are y their X-Y coordinates with respect to the in. The points can be listed in either a r counter-clockwise direction starting at the orner of the area. Each KEEPOUT keyword e keepout area.

ut area can specify a side attribute. This icates which probe plate contains the a. If no side attribute is specified, the a applies to the bottom probe plate.

use a fixture keepout area with a board a. A fixture keepout area is fixed relative e tooling origin. A board keepout area is


: The Fixture Files

Metric UnitsMetric Units specifies if metric units are to be used in the fixture reports.

<option> Specifies if metric units are to be used. OFF specifies units as tenth mils (thousandths of an inch)

Example 5-10 Metric Units syntax

Metric Units <option>;

<option> can be:ONOFF

IncludeThe INCLUDE keyword allows the contents of a specified file to be inserted at that point in the file. Include statements may be nested to any depth; this is useful for incorporating standard options and configurations into new board files. When the new file is stored, the information from the include file becomes part of the new file, and the link to the include file is lost. The include filename can be a relative or an absolute pathname. The filename should be enclosed in quotes.

<filename>

contents are

Example 5-1

INCLUDE <f

<filename>

Example:INCLUDE

Keepout - (FThe KEEPOUdefine a polThis polygopersonality described bfixture origclockwise olower left cspecifies on

Each keepoattribute indkeepout arekeepout are

Do not confkeepout areto the fixtur

© Agilent T 5-16

Chapter 5

re Size BANK2..

rapping MANUAL;BOTH, 20000, 20000, 40000, 40000;oard1

KEEPOUT options

Description

X_coordinate of a keepout point.

Y_coordinate of a keepout point.

Keepout area on the bottom probe plate. When no side is specified, bottom is the default.

Keepout area on the top probe plate.

Keepout area on both the top and bottom probe plates.


: The Fixture Files

relative to the board origin and can change if the board orientation changes. Also, each fixture keepout area is specified following the OPTIONS statement but before the first BOARD statement. A board keepout area is specified only after a BOARD statement. For more information about board keepouts, see the KEEPOUT statement listed in Board Description Block on page 5-6 section. The Keepout options are described in Table 5-4 on page 5-16.

Example 5-12 KEEPOUT syntax

KEEPOUT<x_coord>, <y_coord><x_coord>, <y_coord>

. . . .<x_coord>, <y_coord>;

KEEPOUT <attribute><x_coord>, <y_coord><x_coord>, <y_coord>

. . . .<x_coord>, <y_coord>;

<attribute> can be:BOTTOMTOPBOTH


Example:OPTIONS

Fixture Type EXPRESS;

Fixtu. . .. . .Wirew

KEEPOUT20000400004000020000

BOARD b. . .. . .

Table 5-4

Option

<x_coord>

<y_coord>

BOTTOM

TOP

BOTH

© Agilent T 5-17

Chapter 5

t Placement options are shown in Table 5-6 9.

Description Block description block describes the fixturing for is to be tested on the fixture. There is one iption block for each board. The following cribe the keywords used.

HOLES options

Description

Diameter of the hole in tenth mils.

and Specify the location of the hole.

The TOP keyword specifies that the hole is in the top probe plate; the bottom keyword specifies that the hole is in the bottom probe plate; the BOTH keyword specifies that the hole is in both probe plates. If no side is specified, the hole is in the bottom probe plate only.


: The Fixture Files

HolesThe HOLES keyword indicates a list of hardware holes in the probe plates of a fixture. Holes options are described in Table 5-5.

Example 5-13 HOLES syntax

HOLES<diameter>, <X coord> <Y coord>;<diameter>, <X coord> <Y coord> <side>;

<diameter> is a constant<X coord> and <Y coord> are constants

side> can be:BOTTOMTOPBOTH

Example:HOLES

2500, 145000 -70000;2500, 145000 70000 TOP;2500, 155000 70000;2500, 155000 -7000 BOTH;

Default PlacementThe default placement is restricted syntax and can only be used in fixture default files. This placement will override Board Placement's internal default placement.

The Defaulon page 5-1

The BoardEach boarda board thatboard descrsections des

Table 5-5

Option

<diameter>

<X coord> <Y coord>

<side>

© Agilent T 5-18

Chapter 5

5 BOARD syntax

rd_id>is a <string expression>

E keyword allows the contents of a specified serted at that point in the file. Include

ay be nested to any depth; this is useful for g standard options and configurations into iles. When the new file is stored, the from the include file becomes part of the d the link to the include file is lost. The name can be a relative or an absolute he filename should be enclosed in quotes.

Specifies the name of the file whose to be included in the fixture file.

6 INCLUDE syntax

ilename>;

is a <string expression>

"/board/std_options";


: The Fixture Files

The board description block is organized as follows:

Example 5-14 BOARD description block

BOARDINCLUDEPLACEMENTOUTLINETOOLINGKEEPOUTNODE

PINSPROBESALTERNATESTRANSFERSWIRES. . .

OTHERPINSPROBESALTERNATESTRANSFERSWIRESGROUP

END BOARD

BoardThe BOARD keyword marks the start of the description of all the pieces of the specified board.

<board_id> specifies the name of the board to be described.

Example 5-1

BOARD <boa<board_id>

IncludeThe INCLUDfile to be instatements mincorporatinnew board finformationnew file, aninclude filepathname. T

<filename>

contents are

Example 5-1

INCLUDE <f

<filename>

Example:INCLUDE

© Agilent T 5-19

Chapter 5

Board placement rotation

E keyword specifies a series of points that oard�s corners, at the maximum extents. At nique, non-colinear points define the shape as a polygon. List the coordinates of each

ther a clockwise or counter-clockwise m the starting point coordinate. Do not

arting point again at the end; the compiler ly completes the polygon. If your board has tline, specify the outline as a polygon. The ons are described in Table 5-7 on page 5-20.

8 OUTLINE syntax

d>,<y_coord>d>,<y_coord>


: The Fixture Files

PlacementThe PLACEMENT keyword, supplied by Board Placement, specifies the board's position on the fixture as X and Y offsets from the fixture's tooling origin to the board origin. The placement also specifies the rotation of the board. The rotation is applied to the board first, then the X and Y offsets. Placement options are described in Table 5-6.

Example 5-17 PLACEMENT syntax

PLACEMENT <x_offset>, <y_offset> <rotation>;<x_offset>, <y_offset> <rotation> are<numeric constants>

Example:PLACEMENT 70362, -10198 90;

Figure 5-1

OutlineThe OUTLINdefine the bleast three uof the boardcorner in eidirection frore-list the stautomaticala circular ouOutline opti

Example 5-1

OUTLINE<x_coor<x_coor

Table 5-6 PLACEMENT options

Option Description

<x_offset> X_offset, in tenth mils, of the board origin with respect to the fixture origin.

<y_offset> Y_offset, in tenth mils, of the board origin with respect to the fixture origin.

<rotation> Rotation of the board in degrees. The positive X axis is 0 degrees. See Figure 5-1.

© Agilent T 5-20

Chapter 5

G keyword marks the beginning of a list of oles. The list is needed to avoid conflicts

OUTLINE options

Description

X_coordinate, in tenth mils, of outline point.

Y_coordinate, in tenth mils, of outline point.

(60000, 120000) (150000, 120000)

(60000, 110000)

(150000, 0)


: The Fixture Files

<x_coord>,<y_coord>. . . . , . . . .. . . . , . . . .

<x_coord>,<y_coord>;

<x_coord>,<y_coord> are <numeric constants>

Example:OUTLINE

0, 0150000, 0150000, 12000060000, 12000060000, 1100000, 110000;

Figure 5-2

ToolingThe TOOLINall tooling h

Table 5-7

Option

<x_coord>

<y_coord>

(0, 110000)

(0, 0)

© Agilent T 5-21

Chapter 5

oard) T keyword specifies a series of points that ygon (at least three non-colinear points) that area of the fixture (above or below the ement) where no personality pins or probes d. The points can be listed in either a r counterclockwise direction starting at the orner of the area. Each KEEPOUT keyword e keepout area.

ut area can specify a side attribute. This icates which probe plate of the fixture keepout area. If no side attribute is e keepout area applies to the bottom probe

outs should not be confused with fixture board keepout area can change relative to ooling origin if the board placement fixture keepout remains fixed relative to ooling origin and does not change if the ment is modified. For information about epouts, refer to Keepout - (Fixture) on he Keepout options are described in Table 5-22.

0

d>,<y_coord>d>,<y_coord>d>,<y_coord>


: The Fixture Files

with personality pins. The Tooling options are described in Table 5-8 on page 5-21.

Example 5-19 TOOLING syntax

TOOLING<size> <x_coord>,<y_coord>;<size> <x_coord>,<y_coord>;<size> <x_coord>,<y_coord>;. . . . . . . . . .. . . . . . . . . .

<size> <x_coord>,<y_coord>;

<size> <x_coord>,<y_coord> are <numericconstants>

Example:TOOLING

3750 30650, 30700;3750 72500, 36250;

Keepout - (BThe KEEPOUdefine a poldescribes anboard's placcan be placeclockwise olower left cspecifies on

Each keepoattribute indcontains thespecified, thplate.

Board keepkeepouts. Athe fixture tchanges. A the fixture tboard placefixture kepage 5-15. T5-9 on page

Example 5-2

KEEPOUT<x_coor<x_coor<x_coor

Table 5-8 TOOLING options

Option Description

<size> Diameter of tooling hole in ten thousandths of an inch. This value can be 2000 or 3750.

<x_coord> X_coordinate, in tenth mils, of tooling hole.

<y_coord> Y_coordinate, in tenth mils, of tooling hole.

© Agilent T 5-22

Chapter 5

rd)eyword marks the beginning of a list of all , and wires that connect to the node used in . Items that can be included in the list are: ES, ALTERNATES, TRANSFERS, and ICAL specifies that the shortest possible

e used for this node. The Node options are Table 5-10 on page 5-23.

Keepout area on the bottom probe plate. When no side is specified, bottom is the default.

Keepout area on the top probe plate.

Keepout area on both the top and bottom probe plates.

KEEPOUT options (continued)

Description


: The Fixture Files

. . . .

. . . .<x_coord>,<y_coord>;

KEEPOUT <attribute><x_coord>,<y_coord><x_coord>,<y_coord><x_coord>,<y_coord>

. . . .

. . . .<x_coord>,<y_coord>;

<attribute> can be:BOTTOMTOPBOTH


Example:KEEPOUT TOP

20000, 2000040000, 2000040000, 4000020000, 40000;

Node - (BoaThe NODE kpins, probesa board testPINS, PROB

WIRES. CRITwire must bdescribed in

Table 5-9 KEEPOUT options

Option Description

<x_coord> X_coordinate of a keepout point.

<y_coord> Y_coordinate of a keepout point.

BOTTOM

TOP

BOTH

Table 5-9

Option

© Agilent T 5-23

Chapter 5

ode_id> <usage> CRITICAL


n be:

ux>;

are in the range 1 to 24.


: The Fixture Files

Example 5-21 NODE syntax

NODE <node_id>NODE <node_id> <usage>NODE <node_id> CRITICAL

NODE <n

<node-id>

<usage> caFUNCTIONALGROUNDPOWER <supply> <V> ;POWER <supply> <V> <mux>;OWER <supply> <V> ; . . . <supply> <V> ;POWER <supply> <V> <mux>; . . . <supply> <V> <m

<supply> is an <integer constant><V> & are <numeric constants><mux> can be:MULTIPLEXED

Example:NODE clock CRITICALNODE +5V POWER

1 5.00 3.00 MULTIPLEXED;


Option Description

<node-id> Node name.

CRITICAL The shortest possible wire must be used for the node.

<supply> The power supply connected to the specified node; supplies

<V> Programmed voltage of the power supply.

© Agilent T 5-24

Chapter 5

.> <pin_info>;

can be:

EE <dy>E <dy> <dx>

s an <integer>dx> are <numeric constants>

;

ys to the boards-under-test. This option is board panels. The MULTIPLEXED keyword to access the asru card supplies. However, des. Parallel supplies can also use the

on and safeguard turned off.


: The Fixture Files

PinsThe PINS keyword, when used in conjunction with the NODE keyword in a board description block, marks the beginning of a list of all the personality pins used for the specified node. OVERRIDE is used to mark a pin that would normally be BLOCKED, but which is being used anyway by installing a special personality pin. The Pins options are described in Table 5-11 on page 5-25.

Example 5-22 PINS syntax

PINS<pin_id> <pin_info>;<pin_id> <pin_info>;

. . .<pin_id

<pin_info><dy>OVERRIDOVERRIDOVERRID

<pin_id> i<dy> and <

Example:PINS

11656

 Programmed current of the power supply.

<mux> Allows the power supplies to be multiplexed through the relauseful in some cases of multiple board fixtures and multiple forces fixture tooling to insert personality pins into the fixturefixture tooling is not allowed to wire the pins to the power nomultiplexing option.

FUNCTIONAL The node is used for library tests that have backtrace turned

GROUND The node is used for ground.

POWER The node is used for power.

Table 5-10 NODE options (continued)

Option Description

© Agilent T 5-25

Chapter 5

keyword, when used in conjunction with yword in a board description block, marks g of a list of probes connected to the de. Probes are numbered starting with one. ers may be greater than the number of

to gaps in the numbering. Normal probes are th P; transfer probes with T. Probes options d in Table 5-12.

PROBES options

Description

Probe diameter.

Probe diameter.

es will be used if no other option is specified.

Probe length, if LONG is not specified the length is assumed to be short.

The device-pin on which the specified node is to be placed.

The probe is to be on the top side of the fixture.

The probe is light force, if LWT is not specified then the probe is assumed to be heavy force. This attribute is assigned only by Probe Select.


: The Fixture Files

10834 25,0;10730 OVERRIDE 10 20;

ProbesThe PROBESthe NODE kethe beginninspecified noProbe numbprobes due prefixed wiare describe

Table 5-11 PINS options

Option Description

<pin_id> The personality pin expressed as a bank,row,column, brc.

<dy> Offset, in tenth mils, used for personality pins that are bent to avoid probes on the board. The offset is added to the personality pin base location to get its actual fixture location. This offset is in the Y direction only.

<dx> Offset, in tenth mils, in the X direction. It is added to the X-coordinate of the personality pin's base location. Use this when specifying special personality pins with the OVERRIDE option.

OVERRIDE Marks a pin that would normally be BLOCKED, but will be used.

Table 5-12

Option

50MIL

75MIL

100 mil prob

LONG

<dev.pin>

TOP

LWT

© Agilent T 5-26

Chapter 5

here the previously specified node can be se are potential locations on the node listed esirability. Any of these can be chosen to be

obing location. The X-Y locations should be ed fixture file coordinates. The Alternates described in Table 5-13.

4 ALTERNATES syntax

d>,<y_coord> <options>;d>,<y_coord>;. .d>,<y_coord>;

an be:

ALTERNATES options

Description

X_coordinate, in tenth mils, of the node with respect to the board origin.

Y_coordinate, in tenth mils, of the node with respect to the board origin.

Probe location is on the fixture top plate.

Device-pin that the node is connected to.

50 mil probe.

75 mil probe.


: The Fixture Files

Example 5-23 PROBES syntax

PROBES<probe_id> <x_coord>,<y_coord> <options>;<probe_id>;

. . .<probe_id>;

<probe_id> is an <alpha-numeric expression><x_coord> <y_coord> are <numeric constants><options> can be:

<dev.pin>TOP<probe_info><dev.pin> TOP<dev.pin> <probe_info>TOP <probe_info>

<probe_info> can be:LWT<size>LWT <size>

<size> can be:50MIL75MILLONG

Example:PROBES

P12 34750, 84820 LWT;P23 16080, 12946 Y1.3 TOP;

AlternatesThe ALTERNATES keyword, when used in conjunction with the NODE keyword in a board description block, marks the beginning of a list containing the X-Y

locations wprobed; thein order of dan actual prin normalizoptions are

Example 5-2

ALTERNATES<x_coor<x_coor

.<x_coor

<options> c

Table 5-13

Option

<x_coord>

<y_coord>

TOP

<dev.pin>

50MIL

75MIL

© Agilent T 5-27

Chapter 5


: The Fixture Files

TOP<dev.pin>TOP <dev.pin><size>

<x_coord>, <y_coord> are <numeric constants><dev.pin> is a <string constant>

<size> can be:50MIL75MIL

Example:ALTERNATES

25820, 96740 U1.5;28820, 96740 U2.5 TOP;31820, 96740 U3.5 50MIL;

TransfersThe TRANSFERS keyword, when used in conjunction with the NODE keyword in a board description block, marks the beginning of a list of transfer probes used to carry signals from the bottom of the fixture to the top plate. It should only exist if top-probes-allowed is set to ON. The Transfers options are described in Table 5-14 on page 5-28.

© Agilent T 5-28

Chapter 5

o pin. As wires are added to the fixture, they rmation associating other components of ith the specified node. When listing the

utes: color, gauge, and length, you must list , of them; you cannot list just one or two of wire is included in a GROUP, the WIRES cludes the group designation and the type of

s in the fixture. The probe_id will be prefixed by

ct to the board origin.

ct to the board origin.


: The Fixture Files

Example 5-25 TRANSFERS syntax

TRANSFERS<transfer_info>;<transfer_info>;

. . .<transfer_info>;

<transfer_info> can be:<probe_id> <x_coord>,<y_coord><probe_id> is a <string expression><x_coord>, <y_coord> are <numeric constants>

Example:TRANSFERS

T56 98700,38760;

WiresThe WIRES keyword, when used in conjunction with the NODE keyword in a board description block, marks the beginning of a list of wires, used to connect other components of the specified node together. Wires may be specified as connected from: pin to probe, probe to

pin, or pin tprovide infothe fixture wwires attriball, or nonethem. If thestatement in

Table 5-14 TRANSFERS options

Option Description

<probe_id> A number from 1 to N where N is number of probea T (to indicate that it is a transfer probe).

<x_coord> X_coordinate, in tenth mils, of the node with respe

<y_coord> Y_coordinate, in tenth mils, of the node with respe

© Agilent T 5-29

Chapter 5


: The Fixture Files

wire. The Wires options are described in Table 5-15 on page 5-30.

Example 5-26 WIRES syntax

WIRES<wire_info>;<wire_info>;

. . .<wire_info>;

<wire_info> can be:<id> TO <id><id> TO <id> <color> <gauge> <length><id> TO <id> <type> <gauge> <length> <group des>

<color> is a <string constant><gauge> is an <integer><length> is a <numeric constant>

<id> can be:<probe_id><pin_id>

<type> can be:"Tw-pr"Coax

<probe_id> & <pin_id> are <string expressions>

© Agilent T 5-30

Chapter 5

an be included in the list are: PINS,TERNATES, TRANSFERS, and WIRES.

of the wire is connected to.

20 characters.

ir or coaxial.

tors as G# where # is a number. The first group and so on.


: The Fixture Files

Example:WIRES

P23 to T56;11656 to T56;10834 to P12;22301 to P814 Coax 28 1.00, G1;22377 to P814 "Tw-pr" 28 1.00, G2;

OtherThe OTHER keyword in a board description block marks the beginning of a list of information about fixture components that have not been associated with a node.

Items that cPROBES, AL

Table 5-15 WIRES options

Options Description

<probe_id> Probe that one end of the wire connects to.

<pin_id> Bank-row-column position of the pin that one end

<color> Color of the wire, this is an arbitrary name of up to

<gauge> Gauge of the wire.

<length> Length of the wire.

<type> Type of wire to be used on the group � twisted pa

<group des> The group. Fixture Tooling assigns group designais assigned G1; the second group is assigned G2,

© Agilent T 5-31

Chapter 5

DRILLED;SOCKETED;-15;BLOCKED;OVERRIDE -10 20;

PINS options

Description

Name of the device-pin.

Offset, in tenth mils, used for personality pins that are bent to avoid probes on the board. The offset is added to the personality pin base location to get its actual fixture location.

Offset, in tenth mils, in the X direction. It is added to the X-coordinate of the personality pin's base location. Use this when specifying special personality pins with the OVERRIDE option.

Refers to a location that has been drilled, but does not have a pin installed.

Refers to a location that has a personality pin installed.


: The Fixture Files

Syntax:OTHER


PinsThe PINS keyword, when used in conjunction with the OTHER keyword in a board description block, marks the beginning of a list of personality pins that have some attributes, or which have not been assigned to any nodes. The Pins options are described in Table 5-16 on page 5-31.


PINS<pin_id>;<pin_id> <dy>;<pin_id> <status>;<pin_id> <status> <dy>;<pin_id> OVERRIDE <dy>;<pin_id> OVERRIDE <dy> <dx>;

<pin_id> is a <string expression><dy> and <dx> are <numeric constants>

<status> can be:DRILLEDSOCKETEDBLOCKED

Example:PINS

1345613457116081041712110

Table 5-16

Option

<pin_id>

<dy>

<dx>

DRILLED

SOCKETED

© Agilent T 5-32

Chapter 5

keyword, when used in conjunction with eyword in a board description block, marks g of a list of unused probes. In general, they

hat once contacted a node, but which ard change no longer are physically under a robe-id is kept so that the probe may be y a wire. Probes options are described in

atically numbered in the same sequence by total number of probes and transfer pins in the a P; the probe_id for a transfer pin will be re transfer pins are assigned numbers. For and transfer pins T101 - T150. When mbers not already assigned to probes or

board origin.

board origin.

d and probe force specifications from Global


: The Fixture Files

ProbesThe PROBESthe OTHER kthe beginninare probes tthrough a bonode. The preferred to bTable 5-17.

BLOCKED Refers to a personality pin which cannot be used due to interference with a probe.

OVERRIDE Marks a pin that would normally be BLOCKED.

Table 5-16 PINS options (continued)

Option Description

Table 5-17 PROBES options

Option Description

<probe_id> The name of the probe. Probes and transfer pins are automTest Consultant, using numbers from 1 to N where N is thefixture. The probe_id for a regular probe will by prefixed byprefixed by a T. Probes are always assigned numbers befoexample, The 3070 will assign probes numbers P1 - P100,assigning probe names manually, be sure to assign nutransfer pins.

<x_coord> X_coordinate, in tenth mils, of the probe with respect to the

<y_coord> Y_coordinate, in tenth mils, of the probe with respect to the

TOP Probe is on the top side of the fixture.

LWT Light weight probe. Probe Select uses the density thresholOptions to determine the need for light weight probes.

© Agilent T 5-33

Chapter 5

be:

970, 32670;800, 32500 TOP;520, 76920 LONG;400, 76800 LWT;

ATES keyword, when used in conjunction ER keyword in a board description block,

eginning of a list of unused probe locations. these locations were once candidates for were not selected during the probe selection ese locations are physically no longer under se locations are partially drilled, but do not


: The Fixture Files

Example 5-28 PROBES syntax

PROBES<probe_id> <x_coord>,<y_coord> <options>;<probe_id>;

. . .<probe_id>;

<probe_id> is an <alpha numeric expression><x_coord>, <y_coord> are <numeric constants>

<options> can be:<dev.pin>TOP<probe_info><dev.pin> TOP<dev.pin> <probe_info>TOP <probe_info>

<probe_info> can be:LWT<size>LWT <size>

<size> can 50MIL75MILLONG

Example:PROBES

P1 66P2 66P3 22P4 22

AlternatesThe ALTERNwith the OTHmarks the bIn general, probing butprocess. Tha node. The

50MIL 50 mil probe instead of a 100 mil probe.

75MIL 75 mil probe instead of a 100 mil probe.

LONG Long probe for dual stage testing.

Table 5-17 PROBES options (continued)

Option Description

© Agilent T 5-34

Chapter 5

an be:

n>v.pin>

<y_coord> are <numeric constants>is a <string constant>

be:

TES85600 50MIL;

ERS keyword, when used in conjunction ER keyword in a board description block,

eginning of a list of transfer probes that are ed with any node. They are kept with this se that is where they were created, but they d for any other board on the fixture. TestJet,

, and ConnectCheck transfer pins are this section.

ally adding transfer pins, do not assign pin t are already used for probes or other

s. If you do, you will get a compilation error e that follow:


: The Fixture Files

contain a probe receptacle. The Alternates options are described in Table 5-18.


ALTERNATES<x_coord>,<y_coord> <options>;<x_coord>,<y_coord>;

. . .<x_coord>,<y_coord>;

<options> cTOP<dev.piTOP <de<size>

<x_coord>,<dev.pin>

<size> can 50MIL75MIL

Example:ALTERNA92200,

TransfersThe TRANSFwith the OTHmarks the bnot associatboard becaucould be useQuickPressincluded in

When manunumbers thatransfer pinsuch as thos


Option Description

<x_coord> X_coordinate, in tenth mils, of the node with respect to the board origin.

<y_coord> Y_coordinate, in tenth mils, of the node with respect to the board origin.

<dev.pin> Device pin the probe will contact if installed.

TOP Probe is located on the top side of the fixture.

50MIL 50 mil probe.

75MIL 75 mil probe.

© Agilent T 5-35

Chapter 5

run Board Place again. (WARNING

ese errors, assign numbers at T10000 and bers up to 1 million are available).

rs options are described in Table 5-19.

the same sequence by Test Consultant using s and transfer pins in the fixture. The probe_id

or a transfer pin will be prefixed by a T. Probes signed numbers. For example, The 3070 will 1 - T150. When you assign transfer pin 0 so that you are sure to assign a number that

e board origin.

e board origin.


: The Fixture Files

• A transfer probe was defined previously.Each transfer probe should appear in theFDF source once in a TRANSFERS statement.It may appear in WIRES statements as oftenas necessary. (ERROR FDF29)

• Transfer probe conflicts with a personalitypin. The board has been placed in such aposition that a transfer probe interfereswith a personality pin directly below it.This wastes both resources. Perhaps you

shouldFDF2)

To avoid thabove (num

The Transfe

Table 5-19 TRANSFERS options

Option Description

<transfer_id> Probes and transfer pins are automatically numbered in numbers from 1 to N where N is the total number of probefor a regular probe will by prefixed by a P; the probe_id fare always assigned numbers before transfer pins are asassign probes numbers P1 - P100, and transfer pins T10numbers manually, we recommend you start at T1000is not yet used.

<x_coord> X_coordinate, in tenth mils, of the node with respect to th

<y_coord> Y_coordinate, in tenth mils, of the node with respect to th

<probe_type> Whether or not a probe is installed.

DRILLED Implies that only a hole exists at that location.

SOCKETED Implies that a regular transfer probe is installed.

© Agilent T 5-36

Chapter 5

r end are moved to that node, in the NODE list. describes Wires options.

1 WIRES syntax

_info>;_info>;. ._info>;

can be:> to <pin_id>> to <pin_id> <color> <gauge>

n an <alpha-numeric sting>a <string constant>an <integer>

s a <numeric constant>

to 20125 black 28 8.00;


: The Fixture Files

Example 5-30 TRANSFERS syntax

TRANSFERS<probe_id> <transfer_info>;<probe_id> <transfer_info>;

. . .<probe_id> <transfer_info>;

<probe_id> is a <string expression>

<transfer_info> can be:<x_coord>,<y_coord><x_coord>,<y_coord> <probe_type>

<x_coord>, <y_coord> are <numeric constants>

<probe_type> can be:DRILLEDSOCKETED

Example:TRANSFERS

T57 10780, 34920 SOCKETED;90880, 65840;

WiresThe WIRES keyword, when used in conjunction with the OTHER keyword in a board description block, marks the beginning of a list of wires that connect fixture components that are not on a node. A wire may only be specified as connected from pin to pin. If either of its ends connects to a component that is on a node, the wire

and its otheTable 5-20

Example 5-3

WIRES<wire<wire

.<wire

<wire_info><pin_id<pin_id

<length><pin_id> i<color> is<gauge> is<length> i

Example:WIRES

21325

© Agilent T 5-37

Chapter 5

he Group options are described in Table e 5-38.

2 GROUP syntax

up des> <wire type>ode name>

in name>;

robe name>;ode name>

in name>;

robe name>;s> is a <string constant>

can be:

> is a <string constant>is a <numeric constant>

e> is an <alpha numeric constant>

WISTED5BATT"

377;

14;


: The Fixture Files

GroupThe GROUP keyword marks the beginning of a list of probes that are to be wired as a group. The GROUP keyword also specifies the group designator and the type of wiring to be used. Pins and probes of a group are separated with a semicolon (;). Only one group may be specified under each GROUP keyword.

Groups must consist of two nodes that are probed on the bottom of the board. The compiler determines if the distance between the probes specified in a group is too great for the wire type of that group. The maximum separation for a COAX group is 0.5 inches; the maximum separation for a TWISTED group is 1.0 inch. The compiler generates a warning if this distance is

exceeded. T5-21 on pag

Example 5-3

GROUP <groNODE <n

PINTWISTEDCOAX

<node name<pin name><probe nam

Examples:GROUP G1 T

NODE "+PIN

22PROBE

P8


Option Description

<pin_id> Name of the pin that one end of the wire is connected to.

<color> Color of the wire, this is an arbitrary name of up to 20 characters.

© Agilent T 5-38

Chapter 5

rd marks the end of a board description

syntax:RD

Unit Description Blockal block is used to reserve personality pins, r custom applications. This block can also s to be used externally for fixture Because all entries in this block are om modification, the fixture generation nnot re-assign any resources already this block. You can also use this block as a cribe how to wire your custom application, er provided to the fixture builder in the rt. Typically, you will use Fixture Consultant s information.

ed unit description block is organized as

3

ED UNIT

NSRES

NS


: The Fixture Files

NODE "16.0MHZ"PIN

22378;PROBE

P3;GROUP G2 COAX

NODE "U1-1"PIN

22301;PROBEP

813;NODE "U1-2"

PIN22302;

PROBEP4;

End BoardThis keywoblock.

END BOARD END BOA

Protected This optionor BRCs, fodefine nodeelectronics.protected frsoftware caallocated inplace to deswhich is latwiring repoto create thi

The protectfollows:

Example 5-3

PROTECTNODE

PIWI

OTHERPI

Table 5-21 GROUP options

Option Description

<group des> A group of wires.

<node name> Name of one node in the group.

<pin name> Bank-row-column position of a pin used with a node.

<probe name> Probe number used with a node.

<wire type> Wire to use: coaxial or twisted pair.

© Agilent T 5-39

Chapter 5


n be:NAL

supply> <V> ;supply> <V> <mux>;supply> <V> ; . . . <supply> <V>

supply> <V> <mux>; . . .V> <mux>;> is an <integer constant>I> are <numeric constants>an be: MULTIPLEXED

IRE 10K RESISTOR TO PROBE"

0 TO TERMINAL;IRE 10K RESISTOR TO BRC"

8137 TO TERMINAL;


: The Fixture Files

WIRESEND UNIT

Protected UnitThis keyword identifies the beginning of a protected unit description block. If used, this block must follow the last board description block in the fixture file. Only one protected unit block is allowed. The end of the block is identified by the END UNIT keyword.

Protected unit syntax:PROTECTED UNIT

The PROTECTED UNIT keyword has no parameters.

Node - (External)The NODE keyword in a protected unit marks the beginning of a list of pins and wires that connect to an external node. This external node can then be used for custom applications or fixture electronics. The node name must be unique; it must not conflict with any other node name specified in the fixture file. The Node options are described in Table 5-22 on page 5-40.

Example 5-34 NODE syntax

NODE <node_id>NODE <node_id> <usage>NODE <node_id> CRITICALNODE <node_id> <usage> CRITICAL

<node-id>

<usage> caFUNCTIOGROUNDPOWER <POWER <POWER <

;POWER <

<supply> <<supply<V> & <<mux> c

Examples:NODE "W

WIRESP1

NODE "WWIRES

21

© Agilent T 5-40

Chapter 5

ormally be BLOCKED, but which is being y by installing a special personality pin. The s are described in Table 5-23 on page 5-41.

ode.

; supplies are in the range 1 to 24.

gh the relays to the boards-under-test. This xtures and multiple board panels. The sert personality pins into the fixture to access ot allowed to wire the pins to the power nodes.

tion.

ace turned on and safeguard turned off.


: The Fixture Files

PinsThe PINS keyword, when used in conjunction with the NODE keyword in a protected unit, marks the beginning of a list of all personality pins reserved for use with the specified external node. OVERRIDE is used to mark a pin

that would nused anywaPins option


Option Description

<node-id> External node name.

CRITICAL The shortest possible wire must be used for the n

<supply> The power supply connected to the specified node

<V> Programmed voltage of the power supply.

 Programmed current of the power supply.

<mux> Allows the power supplies to be multiplexed throuoption is useful in some cases of multiple board fiMULTIPLEXED keyword forces fixture tooling to inthe asru card supplies. However, fixture tooling is nParallel supplies can also use the multiplexing op

FUNCTIONAL The node is used for library tests that have backtr

GROUND The node is used for ground.

POWER The node is used for power.

© Agilent T 5-41

Chapter 5

keyword, when used in conjunction with the rd in a protected unit, marks the beginning ires used to connect other components to

node. As wires are added, they provide associating other components in the fixture

PINS options

Description

The personality pin expressed as a bank,row,column, brc.

Offset, in tenth mils, used for personality pins that are bent to avoid probes on the board. The offset is added to the personality pin base location to get its actual fixture location. This offset is in the Y direction only.

Offset, in tenth mils, in the X direction. It is added to the X-coordinate of the personality pin's base location. Use this when specifying special personality pins with the OVERRIDE option.

Marks a pin that would normally be BLOCKED, but will be used.


: The Fixture Files


PINS<pin_id> <pin_info>;<pin_id> <pin_info>;

. . .<pin_id> <pin_info>;

<pin_info> can be:• <dy>• OVERRIDE• OVERRIDE <dy>• OVERRIDE <dy> <dx>

<pin_id> is an <integer><dy> and <dx> are <numeric constants>

Examples:PINS

11656;10834 25,0;10730 OVERRIDE 10 20;

WiresThe WIRES NODE keywoof a list of wthe externalinformation

Table 5-23

Option

<pin_id>

<dy>

<dx>

OVERRIDE

© Agilent T 5-42

Chapter 5

to P12;o TERMINAL BLACK 28 10.0;

WIRES options

Description

Name of probe that one end of the wire is connected to.

Bank-row-column position of the pin that one end of the wire is connected to. If pin_id to pin_id wiring is specified, both pins must only appear in the protected unit section.

Specifies that one end of the wire is to be left unconnected in the wiring instructions. This open ended wire can later be used to connect to fixture electronics or some other custom application.

Color of the wire, this is an arbitrary name of up to 20 characters.

Gauge of the wire.

Length of the wire.


: The Fixture Files

with the external node. When specifying wire attributes: color, gauge, and length, you must list all, or none, of them. The Wires options are described in Table 5-24 on page 5-42.

Example 5-36 WIRES syntax

WIRES<wire_info>;<wire_info>;

. . .<wire_info>;

<wire_info> can be:<id> to <id><id> to TERMINAL<id> to <id> <color> <gauge> <length><id> to TERMINAL <color> <gauge> <length>

<id> can be:<pin_id><probe_id>

<color> is a <string constant><gauge> is an <integer><length> is a <numeric constant><probe_id> & <pin_id> are <stringexpressions>

Examples:WIRES

P23 to T56;11646 to TERMINAL;

10834P14 t

Table 5-24

Option

<probe_id>

<pin_id>

TERMINAL

<color>

<gauge>

<length>

© Agilent T 5-43

Chapter 5

s a <string expression>dx> are <numeric constants>

n be:

D

DRILLED;SOCKETED;-15;BLOCKED;OVERRIDE -10 20;

PINS options

Description

Name of the device-pin.

Specifies an offset, in tenth mils, used for personality pins that are bent to avoid probes on the board. The offset is added to the personality pin base location to get its actual fixture location.


: The Fixture Files

OtherThe OTHER keyword, when used in a protected unit, marks the beginning of a list of pins and wires that have not been associated with an external node.

OTHER syntax:OTHER


PinsThe PINS keyword, when used in conjunction with the OTHER keyword in a protected unit, marks the beginning of a list of reserved personality pins that have some attributes, or which have not been assigned to any external nodes. Because these pins are not assigned to a node, they can be re-claimed for other resource requests, even though they appear in the protected block, unless they are marked DRILLED or SOCKETED. Table 5-25 on page 5-43 describes Pins options.


PINS<pin_id>;<pin_id> <dy>;<pin_id> <status>;<pin_id> <status> <dy>;<pin_id> OVERRIDE <dy>;<pin_id> OVERRIDE <dy> <dx>;

<pin_id> i<dy> and <

<status> caDRILLEDSOCKETEBLOCKED

Examples:PINS

1345613457116081041712110

Table 5-25

Option

<pin_id>

<dy>

© Agilent T 5-44

Chapter 5

l node, in the node list of the protected unit. on page 5-45 describes Wires options.

8 WIRES syntax

nfo>;nfo>;

nfo>;

can be:> to <pin_id>> to TERMINALL to <pin_id>> to <pin_id> <color> <gauge>

> to TERMINAL <color> <gauge>

L to <pin_id> <color> <gauge>

s a <string expressions>a <string constant>an <integer>

s a <numeric constant>

to 20125 black 28 8.00;NAL to 14125 BLUE 28 5.00;


: The Fixture Files

WiresThe WIRES keyword, when used in conjunction with the OTHER keyword in a protected unit, marks the beginning of a list of wires that connect fixture components that are not on an external node. A wire can only be specified as connected from pin to pin or pin to terminal. If either of its ends connects to a component is an external node, the wire and its other end are moved to

that externaTable 5-26

Example 5-3

WIRES<wire_i<wire_i

. . .<wire_i

<wire_info><pin_id<pin_idTERMINA<pin_id

<length><pin_id

<length>TERMINA

<length><pin_id> i<color> is<gauge> is<length> i

Examples:WIRES

21325TERMI

<dx> Specifies an offset, in tenth mils, in the X direction. It is added to the X-coordinate of the personality pin's base location. Use this when specifying special personality pins with the OVERRIDE option.

DRILLED Refers to a location that has been drilled, but does not have a pin installed.

SOCKETED Refers to a location that has a personality pin installed.

BLOCKED Refers to a personality pin which cannot be used due to interference with a probe.

OVERRIDE Is used to mark a pin that would normally be BLOCKED.

Table 5-25 PINS options (continued)

Option Description

© Agilent T 5-45

Chapter 5

word identifies the end of the fixture file.

word has no parameters.


: The Fixture Files

End UnitMarks the end of the protected unit description block.

END UNIT syntax:END UNIT

The END UNIT keyword has no parameters.

EndThe END key

END syntax:END

The END key


Option Description

<pin_id> Pin that one end of the wire connects to. If pin_id to pin_id wiring is specified, both pins must only appear in the protected unit section.

TERMINAL One end of the wire is to be left unconnected in the wiring instructions. This open ended wire can later be used to connect to fixture electronics or some other custom application.

<color> Color of the wire, this is an arbitrary name of up to 20 characters.

© Agilent T 5-46

Chapter 5

Sampl

000 0,110000;


: The Fixture Files

e Fixture File Example 5-39 Sample fixture fileOPTIONS

Fixture Type CASSETTE;Fixture Size BANK1;Fixture Part Number 44201SEC;Top Probes Allowed ON;Density Threshold 500;Heavy Probe Force 8;Light Probe Force 4;Autofile 3078;Metric Units ON;WireWrapping MANUAL;

KEEPOUT BOTH !! Fixture keepout area65000, -2300070000, -2300070000, -1200065000, -12000;

BOARD SamplePLACEMENT 70362, -10198 90;OUTLINE0,0 150000,0 150000,120000 60000,120000 60000,110TOOLING3750 2000, 2000;3750 2000, 108000;KEEPOUT BOTTOM !! Board keepout area

20000, 2000040000, 2000040000, 4000020000, 40000;

NODE clock CRITICALPINS

11656;10834 OVERRIDE 25 -10;

© Agilent T 5-47

Chapter 5


: The Fixture Files

PROBESP12 34750, 84820 LWT;P23 16080, 12946 Y1.3 TOP;

ALTERNATES25820, 96740 U1.5;28820, 96740 U2.5 75MIL;31820, 96740 U3.5 50MIL;

TRANSFERST56 98700,38760;. . .

WIRESP23 to T56;11656 to T56;10834 to P12;

NODE VCCPOWER

1 5 8 MULTIPLEXED;2 5 8;!! Two supplies in parallel

PINS10101;10102;10103;

PROBESP121 98750, 76920;P122 84500, 67800;P123 94000, 12789;

ALTERNATES12320, 56780;23450, 67890;

WIRES10101 to P121;10102 to P122;10103 to P123;

© Agilent T 5-48

Chapter 5


: The Fixture Files

NODE +5BATTPINS

22377;PROBES

P814 48750, 36920;WIRES

12101 to P814 "Tw-pr" 28 1.00 G1;NODE 16.0MHZ

PINS22378;

PROBESP3 68750, 56920;

WIRES11101 to P3 "Tw-pr" 28 1.00 G1;

NODE U1-1PINS

22301;PROBES

P813 58750, 46920;WIRES

10201 to P813 Coax 28 1.00 G2;. . .

NODE U1-2PINS

22302;PROBES

P4 38750, 26920;WIRES

14201 to P4 Coax 28 1.00 G2;. . .

OTHER

© Agilent T 5-49

Chapter 5


: The Fixture Files

PINS13456 DRILLED;13457 SOCKETED;11608 -15;10417 BLOCKED;

PROBESP1 66970, 32670;P2 66800, 32500;P3 22520, 76920;P4 22400, 76800;P359 68970, 34670;P248 24520, 78920 TOP;

ALTERNATES92200, 85600 50MIL;

TRANSFERST57 10780, 34920 SOCKETED;90880, 65840;

WIRES10126 to 11326 black 28 8.00;. . .

GROUP G1 TWISTEDNODE "+5BATT"

PIN22377;

PROBEP814;

NODE "16.0MHZ"PIN

22378;PROBE

P3;. . .

GROUP G2 COAXNODE "U1-1"

PIN22301;

© Agilent T 5-50

Chapter 5


: The Fixture Files

PROBEP813;

NODE "U1-2"PIN

22302;PROBE

P4;END BOARD

END

© Agilent T 5-51

Chapter 5

Fixtur opy a standard template into a file named re_defaults in the board directory and y it for use with the specific board; or

anually create a file named re_defaults in the board directory.

8 fixture templates in the 3070_ROOT/standard/fixture/defaults/

amed after the type and size of fixture they ey include the following:

press_bank1press_bank2press_fullpress_dual_well_wire_bank1 _wire_bank2 _wire_full_wire_dual_wellsette_bank1sette_bank2T_bank1T_bank2T_fullT_dual_wellT_bank1T_bank2T_full


: The Fixture Files

e Defaults File The fixture defaults file is an optional file that provides a template to initialize the fixture object. This gives the test developer more control over fixture options; ensures the fixture object meets the requirements of the board being tested; and reduces the need for interactive fixture development.

Without a fixture defaults file, the development process initializes the fixture object by moving data and options into the fixture object from the .hp3070 file, the config object file, the board object file, and the board_xy object file. The test developer might add other information, such as fixture keepouts, by manually listing, editing and recompiling the initialized fixture file during an interactive development cycle. When a fixture defaults file is used, data from the usual sources will be ignored (except the .hp3070 file) and information in the fixture defaults object file is used instead.

The fixture defaults file is created and compiled before Test Consultant begins the automatic test generation process. The test developer

� may use an Agilent-supplied standard fixture defaults file template;

� may modify an Agilent-supplied standard template for general use;

� may cfixtu

modif

� may mfixtu

There are 1$AGILENTdirectory, nsupport. Th

� ex� ex� ex� ex� no� no� no� no� cas� cas� JO� JO� JO� JO� QP� QP� QP

© Agilent T 5-52

Chapter 5

Eize and type specified in any fixture default ust match what is in the board file. If they do atch, an error will be generated when the Placement program is executed.

defaults object file is not found as faults.o in the board directory or with the

me in the $AGILENT3070_ROOT/standard aults/, the fixture information from the other tory files will be used to initialize the fixture


: The Fixture Files

� QPT_dual_well

A fixture defaults file must be compiled before it can be used. Use the following BT-BASIC command to compile the file when in the standard/fixture/defaults subdirectory:

compile <template name>; defaults

CAUTION

✸When a <template name.o> is located in the $AGILENT3070_ROOT/standard/fixture

/defaults subdirectory, it will be used for all fixtures of that type, unless a local fixture_defaults.o file is found.

When a <boards>/<board name>/fixture_defaults

file exists, it must be compiled in the local board directory.

compile fixture_defaults; defaults

ADVICEFailure to compile the fixture defaults file will cause the software to ignore the optional fixture defaults files. This was done for backward compatibility.

ADVICThe sfile mnot mBoard

If a fixture fixture_de

required na/fixture/defboard direcobject.

© Agilent T 5-53

Chapter 5

SamplDefau

------------------, 2000 07:57:28 AM

------------------

he fixture compiler

ing a copy of the“fixture_defaults”using the command

fixture.


: The Fixture Files

e Fixture lts File

This section describes the syntax of the fixture defaults file.

Example 5-40 Fixture defaults (express_full) format

!!!! 13 0 1 971791024 0000!---------------------------------------------------------!FIXTURE DESCRIPTION LISTER Tue Oct 17!!express_full!---------------------------------------------------------

! To activate this fixture default file, compile it with t! using the default option. The BT-basic command is!! compile <fixture>; fixture,defaults!! You can override the global fixture default files by mak! applicable file and placing it in the board directory as! with the desired changes. You must then compile the file! above before the software will use it to initialize the!

!! Mandatory fields for a default file!OPTIONS

Fixture Type EXPRESS;Fixture Size FULL;Top Probes Allowed OFF;

© Agilent T 5-54

Chapter 5

e space for fixturere coordinatesigin. A typical

tead of using the

t: board_xy placement,n placement used by


: The Fixture Files

Density Threshold 104.0;Heavy Probe Force 8.0;Light Probe Force 4.0;Metric Units OFF;Wirewrapping AUTO;

!! Optional fields for a default file!!OPTIONS! Fixture Part Number! Autofile

! The customer may also include fixture keepouts to reserv! electronics or hardware. Fixture keepouts must use fixtu! which uses the left most fixture alignment pin as the or! example might be!KEEPOUT

200000, 15000200000, 35000240000, 35000240000, 15000;

!! New feature!! This allows you to define your own default placement ins! placement built into Board Placement.!! Precedence for using placements is from highest to lowes! the Default Placement noted below, and last, the built i! Board Placement.

© Agilent T 5-55

Chapter 5

ic Units specifies if metric units are to be n the fixture reports.

Wrapping describes the technology used to he fixture.

ptional fields include those settings that are are-generated and include the following:

re Part Number identifies the type of e. This number is automatically placed in the the software.

file specifies the identification number that dentifies the fixture. If you do not specify an le, Fixture Tooling will automatically assign ue one.

t - (Fixture) option specifies the area of the hich probes cannot be placed.

cement identifies where the board is placed on the overrides the built-in default placement for ment, but not the placement specified in the


: The Fixture Files

! Default Placement 30198, -77677 0.0;

END

The Options SectionsThe mandatory fields list the fixture settings that are translated to Board Consultant. Options include the following:

� Fixture Type refers to the type of fixture. Options include Cassette, Express, No-Wire,

QuickPress, and JOT.

� Fixture Size specifies the area of the testhead that the fixture will cover. Options include Dual_well, Full, Bank1, and Bank2.

� Fixture Handler identifies the fixture handling hardware. This option will not be present in the file if no fixture handler is used. Options include QPT (QuickPress) or JOT.

� Top Probes Allowed specifies if probes will be used for testing the top of the board.

� Density Threshold is the maximum amount of probe force allowed to probe the board.

� Heavy Probe Force specifies the force, in ounces, of the heavy weight probes.

� Light Probe Force specifies the force, in ounces, of the light weight probes.

� Metrused i

� Wirewire t

� The osoftw

� Fixtufixturfile by

� Autoauto-iautofia uniq

KeepoutThe Keepoufixture in w

Default PlaThis optionfixture, andboard placeboard_xy.

© Agilent T 5-56

Chapter 5


: The Fixture Files

Dividing LinesThe fixture defaults file can contain dividing lines to improve the readability of the file. A dividing line is defined to be:

� a blank line or� a line of dashes preceded by an exclamation point.

CommentsAny items preceded by an exclamation point are treated as a comment.

© Agilent T 5-57

Chapter 5

User-MFixturComp

The result of this is that nodal access is y allowing closer probe spacing.

s are available for determining the minimum ng. If the board config file does not specify anced fixturing, then the standard e) probe spacing algorithm will be used. If nfig file specifies enable advanced

the advanced (aggressive) probe spacing ill be used. Contact your fixture vendor to

can construct a fixture with the tighter e standard probe spacing and the advanced ng provided by the Agilent-supplied files are shown in the Table 5-27- Table end of this section. The algorithms for each ing are shown in Understanding Probe Chapter 3 of the Test and Fixture t documentation.

es, you will know before hand that special are needed. For example, if you are on-Agilent standard size probe, you know robes have different characteristics. Or, if

board that is physically too large for the ilent fixture kits, you can work with your or to define a custom oversize fixture for the ese situations, copy the appropriate fixture files to a specific sub-directory in the local tory and modify them as needed.


: The Fixture Files

odifiable e onents

The standard fixturing software in the Agilent3070 is well suited to the majority of boards being tested by the system. However, in some cases the standard parameters used to generate fixture build files may not be optimal. New probe types are being introduced to the test industry as loaded board technology advances. Fixture vendors are providing enhancements to fixture kits to suit the special needs of advanced users. Both of these trends have created requirements for more flexibility in defining fixtures and fixture components.

To meet this need, the Agilent3070 test system offers an advanced fixturing feature called User-Modifiable Fixture Components. This feature moves key attributes of fixture kits, probes and tooling pins into files that can be edited by the test developer to create custom fixturing applications.

The user-modifiable fixture and probes files, also called fixture component files, are files that define specific attributes of fixture kits, probes and tooling pins. The test developer may create custom versions of these files to redefine attributes as needed for particular applications.

Fixture component files are used to define oversize fixture kits and change the minimum spacing between probes. For example to use probes without sockets, you could modify the 100-, 75- and 50-mil component files with updated probe sizes, probe spacing and drilling

parameters.increased b

Two optionprobe spacienable adv

(conservativthe board cofixturing,algorithm wensure theyspacing. Thprobe spacicomponent 5-29 at the type of spacSpacing in Developmen

In most cascomponentstargeting a nthat all the pyou have a standard Agfixture vendboard. In thcomponent board direc

© Agilent T 5-58

Chapter 5

erms, the test developer will copy a standard ponent file for the component requiring n into the local board directory, and then edit hange one or more of the attributes. This is like copying a standard digital library to the directory and modifying it for use with this

Eobes on the fixture using a given modified file are affected. There is not a way to y a single probe�s attributes. However, if a probe has minimal usage, for example 50 robes, you could minimize the impact by ying that probe file.

g software will look in various defined o locate the needed fixture component files. are finds none in the local board directory, it standard files. Users may also change the es, but those changes will then apply to all eloped on that system when the advanced ature is enabled.

component files are modeled after the in structure, usage and file location.

component files may be copied from the 3070_ROOT/standard/fixture/components

y to alternate locations before Test


: The Fixture Files

In other cases, you may discover during test development that probe spacing is too close or that tooling pins are blocking resources. Correcting this requires the test developer to copy and modify the appropriate component files, then restart test development from the process step, described in Chapter 4, Generating Tests and Fixture Files in the Test and Fixture Development documentation.

CAUTION

✸You will need to remove the /<board name>/fixture directory before restarting the test development process.

CAUTION

✸You should consult with your fixture vendor before making any changes to fixture component files. Failure to do so could result in drill probe plates that cannot be populated with probes or may add significant costs to building the fixture.

NOTEThe fixture defaults and fixture/components must be defined during the Creating Board Information process, prior to generating tests and fixture files.

In general tfixture commodificatiothis file to cvery much local board board.

ADVICAll prprobemodifgivenMil pmodif

The fixturindirectories tIf the softwwill use thestandard filfixtures devfixturing fe

The fixture library files

The fixture $AGILENTsubdirector

© Agilent T 5-59

Chapter 5

$AGILENT3070_ROOT/standardure/components files are modified, those es will then apply to all fixtures developed t system when the advanced fixturing e is enabled in the board config file.

3 fixture components templates in the 3070_ROOT/standard/fixture/components/

amed after the type of fixturing component t. They include the following:

0MilLongProbe0MilProbeMilProbeMilProbeMilProbeolingPin200olingPin375pressBank1FixturepressBank2FixturepressFullFixture-WireBank1Fixture-WireBank2Fixture-WireFullFixture

essary to compile these files.


: The Fixture Files

Consultant begins the automatic test generation process. The test developer:

� may use Agilent-supplied component files;

� may modify Agilent-supplied component files for general use;

� may copy $AGILENT3070_ROOT /standard/components files into a board subdirectory called custom_fix and modify them for use with the specific board.

NOTEPlace the fixture component files in a board subdirectory called custom_fix to prevent them from being deleted with the fixture directory during iterative test development.

See Define the custom_fix Directory on page 3-8 in the Test and Fixture Development documentation for more information.

CAUTION

✸Component file names CANNOT be changed. Software errors will result. Only file contents can be modified.

CAUTION

✸If the/fixt

changon thafeatur

There are 1$AGILENTdirectory, nthey suppor

� 10� 10� 75� 50� 39� To� To� Ex� Ex� Ex� No� No� No

It is not nec

© Agilent T 5-60

Chapter 5

FixturCompSyntax

iameterMils - Diameter in thousandths of he clear space required for this probe. Used lect.

Drill - Size and style of drill for drilling ate.

teDrill - Size and style of drill for drilling plate.

eDrill - Size and style of drill for drilling plane (XG-50).

eShallowDrill - Size and style of drill for ground plane.

eClearance - Size and style of drill for ground plane.

le 5-41 on page 5-63 through Example 5-45 4 for default syntax.

Fixture Component Files Syntaxx fields defined in the fixture component ling pins:

elds are used by Fixture Tooling except noted.


: The Fixture Files

e onents Files

Probe Fixture Component Files SyntaxThere are ten fields defined in the fixture component files for probes:

NOTEAll fields are used by Fixture Tooling except where noted.

Name - Comment field - not used by the software (for compatibility with "special" software)

Usage - Describes how this probe type should be selected: Used by Probe Select.

� preferred - use this probe type if at all possible

� acceptable - use this probe type only as needed

� minimize - don't use this probe type unless absolutely necessary

� unavailable - do not use this probe type at all

WireWrapCount - Describes the number of wrapped wires that this probe can accommodate.

DiameterMils - Diameter in thousandths of an inch of the probe socket. Used by Probe Select.

CollisionD

an inch of tby Probe Se

ProbePlate

the probe pl

SupportPla

the support

GroundPlat

the ground

GroundPlat

drilling the

GroundPlat

drilling the

See Exampon page 5-6

Tooling Pin There are sifiles for too

NOTEAll fiwhere

© Agilent T 5-61

Chapter 5

left edge and 8.5275" up from the bottom of gilent3070 fixture.

ally, the probe plate size should be larger he maximum board size which should be than the probe area. However, the software OT check for these relationships.

MinX - The location of the left edge of the referenced to "fixture zero".

MaxX - The location of the right edge of the referenced to "fixture zero".

MinY - The location of the lower (front) probe plate referenced to "fixture zero".

MaxY - The location of the upper (top) edge plate referenced to "fixture zero".

- The maximum width of a board that will fit re (not referenced to fixture zero).

- The maximum height of a board that will xture (not referenced to fixture zero).

inX - The location of the left edge of the h probes can be placed in this fixture, o "fixture zero".


: The Fixture Files

Name - Comment field - not used by the software (for compatibility with "special" software)

DiameterMils - Diameter in thousandths of an inch of the pin. Used by Probe Select.

CollisionDiameterMils - Diameter in thousandths of an inch of the clear space required for this pin. Used by Probe Select.

ProbePlateHoleMils - Diameter in thousandths of an inch for probe plate hole.

ProbePlateDrill - Size and style of drill for drilling the probe plate

SupportPlateDrill - Size and style of drill for drilling the support plate

See Tooling Pin Fixture component defaults in Example 5-46 on page 5-64 and Example 5-47 on page 5-64.

Fixture Kit Component File SyntaxThere are ten fields defined in the fixture component files for fixture kits:

All fields are used by all fixturing software.

Note: Probe Plate and Probe Area dimensions are referenced to the "fixture zero" of a standard Agilent3070 fixture. Fixture zero should be thought of as a fixed location on the testhead. The dimensions describe the fixture dimensions in relation to that fixed location. For reference, fixture zero is 0.1889" to the

right of the a standard A

NOTELogicthan tlargerwill N

ProbePlate

probe plate

ProbePlate

probe plate

ProbePlate

edge of the

ProbePlate

of the probe

BoardMaxX on this fixtu

BoardMaxY fit on this fi

ProbeAreaM

area in whicreferenced t

© Agilent T 5-62

Chapter 5


: The Fixture Files

ProbeAreaMaxX - The location of the right edge of the area in which probes can be placed in this fixture, referenced to "fixture zero".

ProbeAreaMinY - The location of the lower edge of the area in which probes can be placed in this fixture, referenced to "fixture zero".

ProbeAreaMaxY - The location of the upper edge of the area in which probes can be placed in this fixture, referenced to "fixture zero".

See Example 5-48 on page 5-64 through Example 5-53 on page 5-65 for default syntax.

CommentsAny items preceded by an exclamation point are treated as a comment.

© Agilent T 5-63

Chapter 5

SamplComp

3 75MilProbe file

ilferredls: 52unt: 3iameterMils: 88Drill: 0.055in.,Long,FluteteDrill: 2.30mm,Long,FluteeDrill: 0.0625in,Std.,FluteeClearance: 0.080in,Std.,Flute

4 50MilProbe file

ilimizels: 36unt: 1iameterMils: 62Drill: 0.037in,Long,FluteteDrill: .043,in.,Std,FluteeDrill: 0.0625in,Std.,FluteeClearance: 0.080in,Std.,Flute


: The Fixture Files

e Fixture onents Files

This section describes the syntax of the fixture components files.

Example 5-41 100MilLongProbe file

Name: LONGUsage: preferredDiameterMils: 79WireWrapCount: 3CollisionDiameterMils: 121ProbePlateDrill: 2.10mm,Long,FluteSupportPlateDrill: 2.60mm,Std.,FluteGroundPlateDrill: 0.0625in,Std.,FluteGroundPlateClearance: 0.080in,Std.,Flute

Example 5-42 100MilProbe file

Name: 100 milUsage: preferredDiameterMils: 66WireWrapCount: 3CollisionDiameterMils: 104ProbePlateDrill: 1.75mm,Long,FluteSupportPlateDrill: 2.30mm,Long,FluteGroundPlateDrill: 0.0625in,Std.,FluteGroundPlateClearance: 0.080in,Std.,Flute

Example 5-4

Name: 75 mUsage: preDiameterMiWireWrapCoCollisionDProbePlateSupportPlaGroundPlatGroundPlat

Example 5-4

Name: 50 mUsage: minDiameterMiWireWrapCoCollisionDProbePlateSupportPlaGroundPlatGroundPlat

© Agilent T 5-64

Chapter 5

8 ExpressBank1Fixture file

MinX: -0.1889MaxX: 15.6611MinY: -8.5275MaxY: 9.472515.600017.7000

inX: 0.5611axX: 14.9111inY: -7.6430axY: 8.5870

9 ExpressBank2Fixture file


inX: 0.5611axX: 14.9111inY: -7.6430axY: 8.5870


: The Fixture Files

Example 5-45 39MilProbe file

Name: 39 milUsage: unavailableDiameterMils: 32WireWrapCount: 1CollisionDiameterMils: 46ProbePlateDrill: 0.0312in,Long,FluteSupportPlateDrill: .039,in.,Std,FluteGroundPlateDrill: 0.0625in,Std.,FluteGroundPlateClearance: 0.080in,Std.,Flute

Example 5-46 ToolingPin200 file

Name: ToolingDiameterMils: 200CollisionDiameterMils: 220ProbePlateDrill: 3.6mm,Long,FluteSupportPlateDrill: .125in.,Std,Flute

Example 5-47 ToolingPin375 file

Name: ToolingDiameterMils: 490CollisionDiameterMils: 500ProbePlateDrill: 0.25in.,Long,FluteSupportPlateDrill: 4.75mm,Std,Flute

Example 5-4

ProbePlateProbePlateProbePlateProbePlateBoardMaxX:BoardMaxY:ProbeAreaMProbeAreaMProbeAreaMProbeAreaM

Example 5-4


© Agilent T 5-65

Chapter 5

2 No-WireBank2Fixture file


inX: 0.3360axX: 15.1360inY: -7.9030axY: 8.8470

3 No-WireFullFixture file


inX: 1.1360axX: 28.5860inY: -7.9030axY: 8.8470


: The Fixture Files

Example 5-50 ExpressFullFixture file

ProbePlateMinX: -0.1889ProbePlateMaxX: 29.9111ProbePlateMinY: -8.5275ProbePlateMaxY: 9.4725BoardMaxX: 29.8000BoardMaxY: 17.7000ProbeAreaMinX: 0.5611ProbeAreaMaxX: 29.1611ProbeAreaMinY: -7.6430ProbeAreaMaxY: 8.5870

Example 5-51 No-WireBank1Fixture file

ProbePlateMinX: -0.1889ProbePlateMaxX: 15.6611ProbePlateMinY: -8.5275ProbePlateMaxY: 9.4725BoardMaxX: 15.6000BoardMaxY: 17.7000ProbeAreaMinX: 0.3360ProbeAreaMaxX: 15.1360ProbeAreaMinY: -7.9030ProbeAreaMaxY: 8.8470

Example 5-5


Example 5-5


© Agilent T 5-66

Chapter 5

StandAdvanSpacin

Mil 41.0 41.0

Mil 39.0 39.0

Probe to Tooling Pin Spacing

ng Pin size Standard Advanced

5� Tooling 291.0 289.5

375� Tooling 285.0 283.0

75� Tooling 278.0 276.0

75� Tooling 270.0 268.0

75� Tooling 270.0 266.0

0� Tooling 160.0 149.5

200� Tooling 152.5 143.0

00� Tooling 147.5 136.0

00� Tooling 127.5 128.0

00� Tooling 127.5 123.0

Probe to Probe Spacing

Standard Advanced


: The Fixture Files

ard and ced probe g

This section shows the probe to probe spacing, probe to tooling pin spacing and probe to personality pin spacing for standard fixturing and advanced fixturing as defined in the Agilent-supplied component files. All dimensions are center-to-center spacing and are in mils (0.001�).

Table 5-27 Probe to Probe Spacing

Probe Size Standard Advanced

Long 100-Mil to Long 100.0 100.0

100-Mil to Long 100-Mil 95.0 91.5

100-Mil to 100-Mil 85.0 85.0

75-Mil to Long 100-Mil 87.0 83.5

75-Mil to 100-Mil 80.0 77.0

75-Mil to 75-Mil 70.0 70.0

50-Mil to Long 100-Mil 80.0 70.5

50-Mil to 100-Mil 72.0 64.0

50-Mil to 75-Mil 66.0 57.0

50-Mil to 50-Mil 49.0 49.0

39-Mil to Long 100-Mil 62.5 62.5

39-Mil to 100-Mil 56.0 56.0

39-Mil to 75-Mil 49.0 49.0

39-Mil to 50-

39-Mil to 39-

Table 5-28

Probe/Tooli

Long to 0.37

100-Mil to 0.

75-Mil to 0.3

50-Mil to 0.3

39-Mil to 0.3

Long to 0.20

100-Mil to 0.

75-Mil to 0.2

50-Mil to 0.2

39-Mil to 0.2

Table 5-27

Probe Size

© Agilent T 5-67

Chapter 5


: The Fixture Files

Table 5-29 Probe to Personality Pin Spacing (These values can not be changed)

Probe Size to P-Pin Standard Advanced

Long 100-Mil 125.0 125.0

100-Mil 100.0 100.0

75-Mil 93.0 93.0

50-Mil 85.0 85.0

39-Mil 83.0 83.0

© Agilent T 6-1

In this teso prerequisites associated with using this

ools and Materialso required tools or materials associated with hapter.


6666 Log Record Format

chapter... � What are Log Records?, 6-2� About Log Record Prefixes, 6-3

� Hierarchy of Log Records, 6-9

� Interpreting the Log Records, 6-11

� How Log Records are Formatted, 6-16

� Descriptions of the Log Records, 6-18

This chapter describes the format of the standard log records generated by your test system for use by PR PLUS, and Pushbutton Q-STATS. Although an in-depth understanding of log records is not necessary for general users of your test system, it is essential for those who wish to integrate Agilent board test data with non-Agilent (custom) applications.


� Understand the structure and syntax of the log records

PrerequisiThere are nchapter.

Required TThere are nusing this c

© Agilent T 6-2

Chapter 6

What aRecor


: Log Record Format

re Log ds?

Test data is stored in files as a series of formatted records called log records. Each record consists of a character string which represents information. Because the records must be read and interpreted by programs, the characters in each record are arranged in precise formats. You must be familiar with these formats if you wish to interpret existing log records or generate your own from scratch.

NOTEBecause log records are simply strings of ASCII characters, you can load a log record file into the BT-BASIC workspace and examine it. Or, if you are familiar with the shell, you can examine log records with the more command or an editor such as vi. See Chapter 2, Datalogging in Information Management to determine where the log files are located.

© Agilent T 6-3

Chapter 6

AboutPrefix

ere can be any number of @BLOCK log erated, only one type of log record can begin OCK prefix.

are described in Table 6-1.

Generated by

capacitor

diode

fuse

inductor

jumper

measure

nfetr

npn

pfetr

pnp

potentiometer

resistor

switch


: Log Record Format

Log Record es

All standard log records generated by your test system contain a prefix that consists of the @ symbol followed by several descriptive characters that uniquely identify the type of record. For example, prefix @BLOCK indicates that the record describes a block, or group of tests.

Although threcords genwith an @BL

The records

Table 6-1 Log record prefixes

Prefix Purpose

@A-CAP capacitor test results

@A-DIO diode test results

@A-FUS fuse test results

@A-IND inductor test results

@A-JUM jumper test results

@A-MEA measurement results

@A-NFE N-channel FET test results

@A-NPN NPN transistor test results

@A-PFE P-channel FET test results

@A-PNP PNP transistor test results

@A-POT potentiometer test results

@A-RES resistor test results

@A-SWI switch test results

© Agilent T 6-4

Chapter 6

zener

alarm program

alarm program

digitizer

report analog

log board

test

test analog

Boundary-Scan

Boundary-Scan

Boundary-Scan

log board start

log board end

make diagnosis

make diagnosis

make diagnosis

make diagnosis

Generated by


: Log Record Format

@A-ZEN zener test results

@ALM identify a real-time alarm

@AID identify board causing an alarm

@ARRAY digitizer results analysis

@BATCH batch identifier

@BLOCK test block identifier

@BS-CON describe boundary-scan test

@BS-O list of open pins (boundary-scan)

@BS-S list of shorted pins (boundary-scan)

@BTEST describes board test

@BT-DIAG backtrace test results

@BT-FAULT list faults associated with fault syndrome

@BT-FD describe failing test when backtracing

@BT-NOD list nodes & test types

Table 6-1 Log record prefixes (continued)

Prefix Purpose

© Agilent T 6-5

Chapter 6

test

cont digital

probe

test

log is, log out, log failure, and other BT-BASIC logging functions

test

log level is indictments

log level is indictments

Generated by


: Log Record Format

@CCHK Connect Check test results

@DPIN list failing pins for one device

@D-PLD PLD programming results

@D-T digital shorts test results

@GRP group of related subrecords

@INDICT list potentially failing devices


Prefix Purpose

© Agilent T 6-6

Chapter 6

current

diode

fuse

jumper

measure

nfetr

npn

pfetr

pnp

switch

capacitor

inductor

potentiometer

resistor

zener

log level is failures

log level is all

Generated by


: Log Record Format

@LIM2 analog test high/low limits

@LIM3 analog test nom. & tol. limits

@M-CL status of a cluster test


Prefix Purpose

© Agilent T 6-7

Chapter 6

prsetup program

make diagnosis

probe

probe failures

test

pinsfailed

test

probe

prplus program

prplus program

log clear for retest

report

test

test

test shorts

test shorts

test shorts

Generated by


: Log Record Format

@NETV network verification record

@NODE list of nodes

@PCHK Polarity Check test results

@PIN list of pins

@PF pins failure results

@PRB probe failure results

@RACT describe a repair action

@REP describe a repair event

@RETEST indicates log clear for retest

@RPT messages logged by report

@S-PROC describes process in a serial test

@TJET TestJet test results

@TS shorts test results (destination)

@TS-D list of shorted nodes

@TS-O list of open nodes


Prefix Purpose

© Agilent T 6-8

Chapter 6

test shorts

test shorts

Generated by


: Log Record Format

Note that several groups of prefixes exist. For example, records beginning with @A- are generated by analog test statements, records beginning with @D- are generated by digital test statements, and so on. If you are generating custom log records, you may want to create your own prefix groups.

NOTETo keep log records to a manageable size, avoid making custom prefixes excessively long.

@TS-P list of phantoms

@TS-S shorts test results (source)


Prefix Purpose

© Agilent T 6-9

Chapter 6

HierarRecor

The results of the resistor test appear in an rd (which is preceded by an @BLOCK record

he beginning of a block of tests), like this:

-RES record appears as a subrecord of an rd, which is a subrecord of an @BTEST

ch is a subrecord of an @BATCH record.

structure of records and subrecords more will begin indenting the examples, like this:

TLOCK@A-RES

presenting examples clearly shows the f records and subrecords. Note that these for illustration purposes only; they do not in actual log data files.

test two more boards, each with one resistor data file now looks like this:

TLOCK@A-REST


: Log Record Format

chy of Log ds

This section shows how groups of log records are arranged to form log data files. To keep the examples simple, each record is represented by its prefix and not by the actual data it contains. The internal structure of each log record is explained later in Interpreting the Log Records on page 6-11.

Log records are arranged in a hierarchy of records and subrecords, where a subrecord is simply an additional record which further describes whatever precedes it. For example, a group of log records (presumably a log data file) might begin with an @BATCH record containing information to identify a batch of boards that were tested:@BATCH

And the @BATCH record might be followed by an @BTEST record to identify the testing of an individual board:

@BATCH@BTEST

Because the @BTEST record further describes the @BATCH record by identifying a unique board within the batch, it is a subrecord of�i.e., subordinate to�the @BATCH record. The @BATCH record by itself is incomplete; it becomes complete only when followed by an @BTEST record.

Suppose the board described in the @BTEST subrecord had a resistor test performed on it (by a resistor

statement). @A-RES recoto identify t

@BATCH@BTEST@BLOCK@A-RES

Thus, the @A@BLOCK recorecord, whi

To make theobvious, we

@BATCH@BTES

@B

This way ofhierarchy oindents are appear with

Suppose wetest. The log

@BATCH@BTES

@B

@BTES

© Agilent T 6-10

Chapter 6


: Log Record Format

@BLOCK@A-RES

@BTEST@BLOCK

@A-RES

Completing the current batch of boards and beginning a new one gives us:

@BATCH@BTEST

@BLOCK@A-RES

@BTEST@BLOCK

@A-RES@BTEST

@BLOCK@A-RES

@BATCH@BTEST

@BLOCK@A-RES

In a similar fashion, other records and subrecords can be assembled into files of log data describing how boards were tested.

© Agilent T 6-11

Chapter 6

InterpRecor

in the descriptions of the individual log s for the names of the fields associated with og record.

e the names of the fields with typical data, ecord might look like this:|1|1.246700E+01|C1}

optional, the separator character must still place holder. For example, if the @A-CAP e had no value assigned to the measured, it would look like this:|1||C1}

the vertical bars still reserve a space between of the test status and subtest fields for the empty measured value field.


: Log Record Format

reting the Log ds

Up until now, all of the examples have shown only the record prefixes, and not the test data each record contains. This section describes the format of data as it appears within log records and then expands upon the preceding section by showing how actual log records are grouped into log data files.

NOTEAlthough the following examples illustrate the structure of actual log records, the samples shown are not necessarily complete. Refer to the descriptions of the individual log records for complete details.

Each log record is enclosed in braces. The record begins with { immediately followed by the prefix, and ends with }. For example, the @A-CAP record, which describes a capacitor test, looks like this when simplified:

{@A-CAP. . . data fields . . .}

The prefix is followed by one or more variable length data fields containing descriptive information. A vertical bar, |, is used as a separator between fields. Adding the names of the fields to the example above gives us:

{@A-CAP|test status|measured value|subtestdesignator}

NOTELookrecordeach l

If we replacan @A-CAP r

{@A-CAP

If a field is appear as a record abovvalue field

{@A-CAP

Notice that the contentsdesignator

© Agilent T 6-12

Chapter 6

node list|item 1|item 2| . . etc.}

values in place of the field names gives us:2|Node53|+5Volts}

try in a list tells how many items appear in s, the 2 following the \ indicates there are the list: Node53 and +5Volts.

cords are followed by one or more containing additional information. For e @PF record can be followed by an @PIN h contains a list of pins:

\2|11434|22216}

se value (0 or N)

decimal point and any number of consecutive and an integer

ed by one or more consecutive digits

ss otherwise noted)


: Log Record Format

Each field must contain a certain type of information. The log record descriptions denote these beneath TYPE as shown in Table 6-2.

If left empty, most fields default to some predefined value. The log record descriptions denote these beneath DEFAULT as:

� 0, 1, etc. a default numeric value

� "" a null string

Fields for which a default value would be meaningless�that is, fields in which a reported value is mandatory�have a question mark (?) beneath DEFAULT.

Some log records contain a data list. In this case, the initial separator character (to indicate that a list follows) is a backslash, \, and individual items within the list are separated by a vertical bar. For example, the @NODE log record contains a list of node identifiers:

{@NODE\

Substituting{@NODE\

The first enthe list. Thutwo items in

Some log resubrecords example, threcord whic

{@PF|2{@PIN

}

Table 6-2 Log record types

Type Description

bool a boolean, which can have either a true value (1 or Y) or a fal

fp floating point number, which is an integer optionally followed by adigits, all optionally followed by the letter E (upper- or lowercase)

int integer number, which is an optional sign character (+ or -) follow

str string value, which is any number of characters of any type (unle

© Agilent T 6-13

Chapter 6

O|Node43|Node14|-1.500000E+00}S|0|1|Node38TS-P|-1.243853E+02}

an overall @TS log record contains three one each to report shorts, opens, and ssociated with the shorts test reported by the og record. Two of the @TS record's contain subrecords which further describe e the pairing of braces; for each opening is a closing brace.

ave mentioned four special characters which in log records: {, }, |, and \. But suppose more of these characters must appear within and not be interpreted as data field

nother special character, the tilde (~), is tify a data field that should be interpreted e., a literal field. Unlike a normal field, riable length, this literal field must have its sely defined. For example:(test)|!|

ata in this field is !$%(test)|!|. The ~ e field as a special case, the 12 denotes the h as twelve characters, and the | following the 12 delimits the length

n from the data.


: Log Record Format

In other words, the @PF record is further described by the @PIN record that follows it.

Notice the hierarchy of braces�i.e., the @PIN record has its own pair of beginning and ending braces ({ and }) within the @PF record's overall pair of braces. Also notice that the closing brace for the @PF record was dropped onto a new line, and the @PIN record was indented, to make the structure of the overall record more obvious. Indents and new lines are shown here for illustration purposes only; they do not necessarily appear within actual log data files.

If you examine actual log data produced by an Agilent 3070 system, you will see that in some cases subrecords appear on the same line as the records with which they are associated, and in other cases they do not. The important thing to keep in mind is that log records must appear in the correct order and that they must be accurately defined by braces.

Without the indents and new lines, the actual log record looks like this:

{@PF|2{@PIN\2|11434|22216}}

This same hierarchy of braces and indents also applies to more complex, nested groups of log records. Consider the following example:

{@TS|1|2|1|1|{@TS-S|2|0|Node12

{@TS-D|Node25|1.678850E+00}{@TS-D|Node26|2.543211E+00}

}{@TS-{@TS-

{@}

}

In this casesubrecords,phantoms aentire @TS lsubrecords them. Noticbrace, there

So far we hcan appear that one or a data field delimiters. Aused to idenliterally�i.which is valength preci

~12|!$%

The actual didentifies thfield's lengtimmediatelyspecificatio

© Agilent T 6-14

Chapter 6

xception to this is that the truncation cter can appear in a literal field denoted with (~); this does not indicate a truncated .

eceding the truncation character is to be valid, and any subsequent log records idered normal provided they do not contain

on character.

out Process Stepsto type and serial number, boards can be y a process step. The process step is simply p in the manufacturing process�for -circuit or functional�the board is being @BATCH log record contains a process step which you can place a brief code to identify p in the test process a board was tested.

ushbutton Q-STATS does not make use of s. However, if you are generating custom and ever expect to use the optional quality management software (which does steps), you may want to begin acquiring information now.


: Log Record Format

If this field appeared in a log record, it might look like this:

{@RPT~12|!$%(test)|!|}

Notice that the ~ at the beginning of the literal field replaces the usual | delimiter; do not use both delimiters.

If you generate custom log records containing the line feed character, an ASCII 10 (CTRL-J), you must put the line feed character in a literal field; if you do not, it will be misinterpreted as an optional delimiter between a record and a subrecord.

If you need to manipulate log records with BT-BASIC, you should use free-field formatting to input a record's individual fields into variables.

NOTENote that this is different from how 3065 log records are handled in an imaged format.

A Note About Truncated RecordsIf you are using custom datalogging routines, be aware that the presence of a truncation character, an ASCII 4 (CTRL-D), in the data will be interpreted to mean that the log data was unexpectedly interrupted and that the current log record has ended.

NOTEThe echaraa tilderecord

The data prconsidered will be consthe truncati

A Note AbIn addition identified bat which steexample, intested. The data field inat which ste

Note that Pprocess steplog records Q-STATS IIuse processprocess step

© Agilent T 6-15

Chapter 6


: Log Record Format

A Note About User-Defined Log RecordsThe log and log using statements allow you to create user-defined log records in free-field and imaged formats, respectively. User-defined log records can emulate existing log records, or they can be created from scratch for custom applications (which require custom routines to process the non-standard log records).

© Agilent T 6-16

Chapter 6

How Lare Fo

ustom log records or custom datalogging sure that none of these characters appear in unless they are within a literal field.

ormattingng list contains the formatting rules used to cords (or subrecords).

log record begins with { followed by a series ntable characters that uniquely identify the cord type. The convention for log record supplied by Agilent is that they begin with other log records should begin with this cter.

Identifies a truncated (incomplete) log record

Line feed character (new line). Denotes the end of the data fields for the current record, and should only be followed by an end of record character (}) or beginning of a new record or subrecord ({).

Special characters (continued)

Description


: Log Record Format

og Records rmatted

The next two topics summarize how log records are formatted. These topics are useful if you are creating your own custom log records.

Special CharactersThe characters shown in Table 6-3 that have special significance�that is, they are interpreted to mean something other than their normal ASCII value�when they appear in a log record.

If you use croutines, benormal data

Rules of FThe followibuild log re

� Each of prilog retypes@. Nochara

Table 6-3 Special characters

Character Description

{ Begins a log record

} Ends a log record

| Begins a normal data field

~ Begins a literal field

\ Begins a list of fields

ASCII 4 (CTRL-D)

ASCII 10 (CTRL-J)

Table 6-3

Character

© Agilent T 6-17

Chapter 6

e characters which are to be interpreted rally

log record ends with }

record types can contain nested subrecords. ord becomes a subrecord when it occurs he preceding record's data fields but before al } for the preceding record.


: Log Record Format

� The record type is followed by one or more data fields.

� Each data field begins with one of the following characters:

| � Begins a normal data field, which must not contain special characters unless they appear within a literal field. A normal data field is ended by the appearance of the next special character. If you are creating custom log records: Since a special character ends a data field, every data field should be followed by some special character to terminate it.

\ � Begins a data field that contains a list, which must not contain any special characters unless they appear within a literal field. This character is followed by:

� A number showing how many items are in the list

� The items (data) in the list. Each item is itself a data field, and usually begins with |.

~ � Begins a literal field, which is the only way to include special characters inside a log record and not have them interpreted as special. This character is followed by:

� A number showing how many characters are in the field

� A single |

� Thlite

� Each

� SomeA recafter tthe fin

© Agilent T 6-18

Chapter 6

DescrLog R

1.246700E+01}

or parameter of the capacitor statement


: Log Record Format

iptions of the ecords

Record @A-CAP: capacitorThis record describes a capacitor test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: capacitor statement

� Subrecords: @LIM3 is generated when logging limits information. Contains nominal value and high/low limits for test.

� Corresponds to: 12 record on a 3065 system.

Example 6-1

{@A-CAP|1|

Table 6-4 @A-CAP

Format: {@A-CAP|test status|measured value|subtest designator}

Field Type Default Comments

test status int 0 0 = passed1 = failed2 = failed (compliance limit)3 = failed (detector timeout)11 = aborted by operator

measured value fp 0 The actual value measured.

subtest designator

str "" Comes from the optional designat

© Agilent T 6-19

Chapter 6

|1|1.246700E+01}

gnator parameter of the diode statement.


: Log Record Format

Record @A-DIO: diodeThis record describes a diode test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: diode statement

� Subrecords: @LIM2 is generated when logging limits information. Contains high/low limits for test.


Example 6-2

{@A-DIO

Table 6-5 @A-DIO

Format: {@A-DIO|test status|measured value|subtest designator}




subtest designator str "" Comes from the optional desi

© Agilent T 6-20

Chapter 6

gnator parameter of the fuse statement.


: Log Record Format

Record @A-FUS: fuseThis record describes a fuse test. When limits are being logged, it is followed by a subrecord containing additional information.


Example 6-3

{@A-FUS|1|1.246700E+01}

Table 6-6 @A-FUS

Format: {@A-FUS|test status|measured value|subtest designator}





© Agilent T 6-21

Chapter 6

|1|1.246700E+01}

gnator parameter of the inductor


: Log Record Format

Record @A-IND: inductorThis record describes an inductor test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: inductor statement



Example 6-4

{@A-IND

Table 6-7 @A-IND

Format: {@A-IND|test status|measured value|subtest designator}




subtest designator str "" Comes from the optional desistatement.

© Agilent T 6-22

Chapter 6

gnator parameter of the jumper statement.


: Log Record Format

Record @A-JUM: jumperThis record describes a jumper test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: jumper statement


Example 6-5

{@A-JUM|1|1.246700E+01}

Table 6-8 @A-JUM

Format: {@A-JUM|test status|measured value|subtest designator}





© Agilent T 6-23

Chapter 6

|1|1.246700E+01}

btest block in which the measurement


: Log Record Format

Record @A-MEA: measureThis record describes a measurement. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: measure statement



Example 6-6

{@A-MEA

Table 6-9 @A-MEA

Format: {@A-MEA|test status|measured value|subtest designator}




subtest designator str "" Comes from the name of the suoccurred.

© Agilent T 6-24

Chapter 6

|1|1.246700E+01}

gnator parameter of the nfetr statement.


: Log Record Format

Record @A-NFE: nfetrThis record describes an N-channel FET test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: nfetr statement



Example 6-7

{@A-NFE

Table 6-10 @A-NFE

Format: {@A-NFE|test status|measured value|subtest designator}





© Agilent T 6-25

Chapter 6

|1|1.246700E+01}

gnator parameter of the npn statement.


: Log Record Format

Record @A-NPN: npnThis record describes an NPN transistor test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: npn statement



Example 6-8

{@A-NPN

Table 6-11 @A-NPN

Format: {@A-NPN|test status|measured value|subtest designator}





© Agilent T 6-26

Chapter 6

|1|1.246700E+01}

gnator parameter of the pfetr statement.


: Log Record Format

Record @A-PFE: pfetrThis record describes a P-channel FET test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: pfetr statement



Example 6-9

{@A-PFE

Table 6-12 @A-PFE

Format: {@A-PFE|test status|measured value|subtest designator}





© Agilent T 6-27

Chapter 6

0

|1|1.246700E+01}

gnator parameter of the pnp statement.


: Log Record Format

Record @A-PNP: pnpThis record describes a PNP transistor test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: pnp statement



Example 6-1

{@A-PNP

Table 6-13 @A-PNP

Format: {@A-PNP|test status|measured value|subtest designator}





© Agilent T 6-28

Chapter 6

1

|1|1.246700E+01}

gnator parameter of the potentiometer


: Log Record Format

Record @A-POT: potentiometerThis record describes a potentiometer test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: potentiometer statement



Example 6-1

{@A-POT

Table 6-14 @A-POT

Format: {@A-POT|test status|measured value|subtest designator}





© Agilent T 6-29

Chapter 6

2

|1|1.246700E+01}

gnator parameter of the resistor


: Log Record Format

Record @A-RES: resistorThis record describes a resistor test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: resistor statement



Example 6-1

{@A-RES

Table 6-15 @A-RES

Format: {@A-RES|test status|measured value|subtest designator}





© Agilent T 6-30

Chapter 6

gnator parameter of the switch statement.


: Log Record Format

Record @A-SWI: switchThis record describes a switch test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: switch statement


Example 6-13

{@A-SWI|1|1.246700E+01}

Table 6-16 @A-SWI

Format: {@A-SWI|test status|measured value|subtest designator}





© Agilent T 6-31

Chapter 6

4

|1|1.246700E+01}

gnator parameter of the zener statement.


: Log Record Format

Record @A-ZEN: zenerThis record describes a Zener diode test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: zener statement



Example 6-1

{@A-ZEN

Table 6-17 @A-ZEN

Format: {@A-ZEN|test status|measured value|subtest designator}





© Agilent T 6-32

Chapter 6

MDDHHMMSS format (datetime$).

e board that caused the real-time alarm.


: Log Record Format

Record @AID: identify board causing real-time alarmThis record appears as a subrecord of the @ALM record; it identifies the board that caused the real-time alarm described in the @ALM record.

� Generated by: alarm program

� Corresponds to: A2 record on a 3065 system that has PR PLUS installed.

Example 6-15

{@AID|890615094418|12306743}

Table 6-18 @AID

Format: {@AID|time detected|serial number}


datetime detected str "" Date and time of alarm in YYM

subtest designator str "" The unique serial number of th

© Agilent T 6-33

Chapter 6

cords: @AID Logged for any real-time alarm detected; identifies the board that caused al-time alarm.

ype rev|alarm limit|detected

ple yield; 3 = overall yield

MDDHHMMSS format (datetime$).

the alarm.

ssociated with the alarm.

was exceeded.

ed the alarm limit.

rred on.


: Log Record Format

Record @ALM: identify real-time alarmThis record describes a specific real-time alarm. It is followed by an @AID subrecord that identifies which board caused the real-time alarm.

� Generated by: alarm program � Subrethat isthe re

Table 6-19 @ALM

Format: {@ALM|alarm type|alarm status|time detected|board type|board tvalue|controller|testhead number}


alarm type int 1 1 = consecutive failure; 2 = sam

alarm status bool 0 0 = off, 1 = on

datetime detected str "" Date and time of alarm in YYM

board type str "" The board type associated with

board type rev str "" The revision of the board type a

alarm limit int ? The alarm limit (threshold) that

detected value int ? The detected value that exceed

controller str "" Which controller the alarm occu

testhead number int 1 (th$) a positive integer.

© Agilent T 6-34

Chapter 6

the optional designator parameter of the


: Log Record Format

� Corresponds to: A1 record on an 3065 system that has PR PLUS installed.

Example 6-16

{@ALM|1|1|890516145512|proc_bd|2|10|15|alpha|1}

Record @ARRAY: digitizer results analysisThis record describes the results of a measure statement for the digitizer or the results of an array-format reportanalog statement.

Table 6-20 @ARRAY

Format: {@ARRAY|subtest designator|status|failure count|samples}


subtest designator str "" Comes from the digitizer or fromreport analog statement.

status int 0 0 = pass1 = fail7 = error occurred

failure count int 0 The number of failures.

samples int 1024 The number of samples tested.

© Agilent T 6-35

Chapter 6

ATCH: identify a batch of boards identifies a unique batch of boards; i.e., a oards which are treated as a group for test

head type|process step|batch id|operator ev}

ot including the revision. This can be a board

nel type revision.

is currently not used.)

ring process.

.


: Log Record Format

� Generated by: digitizer, report analog statement

Example 6-17

{@ARRAY|""|1|5|1024}

Record @BThis recordnumber of bpurposes.

Table 6-21 @BATCH

Format: {@BATCH|UUT type|UUT type rev|fixture id|testhead number|testid|controller|testplan id|testplan rev|parent panel type|parent panel type r


UUT type str "" The type of unit under test, ntype or a panel type.

UUT type rev str "" The board type revision or pa

fixture id int 0 The decimal autofile code.


testhead type str "" Which type of testhead. (This

process step str "" Which step in the manufactu

batch id str "" ID of current batch of boards

operator id str "" Which operator.

controller str "" Which controller.

testplan id str "" Name of testplan.

© Agilent T 6-36

Chapter 6

ord which in turn has only one @BTEST record.

her The log and log using statements can used to generate other subrecords.

sponds to: 01 and 04 records on an 3065 .

les|MaxWellBT|7|A_panel|2}

s this board.

that contains this board.

head type|process step|batch id|operator ev}


: Log Record Format

� Generated by: log board statement

� Subrecords:

� @BTEST Generated for each board within a batch. When one log data file is generated per board tested, the file has only one @BATCH

recsub

� ot

be

� Corresystem

Example 6-18

{@BATCH|998457-146|0|2550|1||btest|891131172938|pete|achil

testplan rev str "" Revision of testplan.

parent panel type str "" Type of the panel that contain

parent panel type rev str "" Revision of the type of panel

version label str "" Multiple Board version.

Table 6-21 @BATCH (continued)

Format: {@BATCH|UUT type|UUT type rev|fixture id|testhead number|testid|controller|testplan id|testplan rev|parent panel type|parent panel type r


© Agilent T 6-37

Chapter 6

BLOCK subrecords

Generated by

capacitor statement

diode statement

fuse statement

inductor statement

jumper statement

measure statement

nfetr statement

npn statement

pfetr statement

pnp statement

potentiometer statement

resistor statement

Generated by switch statement

zener statement

test statement


: Log Record Format

Record @BLOCK: identify a test blockThis record identifies a named block of analog, digital, serial, or mixed test statements.

� Generated by: test, test analog statements

� Subrecords: Subrecords are shown in Table 6-23.

Example 6-19

{@BLOCK|R12|1{@A-RES||1|1.006789E+01}

}

.

Table 6-22 @BLOCK

Format: {@BLOCK|block designator|block status}


block designator

str "" Name of this test block.

block status

int 0 0 = all statements passed. If a statement failed, the status of the failing test is shown.

Table 6-23

Subrecord

@A-CAP

@A-DIO

@A-FUS

@A-IND

@A-JUM

@A-MEA

@A-NFE

@A-NPN

@A-PFE

@A-PNP

@A-POT

@A-RES

@A-SWI

@A-ZEN

@D-T

© Agilent T 6-38

Chapter 6

rated by: Boundary-Scan Software

cords:

S-O is generated when opens count is ater than zero and the log level is not set to thout pins.

S-S is generated when shorts count is ater than zero and the log level is not set to thout pins.

0

N|9c_connect|1|0|2O|9C|43}O|9C|41|9C|58}

N|27c_connect|1|0|1S|S{@NODE\2|179|112}}


: Log Record Format

� Gene

� Subre

� @B

grewi

� @B

grewi

Example 6-2

{@BS-CO{@BS-{@BS-

}{@BS-CO

{@BS-}

@S-PROC test statement

@TJET test statement

Table 6-24 @BS-CON

Format: {@BS-CON|test designator|status|shorts count|opens count}


test designator

str "" Designator for a boundary-scan connect or interconnect test.

status int 0 0 = pass1 = fail7 = chain failure

shorts count

int 0 How many shorts occurred during the boundary-scan test.

opens count

int 0 How many opens occurred during the boundary-scan test.

Table 6-23 BLOCK subrecords (continued)

Subrecord Generated by

© Agilent T 6-39

Chapter 6

device.

device.

n the second device.


: Log Record Format

Record @BS-O: list of open pinsThis subrecord follows a @BS-CON log record and further describes that record by listing open pins that were found during a failing boundary-scan test.

� Generated by: Boundary-Scan Software

Example 6-21

{@BS-O|9C|43}{@BS-O|9C|41|9C|58}

Table 6-25 @BS-O

Format: {@BS-O|first device|first pin|second device|second pin}


first device name str "" Name of the first device.

first device pin int 1 Number of open pin on the first

second device name

str "" (optional) Name of the second

second device pin int 1 (optional) Number of open pin o

© Agilent T 6-40

Chapter 6


: Log Record Format

Record @BS-S: list of shorted pinsThis subrecord follows an @BS-CON log record and further describes that record by listing a shorted pin that was found during a failing boundary-scan test.

� Generated by: Boundary-Scan Software

Example 6-22

{@BS-S|S{@NODE\2|179|112}}

Table 6-26 @BS-S

Format: {@BS-S|cause|node list}


cause str S S = known shortU = unknown short0 = stuck at 01 = stuck at

node list str "" A list of indicted nodes.

© Agilent T 6-41

Chapter 6

t|log level|log set|learning|known good|end


: Log Record Format

Record @BTEST: describe a board testThis record describes the overall testing of a single board. It is followed by subrecords which report the results of individual tests performed on the board.

Table 6-27 @BTEST

Format: {@BTEST|board id|test status|start datetime|duration|multiple tesdatetime|status qualifier|board number|parent panel id}


board id str "" Serial number of this board.

test status int 0 0 = passed1 = uncategorized failure2 = failed pin test3 = failed in learn mode4 = failed shorts test5 = (reserved)6 = failed analog test7 = failed power supply test8 = failed digital or boundary scan test9 = failed functional test10 = failed pre-shorts test11 = failed in board handler

© Agilent T 6-42

Chapter 6

or missing) : maintained, but not logged.

SS format (datetime$).

? 0 = NO, 1 = YES

t currently used.)



: Log Record Format

12 = failed barcode13 = X�d out (board on panel not tested14 = failed in TestJet15 = failed in polarity check16 = failed in ConnectCheck17 = failed in analog cluster test18-79 = reserved80 = runtime error81 = aborted (STOP)82 = aborted (BREAK)83-89 = reserved90-99 = user-definable

start datetime int 0 Start of board test in YYMMDDHHMM

duration int 0 Test duration in seconds.

multiple test bool 0 Is this the same as the previous board

log level str "" Current value of lli$.

log set int 0 Current default logging set. (This is no

Table 6-27 @BTEST (continued)



© Agilent T 6-43

Chapter 6

rated by:

g board start statement begins this ord.g board end statement ends this record.

sponds to: 02 and 03 records on a 3065 .

utton Q-STATS and Q-STATS II interpret a atus of 1 through 10 as a failing board, while

= YES

S format (datetime$).

d.

as determined by a board number is buffers (board number is *), this value is zero.

ntPanelId> parameter of a log board



: Log Record Format

NOTEThe test status constants (above) are defined in the test plan, and are used by statistical analysis and quality control programs such as PushButton QStats and other packages. These tools respond primarily to the category of PASS/FAIL/BOGUS, though they do sometimes recognize that the value 2 is special. Pins test failure can be a bad board, or a problem with the fixture.

� Gene

� lo

rec� lo

� Corresystem

Pushbtest st

learning bool 0 Is learning on? N = NO, Y = YES

known good bool 0 Is this a known good board? N = NO, Y

end datetime int 0 End of board test in YYMMDDHHMMS

status qualifier str "" Comment string from log board en

board number int 1 The number of the board being tested,statement. When not using multiple logreported as 1 even though it is actually

parent panel id str "" Value derived from the optional <Parestart statement.

Table 6-27 @BTEST (continued)

© Agilent T 6-44

Chapter 6

172938|4|99538-130

ALOG), report (BT-BASIC), or report


: Log Record Format

values 11 through 99 are considered bogus; i.e., they are neither passing nor failing.

Example 6-23

{@BTEST|99538-135|8|891131172855|43|0|failures||n|n|891131. . .

{test results subrecords}. . .

}

Subrecords:

Table 6-28 BTEST subrecords


@BLOCK test and test analog statements

@BS-CON Boundary-Scan connect and interconnect tests

@BT-DIAG make diagnosis statement

@D-LOG log digital statement

@D-T test statement

@PF pinsfailed function

@PRB probe or probe failures statements

@RETEST log clear for retest statement

@RPT any of the report statements; i.e., report (AN

(SHORTS)

© Agilent T 6-45

Chapter 6

d to generate other subrecords


: Log Record Format

Record @BT-DIAG: results of a backtrace testThis record describes how a backtrace test terminated; i.e., whether the last failing node was found, a feedback loop was detected, an open trace was detected, etc. It is followed by a subrecord when the number of nodes in diagnosis (the node count field) is greater than zero.

@TS test shorts statement

other The log and log using statements can be use

Table 6-28 BTEST subrecords (continued)


© Agilent T 6-46

Chapter 6

unt|log point failed vector count|node

tatus)atus)

unter) of backtrace test. 0 = indeterminate.

unter) at log point�i.e., diagnosis. 0 =


: Log Record Format

Table 6-29 @BT-DIAG

Format: {@BT-DIAG|diagnosis|abort substatus|backtrace failed vector cocount|test name|test qualifier}


diagnosis int 1 1 = last failing node2 = feedback loop4 = untestable area8 = open trace9 = aborted by operator10 = abort on node (see abort subs

12 = abort on test (see abort subst

abort substatus int 0 0 = passed (test/reset node)1 = intermittent2 = SAFEGUARD timeout4 = hardware error8 = software timeout

backtrace failed vector count

int 0 Failed vector count (value of vector co

log point failed vector count

int 0 Failed vector count (value of vector coindeterminate.

© Agilent T 6-47

Chapter 6

sponds to: C2 record on an 3065 system.

0, @BT-NOD subrecord must have a list with 2 h node. If = 0, no subrecord is needed.

me).

unt|log point failed vector count|node


: Log Record Format

� Generated by: make diagnosis statement

� Subrecords: @BT-NOD When node count is not zero, there will be one @BT-NOD subrecord listing each node and its test method.

� Corre

Example 6-24

{@BT-DIAG|||3|4|1|functional/HiPassFilter/test|.2}

Record @BT-FAULT: list of predicted faultsThis record is produced when the backtracing statement make diagnosis is executed and the diagnosis is made

node count int 0 How many nodes are in diagnosis. If > X node count items�i.e., a pair for eac

test name str "" Backtrace test designator (directory na

test qualifier str "" Backtrace test designator qualifier.

Table 6-29 @BT-DIAG (continued)

Format: {@BT-DIAG|diagnosis|abort substatus|backtrace failed vector cocount|test name|test qualifier}


© Agilent T 6-48

Chapter 6

T-FD: identify failing test & describe

is produced when the backtracing statement osis is executed and the diagnosis is made the fault dictionary. It describes the failing

fault data associated with the fault hen the number of failing nodes is greater

is record is followed by a subrecord that

e either a pin number or INTERNAL.

dictionary data.

ed


: Log Record Format

from data in the fault dictionary. It lists the predicted faults associated with the fault syndrome in the fault dictionary.


Example 6-25

{@BT-FAULT|u4|7|SA0|0|HARD}{@BT-FAULT|u6|INTERNAL|SA1|48|POSS}

Record @Bfault dataThis recordmake diagn

from data intest and thesyndrome. Wthan zero, th

Table 6-30 @BT-FAULT

Format: {@BT-FAULT|device|pin number|fault class|fault score|fault type}


device str "" Name of the faulty device.

pin number str "" Number of the faulty pin. Can b

fault class str "" SA0 = stuck at 0SA1 = stuck at 1

fault score int 0 Degree of match with the fault

fault type str "" HARD = hard failure detectedPOSS = possible failure detect

© Agilent T 6-49

Chapter 6

E|CARRYOUT}@BT-FAULT records

syndrome.

his syndrome were found in the fault dictionary.


: Log Record Format

indicates which output nodes failed in the fault syndrome used to access the fault dictionary.

� Subrecords:

� @BT-FAULT: Lists the predicted faults associated with the fault syndrome in the fault dictionary.

� @NODE: When node count is not zero, there will be one @NODE subrecord that further describes the @BT-FD record preceding it for each failed node in the fault syndrome.

Example 6-26

{@BT-FD|cluster_a|239|4|7{@NODE|OUT1}{@NODE|OUT2}{@NODE|OUT3}

{@NOD. . .

}

Table 6-31 @BT-FD

Format: {@BT-FD|test designator|failing vector|node count|fault count}


test designator str "" Designator of failing test.

failing vector int 0 Number of failing vector.

node count int 0 How many nodes failed in this

fault count int 0 How many predicted faults for t

© Agilent T 6-50

Chapter 6

to provide two separate items of information

ame strings. Following them (even items) llows:

st

will be twice the number of nodes�i.e., two


: Log Record Format

Record @BT-NOD: list of nodes and their test typesThis record describes how backtraced nodes were tested. It contains a list of nodes and tells how they were tested.

Table 6-32 @BT-NOD

Format: {@BT-NOD|probed node list}


probed node list str/int ""/0 The entries in this list alternateabout each node.

The odd items are the node nare the test type items, as fo

1 external (user-supplied) te

2 SR using module pin

3 SR using manual probe

4 CRC using module pin

8 non-testable (notest)

12 not checked/traced

The number of items in the list items per node.

© Agilent T 6-51

Chapter 6

(non-testable)


: Log Record Format


� Subrecords: none

� Corresponds to: C3 record on a 3065 system.

Example 6-27

! Two nodes were probed: Node17 and GND. Node17 was type 8! and GND was type 3 (SR using manual probe)

{@BT-NOD\2|Node17|8|GND|3}

Record @CCHK: Connect Check TestThis record that describes the results of Connect Check tests.

Table 6-33 @CCHK

Format: {@CCHK|test status|pin count|test designator}


test status int 00 00 = pass01 = fail07 = fatal error

pin count int 0000 number of failing pins

device designator str ""

© Agilent T 6-52

Chapter 6

PIN: list of device pins for a single

contains a list of device pins for a single

pin list|thru devnode list} with DriveThru

device name is not available.

eparate items of information about each pin. Following them (even items) are the optional ns of this device are connected to the node whenever possible. The number of list items er of device pins.

d nodes, ordered in pairs. Two items alternate vice and node. The odd items are the node id he device id strings to indicate which device ber of list items will always be even�i.e., twice


: Log Record Format

� Generated by: test statement

� Subrecords: @DPIN is generated when logging pins to list the failing device pins.

Example 6-28

{@CCHK|01|0008|u34}

Record @DdeviceThis recorddevice.

Table 6-34 @DPIN

Format: {@DPIN|device name|node pin list} or {@DPIN|device name|node


device name

str "" Name of device, or test designator when

node pin list

str or int

""/0 List of items. Items alternate to give two sThe odd items are the node id strings. device pin strings to indicate which piid's. Device pins should be includedwill always be even�i.e., twice the numb

thru devnode list

str or int

"" This field is a list of DriveThru devices aninformation about each driven through destrings. Following them (even items) are tis connected to the node id's. The numthe number of nodes driven through.

© Agilent T 6-53

Chapter 6

12|BDRV|18}

ome of the action performed. Each block contains a digital sub-record describing the the digital test portion of the test. Each rd may contain NOTE and EXPRT

.

produced for a successful run with logor a failing execution with log level is

therwise no log is produced with the eption of using the log devices

.


: Log Record Format

� Generated by:

� test statement

Tests for digital devices produce an @DPIN record as a subrecord for @D-T (digital powered test) and for @TJET (TestJet test) whenever pins are being logged.

� probe statement, probe failures statement

These statements may produce @DPIN records, but as subrecords of the @PRB record when logging pins.

Example 6-29

{@DPIN|U12\4|Node17|8|GND|3}!No DriveThru Node{@DPIN|U6809\6|TCLK|18|U6809-12|!With DriveThru Node

Record @D-PLD: results of PLD programming -- success or failureData logging for PLD ISP is supported and controlled similarly to that of other test data types. Log record control is enabled via the BT-BASIC logging functions, such as �log is�, �log out�, and �log failure�.

Log records produced for a PLD ISP test type are grouped into a digital test block record (@BLOCK). Every play statement in the digital test generates a sub-record within the block that describes information

and the outcrecord also outcome ofD-PLD recosub-records

A record is level all

failures. Opossible excmechanism

© Agilent T 6-54

Chapter 6

message string> | <Player program

ram file used by the test.

by the play statement. SVF and Jam files use ns are not supported in these file types.

unning the action. A zero (or empty parameter)

e failure occurred.


: Log Record Format

.

D-PLD may have one or more @EXPRT subrecords, a shown in Table 6-36. These are Generated by the use of STAPL export commands in the programming file.

Table 6-35 @D-PLD

Format: {@D-PLD|<Filename> | <Action> | <Action return code> | <Resultcounter> | }


Filename str � � Identifies the name of the compiled prog

Action str � � Identifies the STAPL source action takena default name because procedural actio

Action return code

int 0 Specifies the return code as a result of rdesignates a passing condition.

Result message string

str � � Describes the error condition code.

Player program counter

int 0 Indicates the JBC opcode index where th

© Agilent T 6-55

Chapter 6

header commands within the STAPL source

able exported.

n exported.

eld returned.

returned.


: Log Record Format

D-PLD may also have one or more @NOTE subrecords as shown in Table 6-37. This record is generated by the

use of note file.

� Generated by: play statement

� Subrecords: @EXPRT and @NOTE

Table 6-36 @EXPRT

Format: {@EXPRT | <Key> | <Field> }


Key str � � Value that identifies the name of the vari

Field int 0 Represents the value of the variable whe

Table 6-37 @NOTE

Format: {@NOTE | <Note name> | <Note string> }


Note name str � � Identifies a keyword name for the note fi

Note string str � � Represents the contents of the note field

© Agilent T 6-56

Chapter 6

code test program:

2--Debug pipe mode}


: Log Record Format

Example 6-30

The following example shows a record produced from a STAPL read ID

{@BLOCK|d3_18v04|00{@D-PLD|digital/idtest.jam.jbc|read_idcode||||

{@EXPRT|Expected is: |1BBBB44444444445555555AAAA4321}{@EXPRT|Got >> nd : |01BBB44444444445555555AAAA4321}{@NOTE|CREATOR|Altera Chain Interrogation Version 2.0{@NOTE|DATE|2001/04/30}{@NOTE|ALG_VERSION|1}{@NOTE|STAPL_VERSION|JESD71}{@NOTE|MAX_FREQ|10000000}

}{@D-T|0|384||0|d3_18v04}

}

© Agilent T 6-57

Chapter 6

|test designator}

us for reason)

plete)

ary value; a bit is set to 1 if the event occurred; eanings (lsb to msb) are:


: Log Record Format

Record @D-T: test digitalThis record describes the results of a digital test. When pin logging is in effect, it is followed by a subrecord containing additional information.

Table 6-38 @D-T

Format: {@D-T|test status|test substatus|failing vector number|pin count


test status int 0 0 = passed1 = failed (see test substat

5 =CRC related failure7 = fatal error (test did not com

test substatus int 0 Decimal equivalent of a 6-bit binto 0 if it did not occur. The bit m� bit 0 fail� bit 1 SAFEGUARD timeout� bit 2 hardware error� bit 3 pause� bit 4 halt� bit 5 overvoltage

failing vector number

int 0 Which vector failed.

© Agilent T 6-58

Chapter 6

is statement is set to indictments (or r level). When these conditions are met, the groups the indict (@INDICT) records to that are believed to be faulty.

the example below, the group record is subrecord of MAGICCLUSTER (@M-CL) records roup (@GRP) records. Indict (@INDICT)

|test designator}


: Log Record Format




Example 6-31

{@D-T|1|1|39|3|U18}

NOTEFlash ISP tests are logged like a normal digital test.

Record @GRP: group recordThis record is used with MagicTest to indicate the grouping and relationship of the subrecords of a particular log record. This record is generated only when the MagicTest cluster test fails, and only when the

log level

some highe@GRP recordshow those

As shown innested as a and other g

pin count int 0 How many pins failed.

test designator str "" Designator (name) of test.

Table 6-38 @D-T (continued)

Format: {@D-T|test status|test substatus|failing vector number|pin count


© Agilent T 6-59

Chapter 6

T|MT\1|R3}T|MT\1|C4}

NDT|MT|0.333\1|R4|4.234291E+01|||R}RT|MT|0.167\1|C2}T|MT|0.167\1|R5}

NDT|MT|0.333\1|R6}RT|MT\1|R3}T|MT\1|C4}

NDICT: indict record is used with DriveThru and MagicTest. This ains a list of devices indicted by the est as either a potential failure or a known is generated when the log level is set to indictments (or some higher level). DriveThru, this record is nested as a f CPROBE (@TJET). When using MagicTest,


: Log Record Format

records can also be nested as a subrecord of group records.


Example 6-32

{@M-CL|1|cluster_C4{@GRP|OR{@GRP|AND{@GRP|OR{@INDICT|MT\1|R1}{@INDICT|MT\1|R2}}{@GRP|OR

{@INDIC{@INDIC}}{@GRP|A{@INDIC{@GRP|O{@INDIC{@INDIC}}{@GRP|A{@INDIC{@GRP|O{@INDIC{@INDIC}}}}

Record @IThis recordrecord contrespective tfailure, andstatement isWhen usingsubrecord o

Table 6-39 @GRP

Format: {@GRP|relationship}


relationship str "" Describes how subrecords are related, or what causes them to be grouped:� AND indicates all of

the subrecords� OR indicates one or

more of the subrecords.

© Agilent T 6-60

Chapter 6

t induct|est model}

u or MT to indicate MagicTest.

esignators for the indicted devices. When using evice name. When using DriveThru, the record eparated by a colon). For more information see erpreting the Log Records on page 6-11.

or MagicTest to show the estimated resistance.

for MagicTest to show the estimated

for MagicTest to show the estimated

l used for deriving the estimates (if any) for rtion of the string indicate that a particular or C. If there is more than one such letter, then for in series or -P for in parallel.C-S, RL-P, and RL-S. L and C are not


: Log Record Format

this record is nested as a subrecord of a MAGICCLUSTER (@M-CL) or a GROUP (@GRP) record.

Table 6-40 @INDICT

Format: {@INDICT|technique\device list|est resistance|est capacitance|es


technique str "" Always either DT to indicate DriveThr

device list str The device list shows the reference dMagicTest, the record contains one dcan contain multiple device names (sthe examples below, and refer to Int

est resistance fp (optional) This is sometimes present fNot used for DriveThru.

est capacitance

fp (optional) This is sometimes present capacitance. Not used for DriveThru.

est inductance fp (optional) This is sometimes present inductance. Not used for DriveThru.

est model str "" (optional) String identifying the modeMagicTest. The letters in the main poparameter has been estimated: R, L,there will also be a suffix of either -SExpected values are R, L, C, RC-P, Rcombined.

© Agilent T 6-61

Chapter 6

}

ode statement


: Log Record Format


Example 6-33

MagicTest examples:{@INDICT|MT\1|r40809|+5.179527E+03|||R}{@INDICT|MT\1|c40233|+6.937080E+03|+8.442845E-10||RC-P}{@INDICT|MT\1|R40554|+5.653664E+05||+1.074852E+01||RL-P{@INDICT|MT\1|c40812}

DriveThru examples:{@INDICT|DT\1|r12}{@INDICT|DT\3|rp6:r2|c412|r22}

Record @LIM2: high & low limits of analog testThis record contains the high and low limits for an analog test. When limits are being logged, it is followed by a subrecord containing additional information.

� Generated by: � di

Table 6-41 @LIM2

Format: {@LIM2|high limit|low limit}


high limit fp 0 Upper limit for allowable range.

low limit fp 0 Lower limit for allowable range.

© Agilent T 6-62

Chapter 6

4

8.666667E+01|2.000000E+00}

IM3: nominal high/low is logged by statements which optionally nent's nominal value and its high and low . The limits are calculated from the nominal lus and minus tolerance limits, and any ffect from a tolerance margin statement. is not generated if the log level was specified nhls.

tentiometer statementsistor statementner statement

inal value plus the allowed positive deviation

inal value plus the allowed negative deviation


: Log Record Format

� fuse statement� jumper statement� measure statement� nfetr statement� npn statement� pfetr statement� pnp statement� switch statement


Example 6-3

{@LIM2|

Record @LThis recordlog a compovalue limitsvalue, the pmargin in eThe record as without

� Generated by:

� capacitor statement� inductor statement

� po

� re

� ze

Table 6-42 @LIM3

Format: {@LIM3|nominal value|high limit|minus tolerance}


nominal value fp 0 The nominal value.

high limit fp 0 Upper limit: The sum of the nomfrom the nominal value.

low limit fp 0 Lower limit: The sum of the nomfrom the nominal value.

© Agilent T 6-63

Chapter 6

rated by: test statement

6

luster_C4RNDRT|MT\1|R1}T|MT\1|R2}

RT|MT\1|R3}T|MT\1|C4}

NDT|MT|0.333\1|R4|4.234291E+01|||R}RT|MT|0.167\1|C2}T|MT|0.167\1|R5}

NDT|MT|0.333\1|R6}RT|MT\1|R3}T|MT\1|C4}


: Log Record Format


Example 6-35

{@LIM3|22|1.500000E+00|2.000000E+00}

Record @M-CL: MAGICCLUSTER recordThis record is used with MagicTest to return the status of a cluster test. This record is generated when the MagicTest cluster test fails, and when the log level

is statement is set to failures (or some higher level). This record is nested within the @BTEST record and indicates the pass/fail status of an analog cluster test. MAGICCLUSTER records sometimes contain the following subrecords: GROUP (@GRP) records, INDICT (@INDICT) records, or no subrecords.

� Gene

Example 6-3

{@M-CL|1|c{@GRP|O{@GRP|A{@GRP|O{@INDIC{@INDIC}{@GRP|O{@INDIC{@INDIC}}{@GRP|A{@INDIC{@GRP|O{@INDIC{@INDIC}}{@GRP|A{@INDIC{@GRP|O{@INDIC{@INDIC}}}}

Table 6-43 @M-CL

Format: {@M-CL|status|cluster_name}


status int 0 0 = passed1 = failed7 = indeterminate test due to measurement error

cluster_name str "" Name of this cluster.

© Agilent T 6-64

Chapter 6

quest in YYMMDDHHMMSS format

rated by prsetup, and changes to a 1 when rm.


: Log Record Format

Record @NETV: network verification recordThis record is used to verify the integrity of the network link to whichever system is specified.

� Generated by: prsetup program


Example 6-37

{@NETV|890530102019|alpha|beta|1}

Table 6-44 @NETV

Format: {@NETV|datetime|test system|repair system|source}


datetime str 0 Date and time of verification re(datetime$).

test system str "" Identifier of test system.

repair system str "" Identifier of repair system.

source bool 0 This field contains 0 when genethe record is processed by ala

© Agilent T 6-65

Chapter 6

node by its node id.


: Log Record Format

Record @NODE: list of nodesThis record contains a list of nodes. It appears as a subrecord to further describe whichever record precedes it.

� Generated by:

� make diagnosis statement� probe statement� probe failures statement

Example 6-38

{@NODE\2|Node53|+5Volts}

Table 6-45 @NODE

Format: {@NODE\node list}


node list str "" Each item in the list specifies a

© Agilent T 6-66

Chapter 6

lete)


: Log Record Format

Record @PCHK: Polarity Check TestThis record describes the results of a test made by an Polarity Check test.


Example 6-39

{@PCHK|01|c34}

Table 6-46 @PCHK

Format: {@PCHK|test status|test designator}


test status int 00 00 passed

01 failed

07 fatal error (test did not comp

test designator str ""

© Agilent T 6-67

Chapter 6

tifies the file containing the source code for the <file id> parameter in the test statement.


: Log Record Format

Record @PF: pinsfailedThis record contains the results of a test statement. It is followed by a one or more subrecords containing a list of pins.


� Subrecords: @PIN: Contains a list of pins acquired in test mode


Example 6-40

{@PF||1|4{@PIN\4|10472|12235|21612|11302}

}

Table 6-47 @PF

Format: {@PF|designator|test status|total pins}


designator str "" An optional designator that idenpins test. This comes from the

test status int 0 0 = testing passed1 = testing failed

total pins int 0 Total number of failing pins.

© Agilent T 6-68

Chapter 6

RB: (partial) results of probing

contains the results of the probe and probetatements. It can be followed by subrecords list of failing pins.

pin in BRRCC format.

iling device).


: Log Record Format

Record @PIN: list of pinsThis record contains a list of pins. It appears as a subrecord to further describe to whichever record precedes it.

� Generated by: pinsfailed statement


Example 6-41

{@PIN\5|11571|20314|12065|20508|11443}

Record @P(failures)This recordfailures scontaining a

Table 6-48 @PIN

Format: {@PIN\pin list}


pin list str "" Each item in the list specifies a

Table 6-49 @PRB

Format: {@PRB|test status|pin count|test designator}


test status int 0 0 = passed; 1 = failed

pin count int 0 How many pins failed.

test designator str "" The test designator (name of fa

© Agilent T 6-69

Chapter 6

robe record is generated for each device .

probe failures statement generates cords to report all of the failing nodes.

sponds to: 51 record on a 3065 system.

ACT: describe a repair action describes a repair that was performed on a

nt batch|repair omment3|comment4|comment5|rep cause

for the board.

for the board.

d component.

component.

ir was recorded.

nent.


: Log Record Format

� Generated by:

� probe statement� probe failures statement

� Subrecords: @DPIN is generated when logging pins to list failing device pins

Example 6-42

{@PRB|1|2|U23{@DPIN|\2|Node63||Node22|}

}

NOTEOne ptested

Each subre

Corre

Record @RThis recordPC board.

Table 6-50 @RACT

Format: {@RACT|rep cause code|rep action code|component id|componedatetime|vendor|designator|Xlocation|Ylocation|comment1|comment2| |cdesc|rep action desc}


rep cause code str "" The repair cause code entered

rep action code str "" The repair action code entered

component id str "" The unique identifier of the faile

component batch str "" Batch information for the failed

repair datetime int 0 The date and time that the repa

vendor str "" The vendor of the failed compo

© Agilent T 6-70

Chapter 6

sponds to: R6, R7, and R8 records on a 3065 that has PR PLUS installed.

aged part|board repaired locally}

ponent.

he failed component on the PC board.

he failed component on the PC board.

nt describing the repair.





use code, as entered in prsetup.

tion code, as entered in prsetup.

nt batch|repair omment3|comment4|comment5|rep cause


: Log Record Format

� Generated by: prplus program � Corresystem

Example 6-43

{@RACT|3|2|||890315171548|LexCo|U98|12|10|Bent pin|||||dam

designator str "" The designator of the failed com

X-location str "" The X-location (coordinate) of t

Y-location str "" The Y-location (coordinate) of t

comment1 str "" An optional free-format comme





rep cause desc str "" The description of the repair ca

rep action desc str "" The description of the repair ac

Table 6-50 @RACT (continued)

Format: {@RACT|rep cause code|rep action code|component id|componedatetime|vendor|designator|Xlocation|Ylocation|comment1|comment2| |cdesc|rep action desc}


© Agilent T 6-71

Chapter 6

head type|process step|repair system|batch tion|rep operator type|rep operator id|repair

ard.

.

used to test the failed board.

st the failed board�65H, 70, etc.

ring process the board failed.

aired.

he failed board belonged.

ted.

he failed board.

t the failed board.

e failed board.


: Log Record Format

Record @REP: describe a repair eventThis record describes a repair event associated with a PC board.

Table 6-51 @REP

Format: {@REP|board type|board type rev|fixture id|testhead number|testid|test system|testplan id|testplan rev|board id|repair datetime|repair duraalarm|test datetime|repair status}


board type str "" The board type of the failed bo

board type rev str "" The revision of the failed board

fixture id int 0 The autofile code of the fixture


testhead type str "" The type of testhead used to te

process step str "" At which step in the manufactu

repair system str "" Where the failed board was rep

batch id str "" ID of batch of boards to which t

test system str "" Where the failed board was tes

testplan id str "" Name of testplan used to test t

testplan rev str "" Revision of testplan used to tes

board id str "" The unique serial number of th

© Agilent T 6-72

Chapter 6

HHMMSS format (datetime$) when the repair

onds.

repair.

= no

HHMMSS format (datetime$) when the failed

ir?

Versions.

head type|process step|repair system|batch tion|rep operator type|rep operator id|repair


: Log Record Format

repair datetime int 0 The date and time in YYMMDDbegan.

repair duration int 0 How long the repair took, in sec

rep operator type str R R = RepairA = Technical AnalystQ = Quality Assurance

rep operator id str "" Which repair operator made the

repair alarm bool N Repair alarm active? Y = yes, N

test datetime int 0 The date and time in YYMMDDboard was last tested.

repair status int 0 What was the status of the repa� 0 no repair (viewed failures)� 1 normal repair� 2 board was scrapped� 3 board was lost

version label str "" Version label for Multiple Board

Table 6-51 @REP (continued)

Format: {@REP|board type|board type rev|fixture id|testhead number|testid|test system|testplan id|testplan rev|board id|repair datetime|repair duraalarm|test datetime|repair status}


© Agilent T 6-73

Chapter 6

sponds to: R4, R5, and R8 records on a 3065 that has PR PLUS installed.

35-608||881108112344|112|R

ta which was logged and later found to be pinsfailed function being true.

PT: messages logged by report contains the text string produced by ny of the report statements�i.e., report

for retest in YYMMDDHHMMSS format


: Log Record Format

� Subrecords: @RACT subrecord(s) describe the repairs made on the failed board.

� Corresystem

Example 6-44

{@REP|my_bd|1|241|1|70A|TEST|delta|0314898|beta|my_bd1|B|1|Jack|Y| 881108101516|1

(any @RACT subrecords)}

Record @RETEST: indicate a log clear for retestThe presence of this record indicates that a log clear

for retest occurred. A log clear for retest

removes dabogus by a

� Generated by: log clear for retest statement

Example 6-45

{@RETEST|890819184413}

Record @RThis recordexecuting a

Table 6-52 @RETEST

Format: {@RETEST|datetime}


datetime str "" Date and time of a log clear

(datetime$).

© Agilent T 6-74

Chapter 6

tatement.


: Log Record Format

(ANALOG), report (BT-BASIC), or report (SHORTS)�whenever the report level is log or all.

� Generated by: report statements


The location at which this record is nested inside @BLOCK records may vary; for example, an @RPT record associated with a specific test may appear nested inside the @BLOCK record associated with a different test. This causes no problem for the standard software packages that use log data, such as Pushbutton Q-STATS.

Example 6-46

{@RPT|U91 failed}

Table 6-53 @RPT

Format: {@RPT|message}


message str "" The string given in a report s

© Agilent T 6-75

Chapter 6

ss substatus}

en not using a debug object, a name having

failed. Or, when not using a debug object, this program counter when the failure occurred.

e test failed. Possible values are: 0 and 23

on failed


: Log Record Format

Record @S-PROC: describe process in serial testThis record describes a process in a serial test. Each process in the test generates its own log record that contains information about that process.

Table 6-54 @S-PROC

Format: {@S-PROC|process|test status|fail location|process status|proce


process str "" Identifier of the process. Or, whthe form MSSP, where:� M module� SS slot� P process

test status int 0 The status of the test, where:� 0 pass� 1 fail

fail location int 0 Line number where the processis a negative value equal to the

process status int 0 A number that indicates why th� 4 Bit index must be between� 5 Received frame comparis

© Agilent T 6-76

Chapter 6

xpectedexpectednment overflow

e is invalidger conversion

alid0 error

sslls are not allowedeived a frame of incorrect length

an two bits

l trigger

ss substatus}


: Log Record Format

� 6 Received more bits than e� 7 Received fewer bits than � 8 Function "itf$" frame assig� 9 Function "itf$" length valu� 10 Overflow in frame to inte� 11 Illegal use of null frame� 12 Trigger state value is inv� 13 Cannot mod, div, or / by � 14 Receive buffer overflow� 15 Halted by another proce� 16 Recursive subroutine ca� 17 Function "berreceive" rec� 18 Channel value is invalid� 19 Cannot transmit fewer th� 20 User halted serial failing� 21 User halted process� 30 Running normally� 31 Completed normally� 32 Timeout waiting for digita

Table 6-54 @S-PROC (continued)



© Agilent T 6-77

Chapter 6

ve frame syncmit frame syncve clock

start error

length errorlowignment overflow

rruptr interruptrupt

upttruptterrupt

runnun

ss substatus}


: Log Record Format

� 33 Timeout waiting for recei� 34 Timeout waiting for trans� 35 Timeout waiting for recei� 40 Subframe start error� 41 Subframe temp-variable � 42 Subframe length error� 43 Subframe temp-variable � 44 Frame assignment overf� 45 Frame temp-variable ass� 70 internal error: Reset inte� 71 internal error: Stack erro� 72 internal error: Trace inter� 73 internal error: SWI interr� 74 internal error: III interrup� 75 internal error: Extra inter� 76 internal error: SSIWEX in� 80 STC transmit data under� 81 STC receive data overru� 82 STC receive frame overr




© Agilent T 6-78

Chapter 6

ream or filter error occurredd LCA interrupt occurred

n stream connected to this process

et, indicate the following low-level conditions:

etected on the Serial Test Card used by this

on the stream attached to this process on the stream attached to this processers were received from the digital sequencer

ss substatus}


: Log Record Format


� 83 Undefined stream, subst� 84 internal error: unexpecte� 411 Transmit data underrun� 412 XDLC filter FCS error� 413 Overcurrent detected o

test substatus int 0 A set of bits whose bits, when s� bits 0 - 9 not used� bit 10 PLL out-of-lock was d

process� bit 11 not used� bit 12 overcurrent occurred� bit 13 overvoltage occurred� bit 14 too many digital trigg� bit 15 not used




© Agilent T 6-79

Chapter 6

ontents of two fields, process and failion, depend not only on the failure but also ether there is a debug object present for that lternating between having and not having a object will cause inconsistent naming es to be used by statistical quality control ges, such as Pushbutton Q-STATS. Thus, a test is in production, it probably is best to s have the debug object present.

to the System Administrator: You can l this by specifying yes or no for the .Debug variable in the .hp3070 file

iated with the user login.


: Log Record Format

Example 6-47

Example of output from failing mixed test func1. This test has three processes: RECEIVE, FILTER, and FBMON. The first two processes are failing, while the last passes.

{@BLOCK|func1|1{@D-T|1|4161|41|0|func1}{@S-PROC|RECEIVE|1|82|3|19}{@S-PROC|FILTER|1|996|12|3}{@S-PROC|FBMON|7|0}

}

Example of output from passing mixed test func2. In this test all processes are passing.

{@BLOCK|func2|0{@D-T|0|384||0|stl01}{@S-PROC|RECEIVE|0}{@S-PROC|FILTER|0}{@S-PROC|CAR1|0}{@S-PROC|CAR2|0}{@S-PROC|FBMON|0}

}

NOTEThe clocat

on whtest. Adebugschempackaonce alway

Note controMcomp

assoc

© Agilent T 6-80

Chapter 6


: Log Record Format

Record @TJET: TestJet TestThis record that describes the results of TestJet tests.



Example 6-48

{@TJET|01|0008|u34}

Table 6-55 @TJET

Format: {@TJET|test status|pin count|test designator}


test status int 00 00 = pass01 = fail07 = fatal error

pin count int 0000 number of failing pins

test designator str ""

© Agilent T 6-81

Chapter 6

9

2|1|1|S|2|0|Node12TS-D|Node25|1.678853E+00}TS-D|Node26|2.543216E+00}

O|Node43|Node14|-1.500000E+00}S|0|1|Node38TS-P|-1.243853E+02}

gnator}

d

shorted to some short-source node.

open.

red.

e file containing the source code for the shorts rameter in the test shorts statement.


: Log Record Format

Record @TS: test shortsThis record describes a shorts test.

� Generated by: test shorts statement

� Subrecords:

� @TS-O is generated for each unexpectedly open node pair.

� @TS-S is generated for each unexpectedly shorted short-source node. Contains @TS-D subrecords to identify which destination node(s) the source node was shorted to, or @TS-P subrecords to identify phantom shorts.

� Corresponds to: 41 statement on an 3065 system.

Example 6-4

{@TS|1|{@TS-

{@{@

}{@TS-{@TS-

{@}

}

Table 6-56 @TS

Format: {@TS|test status|shorts count|opens count|phantoms count|desi


test status int 0 0 passed; 1 failed; 20 learning passe

shorts count int 0 How many nodes were unexpectedly

opens count int 0 How many nodes were unexpectedly

phantoms count int 0 How many phantoms were encounte

designator str "" (optional) Designator that identifies thtest. This comes from the <file id> pa

© Agilent T 6-82

Chapter 6

sponds to: 06 record on an 3065 system preceded by a 42 record whose field 5-8 has lue 01.

red into two fields for each destination

tination node. M - T, where M is this destination node's threshold.


: Log Record Format

Record @TS-D: destination nodes shorted to source nodeThis record describes destination nodes which are shorted to a source node.

� Generated by: test shorts statement � Correwhenthe va

Example 6-50

{@TS-D\4|Node7|1.398537E+02|Node15|4.138792E+01}

Table 6-57 @TS-D

Format: {@TS-D\destination list}


destination list str/fp ""/0 A list of items which are painode, as follows:

� node id the id of this des� deviation the difference

measured value and T is the

© Agilent T 6-83

Chapter 6

S-P: phantoms found while shorts

describes phantoms found while shorts

is the measured value and T is the threshold.

is the measured value and T is the threshold.


: Log Record Format

Record @TS-O: opens found while shorts testingThis record describes open found while shorts testing.


� Corresponds to: 42 record on a 3065 system with a value of either 2 or 3 in field 3-4.

Example 6-51

{@TS-O|Node85|Node14|-1.510000E+00}

Record @TtestingThis recordtesting.

Table 6-58 @TS-O

Format: {@TS-O|source node|destination node|deviation}


source node str "" The open-source node id.

destination node str "" The open-destination node id.

deviation fp 0 The difference M - T, where M

Table 6-59 @TS-P

Format: {@TS-P|deviation}


deviation fp 0 The difference M - T, where M

© Agilent T 6-84

Chapter 6

S-S: results of shorts testing from a de describes a shorts test from a source node.

3

2||Node43D|Node14|1.678859E+00}D|Node32|6.182541E+01}

ere unexpectedly shorted to the source node.

ountered from the source node.

e is actually a set of siamese nodes, then the of the set�probably just the first one in the list.


: Log Record Format


� Corresponds to: 42 record on a 3065 system with a value of 4 in field 3-4.

Example 6-52

{@TS-P|-1.243853E+02}

Record @Tsource noThis record


� Subrecords:

� @TS-D is generated for each destination that is unexpectedly shorted.

� @TS-P is generated for each phantom encountered.

� Corresponds to: 42 record on a 3065 system with a value of 0 or 1 in field 3-4.

Example 6-5

{@TS-S|{@TS-{@TS-

}

Table 6-60 @TS-S

Format: {@TS-S|shorts count|phantoms count|source node}


shorts count int 0 How many destination nodes w

phantoms count int 0 How many phantoms were enc

source node str "" The source node id. If the sourcnode id given is representative

© Agilent T 7-1

In this


7777 The Board Defaults FilesThe Board Defaults FilesThe Board Defaults FilesThe Board Defaults Files

chapter... � Overview, 7-2� The board_defaults File, 7-3� The edge_ board_defaults File, 7-5


� Understand the content the board defaults files



© Agilent T 7-2

Chapter 7

Overv s of board defaults files are in the standard

oard_defaults file, $AGILENT3070_ROOT/ard/board_defaults, contains values that pical for a combinational test strategy.

dge_board_defaults file, $AGILENT3070_standard/edge_board_defaults,

ins values that are typical for an connector-only test strategy.

y one of the standard board defaults files to irectory, modify it to fit your exact needs, it as board_defaults. However there are tions when modifying the default file:

s are not allowed for nodes, internal es, device options, or critical pins.

-checking of the default board is not ed.

eveloping an edge-connector-only test, you the edge_board_defaults file to your directory and rename it board_defaults rming data entry.


: The Board Defaults Files

iew The board defaults file, board_defaults, provides Board Consultant and the CAD Format Translator (CFT) with values to use in the board file when those values are not provided by data files or by data entry.

Board Consultant and CFT look for a board_defaults file in the local board directory. If there is no board_defaults file in the local board directory, Board Consultant and CFT look under $AGILENT3070_ROOT/standard.

NOTEWith Agilent 3070 software revision 3070 04.00pa, an environment variable was created so that files can be easily transferred between UNIX® and MS Windows® controllers, which have different file systems. The environment variable, $AGILENT3070_ROOT, replaces the upper path names on both systems. For example, the $AGILENT3070_ROOT factory default value is /var/hp3070. In this document, only path names using the environment variable are used. If you must use actual path names, refer to older versions of the documentation. Please see The Root Directory Environment Variable in Administering Agilent 3070 UNIX Systems for further information.

Two versiondirectory:

� The bstand

are ty

� The eROOT/

contaedge-

You can copyour local dand re-savesome restric

� Entriedevic

� Crossallow

If you are dshould copylocal board before perfo

© Agilent T 7-3

Chapter 7

The boFile put DefaultX;

NONE;

igh 3.5;ow 0.2;High 2;Low 0.8;

eed 100;put DefaultX;

UP;

igh -0.5;ow -2.7;High -1.2;Low -1.5;

eed 150;put Default0;

DOWN;IONS

OPTIONSNT3070_ROOT/library/ttl"NT3070_ROOT/library/lsi"NT3070_ROOT/library/cmos"NT3070_ROOT/library/ecl"NT3070_ROOT/library/setup"



ard_defaults Example 7-1 Board defaults specified in the board_defaults file

HEADING"These are the board defaults";GLOBAL OPTIONSFixture Type EXPRESS;Fixture Size FULL;Top Probes AllowedOFF;Heavy Probe Force8;Light Probe Force4;Mechanical Density Threshold800;Vacuum Density Threshold104;Test Strategy COMBINATIONAL;WireWrapping MANUAL;Metric Units OFF;Common Lead Resistance0.5;Common Lead Inductance1u;Capacitance CompensationON;DEVICE OPTIONSTolerance Multiplier5;Remote Sensing ON;Fuse Threshold 10;Diode Current 5m;Zener Current 10m;Adjust FAST;Upstream Disable OFF;Upstream ConditionOFF;FAMILY OPTIONSCMOSDrive High 4;Drive Low 0.8;Receive High 3.6;Receive Low 1.3;Edge Speed 50;

Open InLoadTTLDrive HDrive LReceiveReceiveEdge SpOpen InLoadECLDrive HDrive LReceiveReceiveEdge SpOpen InLoad

CARD OPTCMOSHYBRID;TTLHYBRID;ECLHYBRID;

LIBRARY“$AGILE“$AGILE“$AGILE“$AGILE“$AGILE

© Agilent T 7-4

Chapter 7

ARY

METER** **;

** ** f;

OFF;OR

** n;

** **;



CAPACITORC ** ** ** f;CONNECTORJ NT;DIODECR ** **;FETQF ** ** n;FUSEF 1;INDUCTORL ** ** ** 1 f;JUMPERJP Closed;

PIN LIBRU;POTENTIOP **RESISTORR **SWITCHS **TRANSISTQ **ZENERDS **END

© Agilent T 7-5

Chapter 7

The edboard Low 1.3;

eed 50;put Default X;

NONE;

igh 3.5;ow 0.2;High 2;Low 0.8;

eed 100;put Default X;

UP;

igh -0.5;ow -2.7;High -1.2;Low -1.5;

eed 150;put Default 0;

DOWN;IONS

OPTIONST3070_ROOT/library/ttl"T3070_ROOT/library/lsi"T3070_ROOT/library/cmos"T3070_ROOT/library/ecl"



ge__defaults File

Example 7-2 Board defaults specified in the edge_board_defaults file

HEADING"These are the board defaults foredge connector use only";GLOBAL OPTIONSFixture Type EXPRESS;Fixture Size FULL;Top Probes Allowed OFF;Heavy Probe Force 8;Light Probe Force 4;Mechanical Density Threshold800;Vacuum Density Threshold 104;Test Strategy EDGE CONNECTOR

ONLY;WireWrapping MANUAL;Metric Units OFF;Common Lead Resistance 0.5;Common Lead Inductance 1u;Capacitance Compensation ON;DEVICE OPTIONSTolerance Multiplier5;Remote Sensing ON;Fuse Threshold 10;Diode Current 5m;Zener Current 10m;Adjust FAST;Upstream Disable OFF;Upstream Condition OFF;FAMILY OPTIONSCMOSDrive High 4;Drive Low 0.8;Receive High 3.6;

ReceiveEdge SpOpen InLoadTTLDrive HDrive LReceiveReceiveEdge SpOpen InLoadECLDrive HDrive LReceiveReceiveEdge SpOpen InLoad

CARD OPTCMOSHYBRID;TTLHYBRID;ECLHYBRID;

LIBRARY“$AGILEN“$AGILEN“$AGILEN“$AGILEN

© Agilent T 7-6

Chapter 7

RARYNS;

METER** ** NT;

** ** f NT;

OFF NT;OR

** n NT;

** ** NT;TED PIN NC;



“$AGILENT3070_ROOT/library/setup"CAPACITORC ** ** ** f NT;CONNECTORJ NT;DIODECR ** ** NT;FETQF ** ** n NT;FUSEF 1 NT;INDUCTORL ** ** ** 1 f NT;JUMPERJP ClosedNT;

NODE LIBU NTPOTENTIOP **RESISTORR **SWITCHS **TRANSISTQ **ZENERDS **UNCONNECEND

© Agilent T 8-1

In this


8888 Part Description LanguagePart Description LanguagePart Description LanguagePart Description Language

chapter... � About Part Description Language, 8-2� Reference Description of PDL, 8-16


� Understand the Part Description Language (PDL), which is the language used to describe devices in a part description library.



© Agilent T 8-2

Chapter 8

AboutDescrLangu

ent describes a fixed resistor (f) denoted r1. value is 10k ohms, and it has a tolerance of means the resistor is not individually ; it is a child device within a parent device. If ing board test, a replaceable device that in the hierarchy must be replaced.

escription library has PDL statements like in a file. The next section provides at show how these statements are used form libraries.

ctory $AGILENT3070_ROOT/library/art_library for examples of part

library files. For complete descriptions of f PDL, see Reference Description of PDL 6.

Agilent 3070 software revision 3070 pa, an environment variable was created so les can be easily transferred between ® and MS Windows® controllers, which

different file systems. The environment le, $AGILENT3070_ROOT, replaces the upper ames on both systems. For example, the ENT3070_ROOT factory default value is p3070. In this document, only path names the environment variable are used. If you


: Part Description Language

Part iption age

OverviewPart Description Language has statements that describe devices. These statements are stored in files, one file per part, in library directories. When you use the Part Description Editor it automatically creates files containing the required PDL statements. Thus, test developers will usually not need to know much about PDL.

Structure of Part Description LanguageLike other programming languages, PDL has a specific syntax. To read files containing descriptions of parts written in PDL, you must understand this syntax. Sometimes PDL describes the relationship between a parent device and its child devices. For example,

external pins 1device "u1" pins 2

describes the connection between the external pin 1 on the parent device and pin 2 on child device u1.

In other cases, PDL has keywords followed by parameters (some of which may be optional) that describe a child device. For example, the keyword resistor would be followed by a list of parameters that describe a specific resistor, like this:

resistor "r1", 10k, 5, 5, f, nr

This statemIts nominal+/- 5%. nr replaceabler1 fails durprecedes it

Each part dthese storedexamples thtogether to

Look in diretemplate/p

description the syntax oon page 8-1

NOTEWith 04.00that fiUNIXhave variabpath n$AGIL

/var/husing

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Chapter 8

of Part Description Librariesw are several examples of how PDL is used tries in a part description library.

ple: A Resistor Packu were writing a part description library for pack shown in Figure 8-1.

nnections between internal devices and s.



must use actual path names, refer to older versions of the documentation. Please see The Root Directory Environment Variable in Administering Agilent 3070 UNIX Systems for further information.

Examples Shown beloto create en

Simple ExamSuppose yothe resistor

Figure 8-1 Internal structure of a resistor pack

Notice that the internal devices in the figure above have arbitrarily assigned pin numbers. These are needed to

describe coexternal pin

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Chapter 8

ription library file (named rpack_type123, the board file) describing this device might is:

erpt from part description library

r "r1", 10k, 5, 5, f, nrr "r2", 10k, 5, 5, f, nrr "r3", 10k, 5, 5, f, nrl pins 1e "r1" pins 1l pins 2e "r2" pins 1l pins 3e "r3" pins 1l pins 4e "r1" pins 2e "r2" pins 2e "r3" pins 2

y cannot be individually replaced, the stors�r1 through r3—are denoted nr for able. The number following the externalent is a designator that refers to a pin

the package, which must be an external node sible for probing.



Before you can use a part description library in a board test, you must invoke the Pin Library Device Entry Form in Board Consultant (described in Chapter 2, Agilent Board Consultant in Test Development Tools) and make a corresponding entry there. Use the form to specify the associations between device pins on the parent part and nodes at the board level.

After using the Pin Library Device Entry Form, the board file entry for the example above might look like this:

Example 8-1

! Excerpt from board file!

PIN LIBRARYrp1 PN"RPACK_TYPE123"

CONNECTIONSNODE_A

rp1.1;NODE_B

rp1.2;NODE_C

rp1.3;NODE_D

rp1.4;

Each pair of entries beneath the connections keyword associates a pin on the library device with a node to be tested. For example, NODE_A is associated with rp1.1, which is pin 1 on rp1, NODE_B is associated with pin 2 on rp1 (rp1.2), etc.

A part descas shown inlook like th

Example 8-2

! Exc!

resistoresistoresistoexterna

devicexterna

devicexterna

devicexterna

devicdevicdevic

Because theinternal resinon-replacepins statemnumber on that is acces

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Chapter 8

1 nr;

is expanded listing is useful for verifying of the board file, it is not a valid source file ontains colons, which are not allowed in es. You must not replace your original board

ith this file.

ignators were numbers in the preceding t they also could have been strings to denote vice whose pin designators are not strictly r example, the entry in the board file:

erpt from board file

RARYPN"RPACK_TYPE123"IONSA1."R1"; ! Note the use of strings

! for pin designators that! were numbers in the

B ! previous example.1."R2";C1."R3";Drp1."COMMON";

s part description library:



IPG will use the part description library and information entered in Board Forms to create three analog test files during the test development process. These files are:

� rp1:r1

� rp1:r2

� rp1:r3

If a resistor inside the resistor pack fails during testing, the failure message associated with it will identify which one failed�for example, rp1:r1�and that the entire package�rp1�must be replaced.

If desired, you can list the compiled board file to examine its contents. This lets you verify that the library test was created. You use the BT-BASIC list object statement to create a source listing of an object file.

For example, executinglist object 'board.o'

produces a source file listing that includes the following:

Example 8-3

resistorrp1:r1 10k 5 5 f;rp1:r1 10k 5 5 f;rp1:r1 10k 5 5 f;

internal structure rp1;rp1:r1 nr;rp1:r1 nr;

rp1:r

Although ththe contentsbecause it cdevice namsource file w

The pin desexample, bupins on a denumeric. Fo

Example 8-4

! Exc!

PIN LIBrp1

CONNECTNODE_

rp

NODE_rp

NODE_rp

NODE_

matches thi

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Chapter 8



Example 8-5

! Excerpt from part description library!resistor "r1", 10k, 5, 5, f, nrresistor "r2", 10k, 5, 5, f, nrresistor "r3", 10k, 5, 5, f, nrexternal pins "r1"

! Each pin designator in! an "external pins" statement! must match its counterpart! in the board file.

device "r1" pins 1external pins "r2"

device "r2" pins 1external pins "r3"

device "r3" pins 1external pins "common"

device "r1" pins 2device "r2" pins 2device "r3" pins 2

Whichever method you use, numbers or strings, the pin designator following the external pins statement must match the corresponding pin designator in the board file.

Complex Example: A Package DeviceFigure 8-2 shows a more complex parent device, followed by a correspondingly more complex example of a part description library file.

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Chapter 8

l pins 2e "u1" pins 2l pins 3e "u1" pins 3l pins 4e "u1" pins 4l pins 5e "rp1" pins 1l pins 6e "rp1" pins 2l pins 7e "r1" pins 1l pins 8; noconnect



Figure 8-2 Internal structure of a package device

A part description library file describing this parent device might look like this:

Example 8-6

! Part description library for! package1

pin library "u1", nr, pn"7705"pin library "rp1", nr, pn"rpack_type123"resistor "r1", 10k, 5, 5, f, nrcapacitor "c1", 100p, 10, 10, f, nrexternal pins 1

device "u1" pins 1

externadevic

externadevic

externadevic

externadevic

externadevic

externadevic

externa

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Chapter 8

nal pins 8 and 9 are denoted noconnect se, although they exist physically, they do ectrically connect to a device within ge1.

is one internal (not externally accessible) internal_c1_r1, which is the connection en c1 and r1. It is denoted nomanual se it cannot be manually probed by the test operator.

rt description library has been created, the ices in package1 can be referenced as

ge1:u1 is a non-replaceable library device e type is 7705.

ge1:rp1 is a non-replaceable resistor pack. library device whose type is _type123.

ge1:r1 is a 10K resistor.

ge1:c1 is a 100 picofarad capacitor.

and c1 are connected to an internal node, t accessible via the fixture, IPG will not for them.



external pins 9; noconnectexternal pins 10

device "c1" pins 2external pins 11

device "rp1" pins 3external pins 12

device "rp1" pins 4external pins 13

device "u1" pins 5external pins 14



device "u1" pins 8node "internal_c1_r1"; nomanual

device "c1" pins 1device "r1" pins 2

Suppose the device for which this file was written is called package1. A part description library file begins with a list of child devices within the parent device. The library statements at the beginning of the file specify two child devices, u1 and rp1, inside package1. Note that each of these child devices is itself a parent device (that is, it contains child devices) with its own library file. A resistor statement and a capacitor statement specify two additional child devices within package1.

Following the list of child devices within package1 is a list of pin specifications that describes the associations between internal pins and external pins. Examine these specifications and notice the following:

� Exterbecaunot elpacka

� Therenode,betwebecauboard

After the painternal devfollows:

� packa

whos

� packa

It is arpack

� packa

� packa

Because r1which is nowrite a test

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Chapter 8

ited Traits to Model Devicesshows one section of a hypothetical device Suppose PK1 already has a library test (but escription library) written for it. That library es the device so that IPG can generate a test t the library test does not help when e effect that PK1 has on adjacent circuitry.



How Child Devices Inherit Traits From Parent DevicesIf you enter an asterisk (*) as a designator for a child device in a part description library, that occurrence of the child device will be aliased or associated with its parent device. An aliased child device inherits several traits from its parent, including the parent's name, replaceability attribute, testability attribute, SAFEGUARD attribute, backtrace attribute, device options, and (optionally) failure message. Except for a failure message, you should never specify any of these options for an aliased device. You can alias one child device per part description library.

NOTEIf you have one part description library inside another part description library, each of them can have one aliased device, etc.

This inheritance of traits has the following uses:

� It aids you in defining the internal analog characteristics of digital devices, which improves the accuracy of tests.

� It simplifies the entry of data in Board Consultant.

Each of these applications is individually described below.

Using InherFigure 8-3 called PK1.not a part dtest describfor PK1. Bumodeling th

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Chapter 8



Figure 8-3 Modeling a pull-up resistor inside a library device

Notice that PK1 has an internal pull-up resistor, r1, connected between the collector of an output transistor (which we will say is part of driver circuit driver_xyz) and power supply VCC.

Seen from an external viewpoint, PK1 looks like Figure 8-4.

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Chapter 8

for this device in the board file might look

erpt from board file

RARYN"pk1_internal"IONS

D



Figure 8-4 An external view of device PK1

Because of pull-up resistor r1 inside driver_xyz, it appears as if a 5K resistor is connected across pins 4 and 10 of device PK1. The resistor provides a shunt resistance across any external circuitry connected between VCC and pin 4 of PK1. If IPG does not know about the presence of r1, it may not be able to write an accurate test for circuitry external to PK1.

You can fix this problem by writing a part description library that describes the analog characteristics of PK1 as they relate to device driver_xyz. Suppose we call this library test pk1_internal. An excerpt from the

library entrylike this:

Example 8-7

! Exc!

PIN LIBpk1 P

CONNECT. . .NODE_

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Chapter 8

of traits, part description library will be identified as pk1 if it fails.

each external pins statement is followed ce statements�one for device * (the alias xyz) and one for a connection to resistor r1.

e, external pin 10 of parent device PK1 is o pin 1 of child device r1 and pin 4 of child ese descriptions show that resistor r1 is in

h pins on device *.

r a more specific failure message associated t description library�for example, to urately why PK1 fails�simply specify an lure message, like this:



pk1.4;. . .NODE_J

pk1.10;. . .

An excerpt from the corresponding part description library file (pk1_internal) might look like this:

Example 8-8

! Excerpt from part description library! "pk1_internal"

pin library *, pn"driver_xyz"! Notice the asterisk as a! device designator

. . .! in this example.resistor "r1", 5k, 5, 5, f, nt

. . .external pins 4

device "r1" pins 2device * pins 5



The use of an asterisk as a part designator aliases the name of this occurrence of child device driver_xyz with its parent device, PK1. The traits the part description library inherits from its parent include the parent's name and failure message. Because of this

inheritance driver_xyz

Notice that by two devifor driver_For examplconnected tdevice *. Thparallel wit

If you prefewith the paridentify accalternate fai

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Chapter 8

driver_xyz failed."

art description library contains the same you enter to describe devices, it provides a can use to keep from manually entering all nt information. Instead of repeatedly esistor R789 in the Resistor Device Entry an create a single part description library ply refer to it by name in the Pin Library

y Form. After you have done this, entering m�the name of the library device�in the Device Entry Form is equivalent to entering acteristics of the device in the Resistor y Form.

istor type R789 is denoted as r1 on a board . The library entry for r1/R789 in the board ok like this:



Example 8-9

! Excerpt from part description library!

pin library *, pn"driver_xyz", "Pullup resistor insideresistor "r1", 5K, 5, 5, f, nt





Simplifying Data Entry Creating a part description library for each part you use can greatly reduce the amount of data you must manually enter in Board Consultant (or in Board Forms). For example, suppose your company uses 500 different resistors to build its circuit boards. Each of these resistors has characteristics such as its nominal value, its plus and minus tolerances, and whether it is fixed or variable.

Suppose one of these resistors is type R789. Each time you use a type R789 resistor on a board, you must re-enter its characteristics�nominal value, fixed or variable, tolerances�in the Resistor Device Entry Form. If you use the same type R789 resistor 50 times on a single board (as a pull-up resistor, perhaps), you must describe its characteristics 50 times.

Because a pinformationshortcut youthis redundadescribing rForm, you cand then simDevice Entronly one itePin Librarythe full charDevice Entr

Suppose resto be testedfile might lo

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Chapter 8

me with this occurrence of the child device. s instance of the aliased child device inherit the parent device from the board file. The le now looks like this:

2

erpt from part description library

r *, 10, 5, 5, f! Notice the asterisk as a! device designator! throughout this example.

l pins 1e * pins 1l pins 2e * pins 2

y device fails, the cause will be accurately s r1.

is simple example showed a resistor, you method to reduce the amount of data other devices. The more complex the device, fort you can save by creating a part library for it.

ly will not want to create part description all devices, especially those that are lsewhere. For example, the description of a lator IC probably belongs in an analog

ibrary test, and not here.



Example 8-10


PIN LIBRARYr1 PN"R789"

CONNECTIONSNODE_A

r1.1;NODE_B

r1.2;

Initially, you might think the PDL file for the example should look like this:

Example 8-11

! Excerpt from part description library!

resistor "r1", 10, 5, 5, fexternal pins 1

device "r1" pins 1external pins 2

device "r1" pins 2

But describing resistor r1 this way causes a problem. A failing test will identify the cause of the failure as r1:r1; that is, this file describes a child device within a parent device, which does not match the real case of a single device with no internal devices.

To prevent this anomaly, enter an asterisk (*) instead of a device designator. The asterisk associates an alias or

alternate naThis lets thithe name ofcorrected fi

Example 8-1

! Exc!

resisto

externadevic

externadevic

If this libraridentified a

Although thcan use thisentered for the more efdescription

You probablibraries fordescribed evoltage regufunctional l

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Chapter 8

u also can make a part description library stable by specifying the nt option for each e the library. But then you can never test that ce. The best way to control the testability of vice is by modifying the testability of the e in the board file.

s on Nested Entriesription library can contain other library e nesting or layering of libraries within

es not exceed 16. For example, one part library can contain any number of library t those library devices may contain other ces, which may contain other library . This nesting of library entries must not evels.

triction on nesting is that you cannot use an to alias a part description library device that ther part description library. For example, g statement is not validy *, pn"part_description_library"

rt number (pn) references another part library. This restriction is necessary because its may cause problems when nested part libraries contain duplicate designators for



A Shortcut for Denoting Non-Testable DevicesSuppose you have created a part description library for a parent device that contains child devices that should not be tested. Perhaps you are using a part description library to model the internal characteristics of a device. Here, the part description library is used solely to improve the accuracy of tests of the surrounding circuitry and you do not want to test the library device itself.

The best way to denote an entire part description library as untestable is to specify NT for the parent device in the board file, which makes its contents (the child devices) non-testable. The following excerpt from a library entry in the board file shows NT used to declare a library device and its child devices as non-testable.

Example 8-13


PIN LIBRARYvr1 NT PN"LM_XYZ"

. . .

This global definition for testability in the board file overrides the individual definitions for testability in a PDL file. None of the child devices will be tested, but IPG will still use the characteristics of the child devices when writing other tests.

Note that yodevice untedevice insidlibrary devia library deparent devic

RestrictionA part descdevices if thlibraries dodescription devices. Bulibrary devidevices, etcexceed 16 l

Another resasterisk (*) is inside anothe followinpin librar

when the padescription inherited tradescription devices.

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Chapter 8

RefereDescr

an specify the bt (backtrace) option for a pin y, which enables backtracing for that library.

an specify that a pin on a child device is taneously connected to more than one pin on rent device�that is, you can manually y:ternal pins 1,2device "r1" pins 2"r1" connects to two external pins

scription Editor lets you specify only the ssociation between pins:ternal pins 1device "r1" pins 2"r1" connects to one external pin

tor keyword precedes a list of parameters Table 8-1 on page 8-18 that describes an apacitor.



nce iption of PDL

The following topics list the full syntax of the statements that comprise PDL. Because part description library files are automatically created whenever you use the Part Description Editor, you do not need to understand PDL syntax to this level of detail in order to use part description libraries.

The syntaxes below are shown in the same format used for the programming statements described in the Syntax Reference documentation. With the exception of items enclosed in quotes�that is, string constants�PDL syntax is case-sensitive. Thus, C1 and c1 are both valid, but NT is not a valid alternate for nt.

Additional Features for Manually Created PDL FilesThe values you enter in the Part Description Editor's data entry fields are automatically merged with PDL statements to create part description libraries. In most cases, this is the best way to create part description libraries. But manually creating PDL files in part mode provides several features that are not available when you use the Part Description Editor. The additional features are:

� You can specify the ns (no safeguard) option for a pin library, which disables SAFEGUARD checking for that library.

� You clibrar

� You csimulits paspecif

ex

! Pin 2 of

The Part Defollowing a

ex

! Pin 2 of

capacitorThe capacidescribed inindividual c

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Chapter 8

, <options>, <message>, <options>, <message>

y commas:

integration time"e inherit traits from parent device



Example 8-14

Syntax:capacitor <designator>, <value>, <+tol>, <-tol>, <type>capacitor <designator>, <value>, <+tol>, <-tol>, <type>capacitor <designator>, <value>, <+tol>, <-tol>, <type>capacitor <designator>, <value>, <+tol>, <-tol>, <type>capacitor *, <value>, <+tol>, <-tol>, <type>capacitor *, <value>, <+tol>, <-tol>, <type>, <message>

<designator> and <message> are <string constants><value>, <+tol>, <-tol> are <numeric constants>

<type> can be:

fv

<options> can be one or more of the following, separated bntnr

pn<part number><part number> is a <string constant>

Example:capacitor "c1", 10u, 10, 10, f, nrcapacitor "c23", 100p, 20, 20, v, pn"123-456", "Variescapacitor *, 100p, 20, 20, v! Asterisk lets child devic

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Chapter 8

ter them in part description libraries simply ntation purposes.

ample, c1. A <designator> cannot be longer

device, which lets it inherit traits from its parent on library.

pacitor value. Both are positive numbers.

r variable.

r.

pacitor is a child device inside a parent device a capacitor and its test fails, you will be told to the options default to nr.

your internal part number�of the capacitor. A nnot be longer than 24 characters.

cannot be longer than 40 characters.



connectorThe connector keyword precedes a list of parameters described in Table 8-2 on page 8-19 that describes an individual connector. Note that connectors are not

testable; enfor docume

Table 8-1 capacitor parameters

Parameter Description

<designator> A unique name that identifies a specific capacitor; for exthan 48 characters.

* Specifying an asterisk as a <designator> aliases a child device. You can alias one child device per part descripti

<value> The nominal value of the capacitor in farads.

<+tol>, <-tol> The plus and minus tolerances as percentages of the ca

<type> Can be f or v to denote whether the capacitor is fixed o

nt (no test) Instructs IPG not to write a test for the capacito

nr Denotes the capacitor as non-replaceable; that is, the caand cannot be individually replaced. If you specify nr forreplace its parent. If you leave the <options> field blank,

pn<part number> The part number�such as the vendor's part number or part number is used for reference purposes only and ca

<message> A message associated with the capacitor. A <message>

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Chapter 8

y commas:

ts from parent device.

xample, j10. A <designator> cannot be




Example 8-15

Syntax:connector <designator>connector <designator>, <options>connector <designator>, <message>connector <designator>, <options>, <message>connector *connector *, <message>

<designator> and <message> are <string constants>

<options> can be one or more of the following, separated bntnrpn<part number>

<part number> is a <string constant>

Example:connector "j5", nr, nt! Connectors cannot be tested.connector "j1", pn"A678", nt, "j1 located near PK2"connector * ! Asterisk lets child device inherit trai

Table 8-2 connector parameters


<designator> A unique name that identifies a specific connector; for elonger than 48 characters.

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Chapter 8

or. If you leave the <options> field blank, the

ed.

your internal part number�of the connector. A nnot be longer than 24 characters.

> cannot be longer than 40 characters.



diodeThe diode keyword precedes a list of parameters shown in Table 8-3 on page 8-21 that describes an individual diode.

nt (no test) Instructs IPG not to write a test for the connectoptions default to nt.

nr Because a connector is not testable, this option is not us


<message> A message associated with the connector. A <message

Table 8-2 connector parameters (continued)

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Chapter 8

>>>, <message>

y commas:

former t1"raits from parent device.

cr1. A <designator> cannot be longer than 48

vice, which lets it inherit traits from its parent library.



Example 8-16

Syntax:diode <designator>, <high value>, <low value>diode <designator>, <high value>, <low value>, <optionsdiode <designator>, <high value>, <low value>, <messagediode <designator>, <high value>, <low value>, <optionsdiode *, <high value>, <low value>diode *, <high value>, <low value>, <message>

<designator> and <message> are <string constants><high value>, <low value> are <numeric constants>

<options> can be one or more of the following, separated bntnrpn<part number><part number> is a <string constant>

Example:diode "cr1", ntdiode "cr2", .8, .4, pn"D123-3", "Located next to transdiode *, .8, .4 ! Asterisk lets child device inherit t

Table 8-3 diode parameters


<designator> A unique name that identifies a specific diode; for example,characters.

* Specifying an asterisk as a <designator> aliases a child dedevice. You can alias one child device per part description

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Chapter 8

cross the diode when it is forward biased.

cross the diode when it is forward biased.

child device inside a parent device and cannot test fails, you will be told to replace its parent.

nr.

r internal part number�of the diode. A part longer than 24 characters.

t be longer than 40 characters.



external pinsThe external pins keyword precedes a list of pins on a part description library device that are accessible via the fixture. Unless the external pin is denoted noconnect because it does not connect to anything, external pins is followed by a list of child devices and pins to which the external pin(s) connects. Parameters are shown in Table 8-4 on page 8-24

<high value> Specifies the upper test limit, in volts, for the voltage drop a

<low value> Specifies the lower test limit, in volts, for the voltage drop a

nt (no test) Instructs IPG not to write a test for the diode.

nr Denotes the diode as non-replaceable; that is, the diode is abe individually replaced. If you specify nr for a diode and itsIf you leave the <options> field blank, the options default to

pn<part number>

The part number�such as the vendor's part number or younumber is used for reference purposes only and cannot be

<message> A message associated with the diode. A <message> canno

Table 8-3 diode parameters (continued)

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Chapter 8

in name>

nt>

t device is connected.a child device.

he parent device arechild devices.



Example 8-17

Syntax:external pins<pin list>; noconnectexternal pins<pin list>

<device pin list>

<pin list> can be:<pin name><pin name>, . . . <pin name>

<device pin list> consists of: device <device name> pin <p<device name> is a <string constant><pin name> can be a <numeric constant> or a <string consta

Example:external pins 5 ! External pin 5 on the paren

device "r5" pins 2 ! to pin 2 on child device r5external pin 8; noconnect ! The pin does not connect toexternal pins 1, 20 ! External pins 1 and 20 on t

device "c3" pins 1 ! connected to pins on threedevice "cr1" pins "a"device "r9" pins 2

Notice that an external pins keyword can be followed by more than one <device pin list>. Each additional <device pin list> begins on a new line.

© Agilent T 8-24

Chapter 8

ptions>essage>ptions>, <message>

on a part description library device.

ot connected to anything inside the library

external pin.



fetThe fet keyword precedes a list of parameters shown in Table 8-5 on page 8-25 that describes an individual field-effect transistor.

Example 8-18

Syntax:fet <designator>, <high value>, <low value>, <type>fet <designator>, <high value>, <low value>, <type>, <ofet <designator>, <high value>, <low value>, <type>, <mfet <designator>, <high value>, <low value>, <type>, <ofet *, <high value>, <low value>, <type>fet *, <high value>, <low value>, <type>, <message>


<type> can be:

Table 8-4 external pins parameters


<pin name> The name or number of one or more external pins

noconnect Denotes the pin as accessible via the fixture but ndevice.

<device pin list> A list of pins associated with <device name>.

<device name> The identifier of a child device associated with the

© Agilent T 8-25

Chapter 8

y commas:

3"traits from parent device.

t transistor; for example, qf1. A <designator>

child device, which lets it inherit traits from its part description library.

el resistance (Ron).

el resistance (Ron).

channel or p-channel device.

T.

ET is a child device inside a parent device and for a FET and its test fails, you will be told to blank, the options default to nr.



np


Examples:fet "qf1", 200, 100, nfet "qf2", 300, 150, p, pn"234", "qf2 is located near jfet *, 300, 150, p ! Asterisk lets child device inherit

Table 8-5 fet parameters


<designator> A unique name that identifies a specific field-effeccannot be longer than 48 characters.

* Specifying an asterisk as a <designator> aliases aparent device. You can alias one child device per

<high value> Specifies, in ohms, the high test limit for the chann

<low value> Specifies, in ohms, the low test limit for the chann

<type> Can be n or p to denote whether the FET is an n-

nt (no test) Instructs IPG not to write a test for the FE

nr Denotes the FET as non-replaceable; that is, the Fcannot be individually replaced. If you specify nr replace its parent. If you leave the <options> field

© Agilent T 8-26

Chapter 8

er or your internal part number�of the FET. A nd cannot be longer than 24 characters.




fuseThe fuse keyword precedes a list of parameters shown in Table 8-6 on page 8-27 that describes an individual fuse.

pn<part number> The part number�such as the vendor's part numbpart number is used for reference purposes only a

<message> A message associated with the FET. A <message

Table 8-5 fet parameters (continued)

© Agilent T 8-27

Chapter 8

y commas:

raits from parent device.

xample, f1. A <designator> cannot be longer




Example 8-19

Syntax:fuse <designator>, <max current>fuse <designator>, <max current>, <options>fuse <designator>, <max current>, <message>fuse <designator>, <max current>, <options>, <message>fuse *, <max current>fuse *, <max current>, <message>

<designator> and <message> are <string constants><max current> is a <numeric constant><options> can be one or more of the following, separated b

ntnrpn<part number><part number> is a <string constant>

Example:fuse "f1", 2, nrfuse "f3", 1.5, pn"89-124", "Fuse for +5 volt supply"fuse *, 1.5 ! Asterisk lets child device inherit t

Table 8-6 fuse parameters


<designator> A unique name that identifies a specific fuse; for ethan 48 characters.

© Agilent T 8-28

Chapter 8

se.

use is a child device inside a parent device and for a fuse and its test fails, you will be told to blank, the options default to nr.

er or your internal part number�of the fuse. A nd cannot be longer than 24 characters.




inductorThe inductor keyword precedes a list of parameters shown in Table 8-7 on page 8-30 that describes an individual inductor.

<max current> The maximum permissible current in amps.

nt (no test) Instructs IPG not to write a test for the fu

nr Denotes the fuse as non-replaceable; that is, the fcannot be individually replaced. If you specify nr replace its parent. If you leave the <options> field

pn<part number> The part number�such as the vendor's part numbpart number is used for reference purposes only a

<message> A message associated with the fuse. A <message

Table 8-6 fuse parameters (continued)

© Agilent T 8-29

Chapter 8

ance>, <type>ance>, <type>, <options>ance>, <type>, <message>ance>, <type>, <options>, <message>e>e>, <message>

ts>

y commas:

ctor"rit traits from parent device.



Example 8-20

Syntax:inductor <designator>, <value>, <+tol>, <-tol>, <resistinductor <designator>, <value>, <+tol>, <-tol>, <resistinductor <designator>, <value>, <+tol>, <-tol>, <resistinductor <designator>, <value>, <+tol>, <-tol>, <resistinductor *, <value>, <+tol>, <-tol>, <resistance>, <typinductor *, <value>, <+tol>, <-tol>, <resistance>, <typ

<designator> and <message> are <string constants><value>, <+tol>, <-tol>, <resistance> are <numeric constan

<type> can be:

fv


Example:inductor "l1", 1.5, 5, 5, 10, finductor "l2", 20u, 10, 10, 2, v, "pn8A9", "Tuning induinductor *, 20u, 10, 10, 2, v! * lets child device inhe

© Agilent T 8-30

Chapter 8

xample, l1. A <designator> cannot be longer

ld device, which lets it inherit traits from its description library.

inductor value. Both are positive numbers.

or variable.

or.

nductor is a child device inside a parent device for an inductor and its test fails, you will be told lank, the options default to nr.

r your internal part number�of the inductor. A annot be longer than 24 characters.




Table 8-7 inductor parameters


<designator> A unique name that identifies a specific inductor; for ethan 48 characters.

* Specifying an asterisk as a <designator> aliases a chiparent device. You can alias one child device per part

<value> The nominal value of the inductor in Henries.

<+tol>, <-tol> The plus and minus tolerances as percentages of the

<resistance> The series resistance of the inductor in ohms.

<type> Can be f or v to denote whether the inductor is fixed

nt (no test) Instructs IPG not to write a test for the induct

nr Denotes the inductor as non-replaceable; that is, the iand cannot be individually replaced. If you specify nr to replace its parent. If you leave the <options> field b

pn<part number> The part number�such as the vendor's part number opart number is used for reference purposes only and c

<message> A message associated with the inductor. A <message

© Agilent T 8-31

Chapter 8

an internal node keyword can be followed n one <device pin list>. Each additional list> begins on a new line.

ant>pin name>

nt>

on between pin 1 of

ther the pins



Internal nodeThe internal node keyword specifies nodes within a part description library device that are not accessible via the fixture. Although these nodes are inaccessible, you must specify them so the part description library accurately describes the structure of a library device. Parameters are shown in Table 8-8 on page 8-32.

Notice that by more tha<device pin

Example 8-21

Syntax:internal node<node name>

<device pin list>internal node<node name>; nomanual

<device pin list>

<node name> can be a <numeric constant> or a <string const<device pin list> consists of: device <device name> pins <<device name> is a <string constant><pin name> can be a <numeric constant> or a <string consta

Example:internal node "c7r15" ! Internal node is a connecti

device "c7" pins 1 ! c7 and pin 2 of r15.device "r15" pins 2

internal node "c4c6r12r13" ! Internal node connects togedevice "c4" pins 1 ! on four devices.device "c6" pins 2device "r12" pins 2device "r13" pins 1

© Agilent T 8-32

Chapter 8

cription library device. This is a node that is not

nal node.

th <device name>.

that is, manual probing is not possible



jumperThe jumper keyword precedes a list of parameters shown in Table 8-9 on page 8-34 that describes an individual jumper.

Table 8-8 internal node parameters


<node name> The identifier of an internal node inside a part desaccessible via the fixture.

<device pin list> A list of pins associated with <device name>.

<device name> The identifier of a device associated with the inter

<pin name> The name (or number) of the pin(s) associated wi

nomanual Denotes the node as inaccessible to the operator;

© Agilent T 8-33

Chapter 8

y commas:

."traits from parent device.



Example 8-22

Syntax:jumper <designator>, <status>jumper <designator>, <status>, <options>jumper <designator>, <status>, <message>jumper <designator>, <status>, <options>, <message>jumper *, <status>jumper *, <status>, <message>

<designator> and <message> are <string constants>

<status> can be:

openclosed


Examples:jumper "jp1", closedjumper "jp2", open, nt, "Jumper will be installed laterjumper *, open ! Asterisk lets child device inherit

© Agilent T 8-34

Chapter 8

or these other library devices. Parameters are ble 8-10 on page 8-35

ample, jp1. A <designator> cannot be longer


mper when it is tested.

r.

mper is a child device inside a parent device for a jumper and its test fails, you will be told to k, the options default to nr.

r your internal part number�of the jumper. A annot be longer than 24 characters.




pin libraryThe library keyword precedes a list of component designators that identify other pin library devices that appear in a part description library. For example, a custom device called device1 might contain child devices that are library devices. Thus, the part description library for device1 must also include

identifiers fshown in Ta

Table 8-9 jumper parameters


<designator> A unique name that identifies a specific jumper; for exthan 48 characters.


<status> Can be open or closed to denote the status of the ju

nt (no test) Instructs IPG not to write a test for the jumpe

nr Denotes the jumper as non-replaceable; that is, the juand cannot be individually replaced. If you specify nr replace its parent. If you leave the <options> field blan


<message> A message associated with the jumper. A <message>

© Agilent T 8-35

Chapter 8

message>

stants>

k on PACKAGE1"inherit traits from parent device.

device. A <designator> cannot be longer than


.



Example 8-23

Syntax:pin library <designator>, pn<part number>pin library <designator>, pn<part number>, <message>pin library <designator>, <options>, pn<part number>pin library <designator>, <options>, pn<part number>, <pin library *, pn<part number>pin library *, pn<part number>, <message>

<designator>, <part number>, and <message> are <string con

<options> can be:btnrnsnt

Example:pin library "u1", nt, pn"7705"pin library "rp1", nr, pn"rpack_type123", "Resistor pacpin library *, pn"HYBRID2"! Asterisk lets child device

Table 8-10 pin library parameters


<designator> A unique name that identifies a specific pin library48 characters.


bt Denotes that backtrace is on for this library device

© Agilent T 8-36

Chapter 8

t is, the library device is a child device inside a . If you specify nr for a library device and its u leave the <options> field blank, the options

is, SAFEGUARD is disabled.

rary device.

ber or your internal part number�of the library ses only and cannot be longer than 24

message> cannot be longer than 40



potentiometerThe potentiometer keyword precedes a list of parameters shown in Table 8-11 on page 8-37 that describes an individual potentiometer.

nr Denotes the library device as non-replaceable; thaparent device and cannot be individually replacedtest fails, you will be told to replace its parent. If yodefault to nr.

ns Denotes no safeguard for this library device�that

nt (no test) Instructs IPG not to write a test for the lib

pn<part number> The part number�such as the vendor's part numdevice. A part number is used for reference purpocharacters.

<message> A message associated with the library device. A <characters.

Table 8-10 pin library parameters (continued)

© Agilent T 8-37

Chapter 8

ptions>essage>ptions>, <message>

y commas:

adjustment"it traits from parent device.

; for example, p1. A <designator> cannot be




Example 8-24

Syntax:potentiometer <designator>, <value>, <+tol>, <-tol>potentiometer <designator>, <value>, <+tol>, <-tol>, <opotentiometer <designator>, <value>, <+tol>, <-tol>, <mpotentiometer <designator>, <value>, <+tol>, <-tol>, <opotentiometer *, <value>, <+tol>, <-tol>potentiometer *, <value>, <+tol>, <-tol>, <message>

<designator> and <message> are <string constants><value>, <+tol>, <-tol> are <numeric constants><options> can be one or more of the following, separated b

ntnrpn<part number><part number> is <string constant>

Example:potentiometer "p1", 1M, 20, 20, nrpotentiometer "p2", 10k, 10, 10, nt, pn"R2A-34", "Gainpotentiometer *, 10K, 10, 10! * lets child device inher

Table 8-11 potentiometer parameters


<designator> A unique name that identifies a specific potentiometerlonger than 48 characters.

© Agilent T 8-38

Chapter 8

potentiometer value. Both are positive

iometer.

, the potentiometer is a child device inside a ou specify nr for a potentiometer and its test the <options> field blank, the options default to

r your internal part number�of the rposes only and cannot be longer than 24

ssage> cannot be longer than 40 characters.



resistorThe resistor keyword precedes a list of parameters shown in Table 8-12 on page 8-40 that describes an individual resistor.

<value> The nominal value of the potentiometer in ohms.

<+tol>, <-tol> The plus and minus tolerances as percentages of the numbers.

nt (no test) Instructs IPG not to write a test for the potent

nr Denotes the potentiometer as non-replaceable; that isparent device and cannot be individually replaced. If yfails, you will be told to replace its parent. If you leave nr.

pn<part number> The part number�such as the vendor's part number opotentiometer. A part number is used for reference pucharacters.

<message> A message associated with the potentiometer. A <me

Table 8-11 potentiometer parameters (continued)

© Agilent T 8-39

Chapter 8

<options><message><options>, <message>

y commas:

connector"nherit traits from parent device.



Example 8-25

Syntax:resistor <designator>, <value>, <+tol>, <-tol>, <type>resistor <designator>, <value>, <+tol>, <-tol>, <type>,resistor <designator>, <value>, <+tol>, <-tol>, <type>,resistor <designator>, <value>, <+tol>, <-tol>, <type>,resistor *, <value>, <+tol>, <-tol>, <type>resistor *, <value>, <+tol>, <-tol>, <type>, <message>


<type> can be:

fv


Example:resistor "r1", 4.7, 5, 5, fresistor "r2", 5k, 10, 10, v, pn"325-5", "Located nearresistor *, 5k, 10, 10, v! Asterisk lets child device i

© Agilent T 8-40

Chapter 8

ample, r1. A <designator> cannot be


ges of the resistor value. Both are positive

r variable.

r.

sistor is a child device inside a parent device or a resistor and its test fails, you will be told to k, the options default to nr.

r your internal part number�of the resistor. A annot be longer than 24 characters.




Table 8-12 resistor parameters


<designator> A unique name that identifies a specific resistor; for exlonger than 48 characters.


<value> The nominal value of the resistor in ohms.

<+tol>, <-tol> The plus and minus tolerances expressed as percentanumbers.

<type> Can be f or v to denote whether the resistor is fixed o

nt (no test) Instructs IPG not to write a test for the resisto

nr Denotes the resistor as non-replaceable; that is, the reand cannot be individually replaced. If you specify nr freplace its parent. If you leave the <options> field blan


<message> A message associated with the resistor. A <message>

© Agilent T 8-41

Chapter 8

ons>age>ons>, <message>

tants>

y commas:

pin 3ontactsor”stedinherit traits



switchThe switch keyword precedes a list of parameters (shown in Table 8-13 on page 8-42) that describe an individual switch.

Example 8-26

Syntax:switch <designator>, <common pin>, <contact pin>switch <designator>, <common pin>, <contact pin>, <optiswitch <designator>, <common pin>, <contact pin>, <messswitch <designator>, <common pin>, <contact pin>, <optiswitch *, <common pin>, <contact pin>switch *, <common pin>, <contact pin>, <message>

<designator>, <common pin>, and <message> are <string cons<contact pin> can be:

<contact pin>OFF

<contact pin> is a <string constant><options> can be one or more of the following, separated b

nrntpn<part number><part number> is a <string constant>

Example:switch "s1", "1", "3", nr ! Switch s1 closed, pin 1 toswitch "s1", "1", OFF ! Switch s1 open; no closed cswitch "s2", "1", "2", nt, pn"GH12-7A", "Channel select

! Switch s2 closed and not teswitch *, "1", "2" ! Asterisk lets child device

! from parent device.

© Agilent T 8-42

Chapter 8

ple, s1. A <designator> cannot be longer than


he switch is open) or the identifier of a pin to

cted during the test.

h is a child device inside a parent device and itch and its test fails, you will be told to replace

ions default to nr.

our internal part number�of the switch. A part be longer than 24 characters.

nnot be longer than 40 characters.



Table 8-13 switch parameters


<designator> A unique name that identifies a specific switch; for exam48 characters.


<common pin> Specifies the common pin in a switch.

<contact> Specifies the contact pin in a switch. This can be OFF (twhich the common pin is connected during the test.

<contact pin> The identifier of a pin to which the common pin is conne

nt (no test) Instructs IPG not to write a test for the switch.

nr Denotes the switch as non-replaceable; that is, the switccannot be individually replaced. If you specify nr for a swits parent. If you leave the <options> field blank, the opt

pn<part number> The part number�such as the vendor's part number or ynumber is used for reference purposes only and cannot

<message> A message associated with the switch. A <message> ca

© Agilent T 8-43

Chapter 8

pe>pe>, <options>pe>, <message>pe>, <options>, <message>

ge>

y commas:

mplifier"it traits from parent device.



transistorThe transistor keyword precedes a list of parameters shown in Table 8-14 on page 8-44 that describes an individual bipolar transistor.

Example 8-27

Syntax:transistor <designator>, <high value>, <low value>, <tytransistor <designator>, <high value>, <low value>, <tytransistor <designator>, <high value>, <low value>, <tytransistor <designator>, <high value>, <low value>, <tytransistor *, <high value>, <low value>, <type>transistor *, <high value>, <low value>, <type>, <messa


<type> can be:

np

<options> can be one or more of the following, separated bnrntpn<part number><part number> is a <string constant>

Example:transistor "q1", 200, 50, n, nrtransistor "q2", 100, 20, p, "pn1245-25", "Part of preatransistor *, 100, 20 ! Asterisk lets child device inher

© Agilent T 8-44

Chapter 8

r; for example, q1. A <designator> cannot be


an npn or a pnp device.

r.

nsistor is a child device inside a parent device a transistor and its test fails, you will be told to the options default to nr.

your internal part number�of the transistor. A nnot be longer than 24 characters.




zenerThe zener keyword precedes a list of parameters shown in Table 8-15 on page 8-45 that describes an individual Zener diode.

Table 8-14 transistor parameters


<designator> A unique name that identifies a specific bipolar transistolonger than 48 characters.


<high value> The upper test limit specified as a DC beta value.

<low value> The lower test limit specified as a DC beta value.

<type> Can be n or p to denote whether the bipolar transistor is

nt (no test) Instructs IPG not to write a test for the transisto

nr Denotes the transistor as non-replaceable; that is, the traand cannot be individually replaced. If you specify nr forreplace its parent. If you leave the <options> field blank,


<message> A message associated with the transistor. A <message>

© Agilent T 8-45

Chapter 8

<message>

y commas:

r transformer"it traits from parent device.

example, ds1. A <designator> cannot be




Example 8-28

Syntax:zener <designator>, <value>, <+tol>, <-tol>zener <designator>, <value>, <+tol>, <-tol>, <options>zener <designator>, <value>, <+tol>, <-tol>, <message>zener <designator>, <value>, <+tol>, <-tol>, <options>,zener *, <value>, <+tol>, <-tol>zener *, <value>, <+tol>, <-tol>, <message>


<options> can be one or more of the following, separated bnrntpn<part number><part number> is a <string constant>

Example:zener "ds1", 5.6, 5, 5, nrzener "ds2", 8.2, 10, 10, pn"z89-1", "Located near powezener *, 8.2, 10, 10 ! Asterisk lets child device inher

Table 8-15 zener parameters


<designator> A unique name that identifies a specific Zener diode; forlonger than 48 characters.

© Agilent T 8-46

Chapter 8

es of the Zener value. Both are positive

ode.

Zener diode is a child device inside a parent nr for a Zener diode and its test fails, you will

ield blank, the options default to nr.

your internal part number�of the Zener diode. annot be longer than 24 characters.

e> cannot be longer than 40 characters.



<value> The nominal value in volts.

<+tol>, <-tol> The plus and minus tolerances expressed as percentagnumbers.

nt (no test) Instructs IPG not to write a test for the Zener di

nr Denotes the Zener diode as non-replaceable; that is, thedevice and cannot be individually replaced. If you specifybe told to replace its parent. If you leave the <options> f

pn<part number> The part number�such as the vendor's part number or A part number is used for reference purposes only and c

<message> A message associated with the Zener diode. A <messag

Table 8-15 zener parameters (continued)

© Agilent T 1-1

P Q R S T U V W X Y Z

FET, 1-39 fuse, 1-41 jumper, 1-45 node library, 1-47 pin library, 1-49 potentiometer, 1-52 resistor, 1-54 switch, 1-56 transistor, 1-58 Zener, 1-60n inductor, 1-43tions, 1-21information, specifiying, 1-68entry errors, 1-11ions, 1-25ower supply nodes, specifying, 1-28, 1-29tions, editing, 1-14 assigning, 1-30, 1-8an optional file, 1-13, 1-8ectories, specifying, 1-32 device options, 1-321-4

vices, 1-68


Numerics A B C D E F G H I J K L M N O

IndexIndexIndexIndex

AAdditional Board Voltage, 1-19additional features in PDL, 8-16aliasing

child devices with parent devices, 8-9asterisk (*)

used to alias child devices with parent devices, 8-9autofile

fixture file syntax, 5-6, 5-14

Bbcf syntax, 1-6board configuration format syntax (BCF), 1-6board file

associating a failure message with a node, 1-62card options, 1-28critical pins, specifying, 1-67dangling pins, 1-67defaults, 1-9defining a capacitor, 1-34defining a connector, 1-36defining a diode, 1-38

defining adefining adefining adefining adefining adefining adefining adefining adefining adefining adefining adevice opdisabling duplicate family optfixed or pglobal opGP relay,identifiersincluding keywordslibrary diroverridingoverview,parent de

© Agilent T 1-2

Index


ing a test for test generation, 3-4

1-67

the log records, 6-1t description libraries as untestable, 8-15shold, 5-6

test generation in the �testorder� file, 3-4

defaults file, 7-2, 7-5

faults file, 7-3rd_defaults file syntax, 7-5

s, 5-38ers, 5-5, 5-13

lts, 5-51

echnologies 2001 Agilent 3070 / 79000 Data Formats


preconditioning, 1-68specifying a heading, 1-13specifying connections to device pins, 1-66, 1-67symbols, 1-6translating device pin names with a pin map, 1-63unconnected pin, identifying, 1-65undefining devices, 1-62

board placementboard_xy file syntax, 2-10

board.o filelisting the object file, 1-3, 2-3

board_defaults file, 7-2, 7-3board file usage, 1-9

board_xy fileincluding another file, 2-10scaling the input coordinates, 2-9specifying a board keepout area, 2-13specifying a board outline, 2-11specifying alternate node locations, 2-14specifying bottom side devices, 2-26specifying the board placement, 2-10

boundary scan chainsboard file, 1-76

CCAD Format Translator

duplicate entry error in the board file, 1-11operation on the board �file�, 1-9

commentcomment

Ddangling pin,

dataloggingformat of

denoting parDensity Thredevice test

controlling

Eedge_board_

Ffile

board_deedge_boa

fixtureelectronicpart numb

fixture defaufixture file

© Agilent T 1-3

Index


f traits in part description libraries, 8-9odel devices, 8-9

implify data entry, 8-13og records, 6-11

-6

specifying a board keepout area, 2-13s a fixture keepout, 5-15

orce, 5-6-2, 6-9g, 6-116-3teps in, 6-14rmatting, 6-16aracters in, 6-16

, 6-14ed, 6-15

-18



board keepout area, 5-21board outline, 5-19board placement, 5-19describing board attributes, 5-6describing fixture attributes, 5-5, 5-11fixture keepout areas, 5-15including another file, 5-15, 5-18tooling holes, 5-20top side electrical probing, enabling, 5-13

Fixture Handler, 5-5fixture keepout areas

specifying, 5-15Fixture Size, 5-5fixture templates, 5-51Fixture Type, 5-5fixture.o, 5-3fixture_defaults.o, 5-52Flash ISP, 6-58formatting log records, 6-16

HHeavy Probe Force, 5-6hierarchy

of log records, 6-9HOLES, 5-6holes

fixture file syntax, 5-16

Iinheritance o

used to mused to s

interpreting l

KKEEPOUT, 5keepout area

syntax of keepout area

specifying

LLight Probe Flog record, 6

hierarchyinterpretinprefixes,process srules of fospecial chtruncateduser-defin

log recordsA-CAP, 6

© Agilent T 1-4

Index


2USTER, 6-63

64-6566

86916-73

36-750

2334

5-6

-1, 2-1, 3-1, 4-1, 5-1, 6-1, 7-1, 8-1



A-DIO, 6-19A-FUS, 6-20AID, 6-32A-IND, 6-21A-JUM, 6-22ALM, 6-33A-MEA, 6-23A-NFE, 6-24A-NPN, 6-25A-PFE, 6-26A-PNP, 6-27A-POT, 6-28A-RES, 6-29ARRAY, 6-34A-SWI, 6-30A-ZE, 6-31BATCH, 6-35BLOCK, 6-37BS-O, 6-39BS-S, 6-40BT-DIAG, 6-45BTEST, 6-41BT-FAULT, 6-47BT-FD, 6-48BT-NOD, 6-50CCHK, 6-51DPIN, 6-52, 6-53D-T, 6-57GROUP, 6-58INDICT, 6-59LIM2, 6-61

LIM3, 6-6MAGICCLNETV, 6-NODE, 6PCHK, 6-PF, 6-67PIN, 6-68PRB, 6-6RACT, 6-REP, 6-7RETEST,RPT, 6-7S-PROC,TJET, 6-8TS, 6-81TS-D, 6-8TS-O, 6-8TS-P, 6-8TS-S, 6-8

MMetric Units,

Oobjectives, 1

© Agilent T 1-5

Index


l, 6-57scription of PDL, 8-16n nested entries in part description libraries, 8-15oardthe board_xy file, 2-10

ius, 1-21cters

ords, 6-16

testplan generation in the �testorder� file, 3-8terials, 1-1, 2-1, 3-1, 4-1, 5-1, 6-1, 7-1, 8-1 records, 6-14

les, 6-15



PPart Description Language

overview, 8-2reference description, 8-16syntax, 8-2

part numberfixture, 5-5

PDL -- See Part Description Languagepermanent

marking a test permanent, 3-4personality pin

connected nodes in the fixture file, 5-24, 5-40pin mapping

board file, 1-9Precondition Levels, 1-18preconditioning

board file syntax, 1-68prefix

for log records, 6-3prerequisites, 1-1, 2-1, 3-1, 4-1, 5-1, 6-1, 7-1, 8-1probe plate

fixture file syntax for specifying holes, 5-16process

steps in log records, 6-14

RRecords

test digitareference derestrictions orotating the b

syntax in

SShorting Radspecial chara

in log rec

Ttestplan

enabling tools and matruncated log

Uuser-definab

log record

Wwirelist.o file

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