Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic...

download Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction

of 20

  • date post

    22-Dec-2015
  • Category

    Documents

  • view

    213
  • download

    0

Embed Size (px)

Transcript of Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic...

  • Slide 1
  • Dale & Lewis Chapter 5 Computing components
  • Slide 2
  • Lets design a computer Generic CPU with registers Program counter (PC) 5 bits (size of addresses) Instruction register (IR) 8 bits (op code + address) Memory Address Register (MAR) 5 bits Main Memory Memory Data Register (MDR) 8 bits (byte addressable) Accumulator (A or Acc) 8 bits
  • Slide 3
  • Instructions Instruction format: 3-bit op code, 5-bit address Instructions and their op codes op codeInstruction 000 HALT (HLT) 001 LOAD (LDA) 010 STORE (STA) 011 ADD (ADD) 100 SUBTRACT (SUB) 101 BRANCH (BR) 110 BRANCH ON ZERO (BRZ) 111 BRANCH ON POSITIVE (BRP)
  • Slide 4
  • Types of instructions Data movement Move data between memory and CPU Move data between different memory locations Input, output Arithmetic and logic operations Integer arithmetic Comparing two quantities Shifting or rotating bits in a quantity Testing, comparing and converting bits Program control Starting a program Halting a program Skipping to another location Testing data to decide whether to skip to another instruction
  • Slide 5
  • Instructions LOAD instruction (LDA) PC MAR MDR IR IR [address] MAR MDR A PC + 1 PC ADD instruction (ADD) PC MAR MDR IR IR [address] MAR A + MDR A PC + 1 PC STORE instruction (STA) PC MAR MDR IR A MDR IR [address] MAR PC + 1 PC HALT instruction (HLT) PC MAR MDR IR stop FETCH DECODE GET DATA EXECUTE
  • Slide 6
  • FETCH Address of next instruction is transferred from PC to MAR and the instruction is located in the memory
  • Slide 7
  • FETCH Instruction is copied from memory to the MDR
  • Slide 8
  • DECODE Decode the instruction
  • Slide 9
  • EXECUTE Execute the instruction control unit sends signals to appropriate devices to carry out execution of the instruction
  • Slide 10
  • A small computer program LOADA 0010000101000 ADDB 0010101101001 STOREC 0011001001010 HLT 0011100000000 ADATA+5 0100000000101 BDATA-3 0100111111101 CDATA 01010 Program Assembly language Main memory Address Contents op code Data
  • Slide 11
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents PC IR Acc MAR MDR CPU
  • Slide 12
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00100 PC IR Acc MAR MDR CPU The program starts
  • Slide 13
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00100 00101000 PC IR Acc MAR MDR CPU Fetch 1 st instruction
  • Slide 14
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00100 00101000 00100 00101000 PC IR Acc MAR MDR CPU Decode 1 st instruction: LOAD A
  • Slide 15
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00100 00101000 00000101 01000 00000101 PC IR Acc MAR MDR CPU Execute1 st instruction: LOAD A
  • Slide 16
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00101 00101000 00000101 01000 00000101 PC IR Acc MAR MDR CPU Advance PC
  • Slide 17
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00101 00101000 00000101 00101 01101001 PC IR Acc MAR MDR CPU Fetch 2 nd instruction
  • Slide 18
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00101 01101001 00000101 00101 01101001 PC IR Acc MAR MDR CPU Decode 2 nd instruction: ADD B
  • Slide 19
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00101 01101001 100000010 01001 11111101 PC IR Acc MAR MDR CPU Execute 2 nd instruction: ADD B
  • Slide 20
  • 00000 00001 00010 00011 0010000101000 0010101101001 0011001001010 0011100000000 0100000000101 0100111111101 01010 01011 01100 01101 etc AddressContents 00110 01101001 00000010 01001 11111101 PC IR Acc MAR MDR CPU Advance PC, etc