DAC2000

Elektor Electronics 11/99

This brand-new digital-to-analogue converter (DAC) is intended especially for those audio enthusiasts who wish to have their audio sys-

tem fully up to date at the beginning of the new millennium. The 24-bitresolution and the top sampling rate of 96 kHz ensure that full advantage

can be taken of the qualities of the latest compact discs (CDs) and digi-tal video discs (DVDs).

58

Design by T Giesberts

for perfectionists

audio DAC 2000Part 1

AUDIO & HI-FI

I N T R O D U C T I O NOver the past few years there havebeen quite a few developments in digi-tal audio engineering. Although qual-ity-conscious audio enthusiasts gener-ally welcome these developments,many of them wonder if there will everbe an end to their having to updateand adapt their systems. It is, therefore,perfectly understandable that the qual-ity DACs published in this magazineover the past seven years or so haveproved very popular. After all, when itcomes to re-evaluating a digital audiosource, it is much simpler to updatejust the DAC and not the entire system.Moreover, a stand-alone DAC has theadvantage that it is universal and canbe combined with any CD/DVD playeror digital tape recorder.

The Audio DAC 2000 is intended forthe new millennium: it has a 24-bit res-olution and is suitable for samplingrates of 32–96 kHz. These propertiesmake it state of the art as far as tech-nology is concerned, while the designof the practical circuit is aimed at qual-ity without compromise.

Some enthusiasts may wonder whyhigher sampling rates have not beencatered for. The answer to this is that itis questionable whether higher rateswill ever be implemented. Althoughthe new 192 kHz standard is written,pundits reckon that it will take quite a

few years before thehardware and softwarewill become commer-cially available.

D E S I G NThe circuit is contained on four indi-vidual printed-circuit boards: one forthe ±12 V and +5 V power supplies;one for the digital audio receiver withdisplay driver; one for a 2-digit LEDdisplay; and one for the digital/ana-logue circuits, the digital filter, theDACs and the analogue output stage.Its block diagram is shown in Figure 1.

The power supplies comprise a+5 V section for the digital circuits(receiver and digital filter) and a ±12 Vsection for the analogue output sec-tion, including the associated relays.There is also a ±5 V supply, derivedfrom the ±12 V supply for the DACs.

The digital audio receiver is associ-ated with a sampling rate display,hardware control, and reference clock.

The display consists of two 7-seg-ment LED modules for indicating thesampling rates: 32 kHz, 44 kHz (in real-ity 44.1 kHz), 48 kHz, 88 kHz (in reality88.2 kHz), or 96 kHz.

The hardware control is primarily acircuit for setting the receive mode viaa 4-pole dual-in-line (DIP) switch.

The reference clock is an accuratecrystal oscillator operating at

6 . 1 4 4 M H zwhich is used bya comparator inthe receiver todetermine the

frequency of the received clock – aphase-locked loop, PLL.

The data that indicate the samplingrate, and the most important receivedchannel-status bits (strictly speakingonly the emphasis bit) are multiplexedby the receiver.

The data are demultiplexed by aGeneric Array Logic – GAL™ – whichalso drives the display. As far as themultiplexed data is concerned, they aretranslated and passed to the outputs ofthe registers. This prevents additionalswitching lines coming into being: amultiplexed display would demandquite a high current.

In normal operation, the outputs ofthe GAL are static. A number of linksneeded for the display are alreadyinterconnected so as to keep the num-ber of requisite outputs to a minimum.

The link between the digital audioreceiver and the display is made by alength of 10-core flatcable, and thatbetween the receiver and DAC boardby 16-core flatcable. The 16-core cablealso carries the +5 V supply and vari-ous signals to and from the digital fil-ter: serial audio data, power on reset,de-emphasis, mute, and switching. The

59Elektor Electronics 11/99

I / U

Converter

(2x OPA627)

4

Reset

Mute

Double Bandwidth

De-emp.

24-Bit

Sign-MagnitudeAudio DAC

(2x PCM1704)

26 / 42 kHzThird-orderLowpass

Post Filter

(2x OPA627)

3

3

12

SamplingFrequency

Display

HardwareControl

DigitalPower Supply

3

HardwareControl

4

HardwareControl

Coax

Optical

ReferenceClock

+5VAnalog

Power Supply

+12V

Analog(DAC)

Power Supply

+5V

-12V -5V 990059 - 11

L

R

24-Bit32...96 kHz

DigitalAudio

Receiver(CS8414)

24-Bit8x oversampling

DigitalInterpolation

Filter(DF1704)

1

Figure 1. The block diagramof the Audio DAC 2000clearly shows the designand what are the mostimportant parts of the unit.

™ GAL is a trademark of National Semiconductor Corporation.* Sony/Philips Digital Interface Format

switching signals almost double thebandwidth of the filter when samplingrates of 88.2 kHz or 96 kHz aredetected.

The mute signal is actuated whenthere is no signal at the receiver inputor when the PLL cannot lock. It istaken from the error output (pin 5 –ERF) of IC1 and used to de-energizethe output relay and to switch the dig-ital filter to the mute mode.

The reset pulse for the receiver anddigital filter is generated by networkR6-C13 and inverted by the GAL.

The de-emphasis signal is used bythe digital filter to correct the pre-emphasis in the source signal. TwelveDIP switches determine the varioussettings of the filter as regards theinput and output formats, the numberof bits, the filter characteristic, and oth-ers.

The digital filter drives two DACchips: one for the lefthand and one forthe righthand channel. These chips canbe set by hardware which will bereverted to later.

The output of each of the DACs is apure current source. The type specifiedwas chosen in view of its well-definedvoltage, good linearity, low noise, lowoffset voltage and high slew rate. It isnot cheap, but ideally suited to the pre-sent application.

The analogue filter at the output isneeded to remove the residue of theoversampling products and the r.f.noise. It can be switched between twocut-off frequencies to allow the use ofthe two highest sampling rates.

Each filter section uses a double-pole relay, since a single-pole type forboth channels would not give the req-uisite channel separation at high fre-quencies. This is because the RC sec-tions of the filters have too high animpedance.

Since the output impedance perchannel is only 100 Ω, a single double-pole relay is used at the output toswitch the mute function on/off and toobviate switch-on noises.

C I R C U I T D E S C R I P T I O NThe circuit diagram of the Audio DAC2000 is shown in Figure 2.

An important task of the circuit isthe decoding of the S/PDIF* data flowinto a serial data format that can beused by the DACs, which is carried outby IC1. The circuit associated with thischip is housed on a discrete board sothat the coaxial and optical input con-nectors can be placed in the most con-venient position on the enclosure.

The input impedance, which hasthe traditional value of 75 Ω as far asthe coaxial input is concerned, is deter-mined by resistor R1.

The optical input is provided byIC2, which is a standard chip used forthis purpose in consumer equipment.

The output of the ICis applied to theinput of IC1 viapotential dividerR1-R2, whose valuesare chosen such that the signal acrossR1 is slightly larger (0.6 V) than thestandard one from the coaxial input(0.5 V). The 0.1 µF coupling capacitorprevents any d.c. on the input fromreaching the receiver.

When the optical input is used,jumper JP1 must be shorted, and thecoaxial input cannot be used. It is then,

however, possible touse the coaxial inputas S/PDIF* output.In this case, the out-put impedance and

signal levels are no longer standard,but the latter may be increased byslightly reducing the value of resistorR2. In fact, the level of the input signalacross R1 may be as high as 1 Vp-pwithout any problems.

The IC uses a number of frequencysensors to ensure that the PLL locks asrapidly as possible to the incoming

60 Elektor Electronics 11/99

1 2

3 4

5 6

7 8

9 10

K2

1 2

3 4

5 6

7 8

9 10

11 12

13 14

K3

15 16

22V10RESET

DEEM

IC5

MUTE

OUT2

OUT4

OUT6

OUT5

OUT3

OUT1CLK

GALRST

SEL

ERF

DBW

23

21

19

17

16

18

20

22F2

F1

F0

10

11

14

15

24

12

13

1

2

3

7

8

9

4

6

5

CS8414

SDATA

FSYNC

IC1

FILT

VERF

FCK

RXP

RXN

SEL

SCK

MCK

CBL

ERF

21

22

13

10

20

16

17M3

18M2

24M1

23M0

12

19

15

14

26

11

27F2

F1

F0

E2

E1

E0

2528

7

8

AD

D A

9

C1

U

2

3

4

5

6

1 2

3

IC4a≥1

5 4

6

IC4b≥1

9 10

8

IC4c≥1

13 12

11

IC4d≥1

S1

R922Ω

R822Ω

R1022Ω

R722Ω

R5

4x 10k

1

5

4

3

2

C1

10n

C2

10n

C3

68n

C11

100n

C5

47n

C7

47n

R3

470Ω

R1

75

Ω

R2

22

0Ω

JP1

TORX173

IC2

3

2 4

1

5 6

C8

100n

C9

100n

L2

47µ

K1

L3

47µ

L4

47µ

C10

10µ 63V

C6

10µ 63V

C4

10µ 63V

C15

100n

C14

47µ 25V

L1

47µ

R4

4Ω

7

C13

47µ 25V

R6

10

k

SG531P

IC3

OSC

OE

1

5

4

8

IC4

14

7

C12

100n

B1

B80C1500

C89 C86

C88 C87

R58

1Ω5

C85

1000µ25V

C83

10µ63V

C84

100n

C82

100n

K13

K12R57

3k

9

D7

POWER

B2

B80C1500

C81 C78

C80 C79

R55

3Ω3

C76

1000µ40V

C72

10µ63V

C74

100n

C70

100n

R56

3Ω3

C77

1000µ40V

C73

10µ63V

C75

100n

C71

100n

K11

K10

IC4 = 74HCT32

S/PDIF

5V

5V

5V5V

5V

5V

5V

5V

5V

+5V

9V

15V

15V

5V

12V

12V

4x 22n

4x 22n

RST

6.144MHz

*7805

IC17

7812

IC15

IC16

7912

Figure 2. Circuit diagram ofthe Audio DAC 2000. Thedashed lines show how thecircuit is divided on to thefour boards.

data flow. In the absence of an inputsignal, the frequency of the voltage-controlled oscillator (VCO) is low.

The digital filter on the DAC boardneeds four signals, all derived from theincoming S/PDIF data by the receiverchip:

SDATA contains the serial data ofboth channels.

PSYNC is the lefthand/righthandclock to separate the samples for thetwo channels. Depending on the modeof operation, it is equal to the sampling

rate, Fs, or twice that rate.Serial clock SCK is needed for clock-

ing the individual bits and is equal to64Fs.

MCK, a clock equal to 256Fs,whichis needed for oversampling and inter-polation. Resistors R7–R10 limit anyringing caused by the capacitive loadsformed by the flatcable and the digitalfilter.

These four signals can be providedby the receiver in various standard for-mats: which one is determined by

mode pins M0–M3. Details of this canbe found in the CS8414 data sheetselsewhere in this issue.

The recommended mode is the I2Smode, since in this the number of bitsis basically not fixed: it may be 16-bitdata or 24-bit. Because of this, the pre-ferred setting of DIP switch S1 is S1–4ON (M1=1) and the remainder OFF(M0=M2=M3=0). Note that on theswitch M0–M3 are mixed up but on theboard the relevant names are adjacentto them (as is the level at ON or OFF).

Other formats are often just as they


MC/LRIP

ML/RESV

DF1704

MD/CKO

BCKIN

LRCIN

WCKO

BCKO

IC6

CLKO

MODE

MUTE

DEM

SF0

SRO

I2S

IW0

DIN

XTI

XTO

RST

DOR

DOL

IW1

OW1

SF1

OW0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1

2

3

4

56

7

8

9

2x

1 2

3 4

5 6

7 8

9 10

K4

12

34

56

78

910

1112

1314

K5

1516

820Ω

820Ω

820Ω

R18

820Ω

820Ω

820Ω

R24

820Ω

820Ω

820Ω

820Ω

R11

820Ω

820Ω

820Ω

R17

820Ω

S3

S4S2

C16

10µ 63V

C17

100n

LD1

dp

CA CA

10

7a6

b4

c2

d1

e

f9

g

8 3

5

HDN1075

LD2

dp

CA CA

10

7 a6

b4

c2

d1

e

f9

g

3 8

5

R25

2k49

R30

3k57

R31

3k65

R32

3k32

R27

3k57

R28

4k12

R29

3k92

C23

2x 47µ

C24

C19C184µ763V

C22

100µ25V

2x

SERVO DC

PCM1704

REF DC

BPO DC

INVERT

20BIT

IOUT

BCLK

IC7

–VDD

+VDD

–VCC

+VCC

WCLK

DATA

AGND

AGND

DGND

14

20

11

17

12

15

16

10

4

6

2

7

1 19

9

5

SERVO DC

PCM1704

REF DC

BPO DC

INVERT

20BIT

IOUT

BCLK

IC8

–VDD

+VDD

–VCC

+VCC

WCLK

DATA

AGND

AGND

DGND

14

20

11

17

12

15

16

10

4

6

2

7

1 19

9

5

C21C204µ763V

2x

C40C394µ763V

C43

100µ25V

2x

C44

2x 47µ

C45

C42C414µ763V

2x

C25

47p

OPA627

IC9

2

3

6

7

4

1

5 OPA627

IC10

2

3

6

7

4

1

5

Re2

C27

2n2

C28

4n7

C29

330p

C31

1n5

C30

1n

C32

270p

R40

100Ω

K6

C46

100n

C47

100n

C48

100n

C49

100n

25V

R26

2k49

R36

3k57

R37

3k65

R38

3k32

R33

3k57

R34

4k12

R35

3k92C26

47p

OPA627

IC11

2

3

6

7

4

1

5 OPA627

IC12

2

3

6

7

4

1

5

Re3

C33

2n2

C34

4n7

C35

330p

C37

1n5

C36

1n

C38

270p

R42

100Ω

K6

C50

100n

C51

100n

C52

100n

C53

100n

Re1

R39

1M

R411

M

K9

25V

C68

100µ25V

C66

100n

LM317

IC13

C69

100µ25V

C67

100n

R51

24

9Ω

R53

24

9Ω

R52

75

0Ω

R54

75

0Ω

LM337

IC14

C64

10µ 63V

C65

10µ 63V

C62

10µ63V

C60

100n

C63

10µ63V

C61

100n

D5

5V61W3

D6

5V61W3

R47

15

0k

R48

15

0k

R49

1M

R50

4Ω

7

C57

470µ25V

D3

1N4148T2

BC517

C56

1µ63V

R43

15

0k

R44

15

0k

R45

1M

R46

10

Ω

C55

220µ25V

D2

1N4148T1

BC517

C54

47µ25V

JP2

K8

C58

100µ25V

C59

100n

D4

5V61W3 JP3

L

R

12V

12V

12V

12V

5VA

5VA

5VD

5VD

5VD

DBW

MUTE

DBW

5VA

5V

5V

12V

12V

12V

12V

12V

12V

12V

12V

DBW'

MUTE'

D1

1N4001

12V 12V

VDBWVMUTE

VDBW

VMUTE

VDBW

5V

5VD

990059 - 12

5VA

A

A

5VA

* *

zie tekst*see text*siehe Text*voir texte*

G

D

are named, for instance, ‘MSB firstright justified’, whereby the location ofthe least significant bit (LSB) is fixedwith respect to the L/R clock. The resultof this is that some most significant bits(MSBs) may be missing. In the I2Smode, the location of the MSB is fixed,so that, assuming there are more bits,only some LSBs may be 0. Some of theother formats are fully compatible withthe Burr Brown digital filter, but that isleft to the reader to sort out if he/she sowishes.

The various modes have been madepresettable on purpose in view offuture extension/expansion/upgrade orother applications. It also enables thereceiver board to be used with otheraudio DACs. This board therefore hasan extra +5 V terminal: the 5 V line islinked to it from the DAC board via K3.

The manufacturers recommendresetting the IC immediately after apower up, for which purpose a circuitwith four OR gates contained in IC4 isused. This circuit cannot be providedin the GAL used, since this would

require four additional inputs and fouroutputs.

The IC is reset when all mode pinsare made high, which is the reason thatthe DIP switch is linked to the modeinput via the OR gates. The resetproper, which is also applied to thedigital filter on the DAC board via theGAL, is provided by network R6-C13.

The reference frequency of6.144 MHz which the receiver needs todetermine the sampling rate is pro-vided by crystal oscillator IC3. The out-put pin of this IC is located very closeto the relevant input (FCK) of IC1 tominimize the noise level of the clocksignal. The supply lines are well decou-pled by network L3-C10-C11.

The supply lines to all ICs aredecoupled effectively: those to the ana-logue and digital sections of IC1 sepa-rately.

Channel status output C, User bitoutput U, and Validity and ERror FlagVERF are not used.

The Channel status BLock (CBL)start is used to demultiplex the channel

status output bits (pins 2–6 and 27) bylinking these to select pin SEL. WhenSEL is low, the Error Condition (notused) and Frequency Reporting Bitsare applied to the outputs, which arethen called E0–E2 and F0–F2 respec-tively. When SEL is high, the ChannelStatus is applied to the relevant out-puts in the shape of some status chan-nel bits, whereupon the outputs arecalled C0 and Ca–Ce. Of these, only Cc(F0) is used, which is channel status bitC3. In fact, this is the emphasis bit ofthe channel status. It is inverted by theGAL and retained via a register output,which therefore retains the actual leveland does not follow SEL. The CBL out-put is therefore linked to an input ofthe GAL to demultiplex the data.

When SEL is low, bits F0–F2 arerecoded to six register outputs to drivea 2-digit LED display. Various segmentsof the display are already combined sothat, without the need of multiplexing,only six outputs are needed to displaythe five sampling frequencies on two7-segment displays (7 mm types). Theonly compromise is that any valueafter the decimal point (rate in kHz) isomitted.

The six outputs, +5 V, and earth, arelinked to the display board via K2, a10-core flatcable, and a 10-pin connec-tor. Owing to its height and locationbehind the front panel, a box headercannot be used on this board.

When ERF is active, all display out-puts are high and only two dashes(hyphens) light. Both g-segment LEDsare permanently linked to earth via R17and R24 respectively and thereforelight permanently as long as there issupply voltage.

The SCK clock (pin 1 of the GAL) isused to clock all register outputs.

The information on the actual sam-pling rate is used not only for drivingthe frequency display, but also forswitching the cut-off frequency of theanalogue output filter to a highervalue. That is, output DBW (doublebandwidth) goes high when a rate of88.2 kHz or 96 kHz is detected.

De-emphasis output DEEM isapplied to the digital filter only. Anindication of this is purposely not pro-vided since CDs with pre-emphasis arevery rare indeed. However, since thefacility is there, it is used in the AudioDAC 2000 for correcting any pre-emphasis, particularly so since there isnow no need for an additional RC net-work in the analogue output output fil-ter (both channels).

[990059]

Next month’s instalment describes theDAC board with particular emphasis onthe digital filter and the DACs.


96 kHz Digital AudioReceiver Type CS8414The Type CS8414 is an upgraded version of Digital Audio Receiver TypeCS8412, which has been used in several past articles published in this mag-azine. It is pin-compatible with its predecessor, but is available in a 28-pin SOIC(standard SMD) case only. A data sheet of it can be found elsewhere in thisissue.

The most notable difference between the two devices is that the range ofsampling rates available with the CS8414 has been extended to 96 kHz. The fre-quency indication with 400 ppm accuracy of the CS8412 has been sacrificedin favour of the 88.2 kHz and 96 kHz rates in the new device.

Clock detection is carried out by a 2nd-order loop filter via a phase-lockedloop (PLL). In the CS8414 the design of the external RO-filter is slightly differ-ent than with the CS8412.

The input of the CS8414 is an RS422 receiver that can handle differential(symmetric) as well as asymmetric (single-ended) signals. In the AudioDAC2000 the input is configured for decoding single-ended signals only: inputRXN is therefore bypassed to earth.

To ensure optimum operation of the phase detector in the internal PLL, theinput is based on a 50 mV Schmitt trigger.

RS422Receiver De-MUXClock and Data

Recovery

AudioSerial Port

RegistersMUX MUX

6C0/E0

16SEL

MCK M3

RXN

13

10

CS12/FCK

5Ca/E1

4Cb/E2

3Cc/F0

2

17M218

M124

M0 23

AGND21

FILT20

VA+22

DGND8

VD+7

Cd/F1

27 Ce/F2

25 ERF

15

990059 - 13 CBL

RXP 9

SDATA26

SCK12

FSYNC11

C1

U14

VERF28

19

CS8414

High power, high quality discrete Class D amplifier

http://www.handsontec.com

The Universal Class D (UcD) version 1.00 demonstrator board implements a 200 W true RMS (into a 4 W load) high quality audio power amplifier on a very compact printed-circuit board. The amplifier is built-up of discrete components only.

The Class D concept allows efficient and cost-effective high output power audio amplifiers to be created. The Universal Class D (UcD) principle enables PWM amplifiersto perform at an excellent sonic level while making use of a relatively simple closed-loop topology.

For detail technical specifications of this discrete design, please visit: http://www.handsontec.com


I N T R O D U C T I O NIt is clear from the description of theoverall design in last month’s instal-ment that the Audio DAC 2000 can bedivided into four distinct sections: thepower supply, the receiver and dis-play driver, the LED display, and theDACs. These sections are identified inthe circuit diagram in Figure 1 bydashed lines.

The DAC section includes the digi-tal interpolation filter, the output filter,the various relays, and the DACs. Forclarity’s sake, these circuits are repro-duced in Figure 3.

Last month’s Part 1 of this article dealt primar-ily with a general description of the new digital-to-analogue converter (DAC) ‘Audio DAC 2000’and details of the input section. In this secondand penultimate part the remainder of the cir-

cuit, more especially the digital interpolation fil-ter and the actual DACs, is described.

78

Design by T Giesberts

audio DAC 2000 Part 2

digital filter and DACs

AUDIO & HI-FI

D I G I T A L F I L T E RThe integrated digital interpolation fil-ter, IC6 (Burr-Brown Type DF1704) is amultipurpose device, which

is suitable for sampling rates of32–96 kHz;

can be used as a notch filter provid-ing 115 dB attenuation;

has an input suitable for 16/20/24bits;

has an output of 16/18/20/24 bits; provides automatic sensing of the

ratios of the clock frequencies (sys-tem clock up to 768Fs – where Fs is

the sampling rate); can be used as slow roll-off filter; provides a soft mute; provides digital emphasis; has a digital attenuator.

Various input and output formats canbe set via hardware or software. In theAudio DAC, setting via hardware hasbeen opted for, since in its standardapplication the unit will invariablyhave a fixed place in the audio system.This means that the various DIPswitches normally need to be set onlyonce. However, as in the receiver,

there is space for experimentation, butnote that the measurements given inthis article refer to default settings ofthe DF1704.

The only difference between con-trol via software and hardware is thatwith the former a digital attenuator canbe used independently, providing 256steps of 0.5 dB each both to the left andto the right.

One of the more important settingsis the correct tuning to the format setat the receiver, that is, I2S.

With reference to Table 1, the vari-ous possible settings are detailed below.


MC/LRIP

ML/RESV

DF1704

MD/CKO

BCKIN

LRCIN

WCKO

BCKO

IC6

CLKO

MODE

MUTE

DEM

SF0

SRO

I2S

IW0

DIN

XTI

XTO

RST

DOR

DOL

IW1

OW1

SF1

OW0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1

2

3

4

56

7

8

9

12

34

56

78

910

1112

1314

K5

1516

S3

S4S2

C16

10µ 63V

C17

100n

R25

2k49

R30

3k57

R31

3k65

R32

3k32

R27

3k57

R28

4k12

R29

3k92

C23

2x 47µ

C24

C19C184µ763V

C22

100µ25V

2x

SERVO DC

PCM1704

REF DC

BPO DC

INVERT

20BIT

IOUT

BCLK

IC7

–VDD

+VDD

–VCC

+VCC

WCLK

DATA

AGND

AGND

DGND

14

20

11

17

12

15

16

10

4

6

2

7

1 19

9

5

SERVO DC

PCM1704

REF DC

BPO DC

INVERT

20BIT

IOUT

BCLK

IC8

–VDD

+VDD

–VCC

+VCC

WCLK

DATA

AGND

AGND

DGND

14

20

11

17

12

15

16

10

4

6

2

7

1 19

9

5

C21C204µ763V

2x

C40C394µ763V

C43

100µ25V

2x

C44

2x 47µ

C45

C42C414µ763V

2x

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47p

OPA627

IC9

2

3

6

7

4

1

5 OPA627

IC10

2

3

6

7

4

1

5

Re2

C27

2n2

C28

4n7

C29

330p

C31

1n5

C30

1n

C32

270p

R40

100Ω

K6

C46

100n

C47

100n

C48

100n

C49

100n

25V

R26

2k49

R36

3k57

R37

3k65

R38

3k32

R33

3k57

R34

4k12

R35

3k92C26

47p

OPA627

IC11

2

3

6

7

4

1

5 OPA627

IC12

2

3

6

7

4

1

5

Re3

C33

2n2

C34

4n7

C35

330p

C37

1n5

C36

1n

C38

270p

R42

100Ω

K6

C50

100n

C51

100n

C52

100n

C53

100n

Re1

R39

1M

R41

1M

K9

25V

C68

100µ25V

C66

100n

LM317

IC13

C69

100µ25V

C67

100n

R51

24

9Ω

R53

24

9Ω

R52

75

0Ω

R54

75

0Ω

LM337

IC14

C64

10µ 63V

C65

10µ 63V

C62

10µ63V

C60

100n

C63

10µ63V

C61

100n

D5

5V61W3

D6

5V61W3

R47

15

0k

R48

15

0k

R49

1M

R50

4Ω

7

C57

470µ25V

D3

1N4148T2

BC517

C56

1µ63V

R43

15

0k

R44

15

0k

R45

1M

R46

10

Ω

C55

220µ25V

D2

1N4148T1

BC517

C54

47µ25V

JP2

K8

C58

100µ25V

C59

100n

D4

5V61W3 JP3

L

R

12V

12V

12V

12V

5VA

5VA

5VD

5VD

5VD

DBW

MUTE

DBW

5VA

5V

5V

12V

12V

12V

12V

12V

12V

12V

12V

DBW'

MUTE'

D1

1N4001

12V 12V

VDBWVMUTE

VDBW

VMUTE

VDBW

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5VA

A

A

5VA

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990059 - 15

3 Figure 3. Section of the cir-cuit diagram in Figure 1 thatis housed on the DAC board.

DIP switch S2 is aquadruple devicesince pins 11–13 havedual functions. When mode pin 10 ishigh, these pins form a 3-wire soft-ware-control port and are then calledMD, MC, and ML, respectively. Thesenames are shown in brackets adjacentto the pin locations on the board. Atthe other side of the location thehardware mode functions are shown,just as the levels adjacent to ON andOFF. In the present application, thisarrangement is not used, but S2 may,if desired, be replaced by an 8-pinboard connector (to accept flatcable)to, say, link the digital filter to amicrocontroller.

Pins 11–13 and mode pin 10 haveinternal pull-up resistors, so that aclosed DIP switch (ON) results in a lowlevel at S2. This means that for thehardware mode, section 1 of S2 mustbe closed (Mode=low). Pin 13 (RESV –section 4 of S2) is then not used.

Pin 12 (LRIP – section 3 of S2) deter-mines at which level of the L/R clockthe data must be considered as belong-ing to the lefthand channel or to therighthand channel. When section 3 ofS2 is off, LRIP is high, whereupon it isassumed that when clock signalLRCIN is high, the data are intendedfor a lefthand sample. In the I2S mode,LRIP is not used.

Pin 11 (CKO – section 2 of S2)determines whether the CLKO outputon pin 9 is equal to the clock at XTI orXTI/2. This pin has no specific func-tion in the Audio DAC and is there-fore not used.

It is possible to connect a crystaloscillator to pins XTI and XT0, but thisis rather pointless since XTI is provided

by the high-precisionmaster clock (MCK)in IC1. XTI may have

a number of values: 256Fs, 384Fs, 512Fs,and 768Fs. Its maximum value at 512Fsand a sampling rate of 96 kHz is49.152 MHz, but the maximum possi-ble frequency of a crystal oscillator is24.576 MHz. In fact, at 256Fs and a sam-pling rate of 96 kHz, the manufactureradvises against the use of a crystaloscillator and suggests the use of anexternal source for XTI. This is the rea-son that there is no space reserved for acrystal oscillator on the board.

Bit clock BCKIN may be 32Fs, 48Fs,or 64Fs, while LRCIN is, of course,always equal to Fs. The input formatsare self-evident and should be com-pared with the output format of IC1.When both a CD player and a DVDplayer with a 24 bit/96 kHz are to beconnected to the Audio Dac, the modeshould always be 24 bit, which fixes theposition of the MSB.

The various input formats aredetermined by inputs IW0 and IW1,and I2S, that is, sections 3, 4, and 5, ofS3 respectively. For clarity’s sake, thefunction of the sections of S3 is shownin tabular form on the board adjacentto K5.

The output format is determinedby inputs OW0 and OW1, that is, sec-tions 1 and 2 of S2, XTI, and the8-times oversampling. The format isalways complement 2, MSB first andright justified. DOR contains samplesfor the righthand channel only, andDOL for the lefthand channel only.The inputs sense whether the data atthe output contains 16, 18, 20, or 24bits per sample.

Output word clock WCKO is, of

course, always 8Fs, irrespective of thesystem clock. Output bit clock BCKO isdetermined by the system clock and is256Fs when XTI is 256Fs or 512Fs, or192Fs when XTI is 384Fs or 768Fs. In thepresent application, BCKO is alwaysequal to the master clock (MCK) of IC1.The outputs are set to 24 bits by settingsections 1 and 2 of S3 to ON.

The slow rolloff filter functionensures reduced ringing in the passband, but produces more aliasingproducts. The manufacturer recom-mends that the filter is not used above96 kHz. Input SRO (pin 27) deter-mines whether the filter is used; itslevel is set with section 8 of S3, whichis normally OFF.

When the deemphasis control isactuated by the receiver, IC1, the tworemaining inputs, SF0 and SF1 (pin 17and 18) respectively determine forwhich sampling rate the deemphasisis valid. This is normally 44.1 kHz, onthe assumption that deemphasis isusually required for certain CDs only.All inputs that are controlled via S3have internal pull-down resistors,which is the reason that S3 is linked tothe +5 V line.

Soft mute control input MUTE isswitched directly by error output ERFof IC1 (which is inverted by the GAL).When the level at MUTE is low, thedigital filter is in the mute position —the output relay is then deactuated.

The DF1704 has an internal power-on reset as well as a reset input. Theinternal reset lasts for 1024 systemclock periods after the supply voltagehas been switched on; all outputs arethen low. This is true also after a low-to-high change at the RST pin.

D I G I T A L - T O - A N A L O G U EC O N V E R T E R S ( D A C )

The data from the digital filter isapplied to two high-quality digital-to-analogue converters (DACs), IC7 andIC8, whose internal block schematic isshown in Figure 4.

These devices are suitable for sampling rates of

16–96 kHz; provide 8× oversampling; provide a choice of 20 or 24 bit data; have a dynamic range of 112 dB; provide a signal-to-noise ratio of

120 dB; have a glitch-free output; invert the data.

In contrast to oversampling data con-verters using, for instance, the delta-sigma architecture, the Burr-Browndevices use a different solution to thebipolar zero transition problem.

Delta-sigma converters have aninherent poor signal-to-noise ratiowhich makes the use of noise-shaping


InterfaceLogicand

Logic Bias

23-BitSegmentSwitches

23-BitCurrent

Segments

BPO

Reference,Servoand

BipolarOffset

10mAAGNDDGND

WCLK

BCLK

DATA

LogicBias

990059 - 2 - 14

AnalogBias

SERVO DC

REF DC

BPO DC

20mA

3mA2mA

-5V Supply

+5V Supply

-VDD -VCC

IOUT

+VDD +VCC

PCM1704

1

Figure 4. Internal blockdiagram of the integrateddigital-to-analogue con-verter Type PCM1704.

circuits to improve that ratio within theaudio band essential. Unfortunately,this creates an appreciable increase innoise outside the audio band. If theoutputs of the DACs were not filteredcorrectly, an overall deterioration ofperformance would ensue.

The PCM1704 uses the traditionalDAC structure (R–2R) in such a man-ner as to provide excellent low-fre-quency performance and yet not losethe outstanding properties of thisstructure: excellent full-scale perfor-mance; high signal-to-noise ratio, andsimplicity of design. Burr-Browndesigners term this architecture sign-magnitude. Briefly, this means that two23-bit DACs are combined in a com-plementary setup which results in ahighly linear output so that a 24-bit res-olution is assured at the zero crossings.

The two DACs have a common ref-erence and R–2R laddernetwork. The networkuses dual-balanced cur-rent segments that ensurecorrect performance in allkinds of circumstance.Moreover, the discrete bitsof the DACs are alter-nated so that, after lasertrimming of the resistors,the DACs are identical forall purposes required bythe present application.

The DAC is timed sothat only the 24 bit beforeword clock WCLK goeslow causes the data in theserial input register to betransferred to the parallelDAC register. If pin 9(20-bit mode) is active(linked to the –5 V line),the foregoing also appliesto the last 20 bit. Anyother bits present will notbe accepted, so that thedata applied to the DACmust correspond to themode to which the DACis set. If this is not so, thedata will become muti-lated or the level is muchtoo low.

The maximum bit clock is specifiedas 25 MHz, which is related to the 8×oversampling, a 32-bit frame for thedata, and the maximum sampling rate,(8×32×96 kHz=24.576 MHz). Thedata can be inverted by linking pin 10(INVERT) of the PCM1704 to the neg-ative supply line.

Pins 9 and 10 have internal pull-upresistors to digital ground (DGND) andare switched with DIP switch S4. Sec-tion 4 of this switch is not connected,so that a 3-section switch would suf-fice. However, 4-section switches aremuch more readily available.

The ICs are powered by a symmet-rical ±5 V supply. This is derived via

regulators IC13 and IC14 from the ana-logue ±12 V line and used only for theDACs. Potential dividers R51-R52 andR53-R54 set the regulators to exactly5 V. Since there is some residual rippleon the ±12 V line (which does notaffect the op amps), capacitors C64 andC65 provide additional ripple suppres-sion. Zener diodes D5 and D6 protectthe DACs against errors such as wrongresistors or defect regulators.

The manufacturer’s specificationstipulates that the supply lines to thedigital and analogue sections must belinked as a single line to an analoguesupply. There is no advantage in sepa-rating the digital and analogue sup-plies, but it is essential that they aredecoupled to the ground plane as closeto the relevant IC pins as possible. This,and that fact that internal voltagesSERVO DC, REF DC, and BPO DC

must be decoupled in a like manner, isthe reason that the ICs are surroundedby decoupling capacitors.

The current output of the DAC isspecified as 1.2 mA/200 ns (the fullrange is ±1.2 mA), which demandscertain requirements from the I/U con-verter as described in the followingsection.

I / U C O N V E R T E ROp amps IC9 and IC11 on which thecurrent-to-voltage converters are basedmust have:

a very low bias current to obviateadditional offset;

a high slew rate to be able to followthe DAC accurately;

excellent linearity.

In the Audio DAC the OPA627 is used,which has a bias current of just 10 pA, aslew rate of 55 V µs–1, and a distortionof only 3×10–7 (0.00003%).

The inherent input offset of theOPA627 ≤ 0.5 V, which results in over-all offset voltages at the output of theprototype ≤ 10 mV and ≤ 20 mVrespectively. This is low enough to pre-vent the use of an output capacitor,particularly since this would inevitablyadversely affect the quality of the out-put signal. It is assumed in any casethat there is invariably a couplingcapacitor between preamplifier andoutput amplifier. If nevertheless anoutput capacitor is desired, a metal-lized polypropylene (MKP, Siemens)

type of about 10 µF should be used.Resistors R40 and R42 may then bereplaced by an external RC network. Itshould be borne in mind that a 10 µFMKP capacitor is fairly large.

The one disadvantage of theOPA627 is its low-frequency noise,which in any FET op amp is fairlyhigh. Even so, the specified values of20 nV/√Hz at 10 Hz and 5.6 nV/√Hz at1 kHz are very good indeed.

Since the value of R25 and R26 isretained at 2.49 kΩ, the actual outputvoltage of 2.1 Vrms is slightly higherthan the standard 2 Vrms.

Capacitors C25 and C26 are neededto filter r.f. components from the signal.


Because of quality considerations,these capacitors should be (axial) poly-styrene types.

O U T P U T F I L T E RAlthough the digital interpolation filterattenuates most aliasing frequencies byat least 115 dB, an analogue low-passfilter is still required to remove anyresidual components plus any spuri-ous products caused by jitter of the sys-tem clock.

In fact there are two output filters,which are selected by a relay. The first,R27–R29-C27–C29 is a 3rd order But-terworth type for the more usual sam-pling rates of 32 kHz, 44.1 kHz, and48 kHz. The cut-off frequency of thisfilter is about 27 kHz.

The second filter,R33–R35-C30–C32, is a 3rd order Besseltype for use with sampling rates of88.2 kHz and 96 kHz. Its cut-off fre-quency is about 43.7 kHz.

The amplitude characteristics of thetwo filters are virtually identical overthe audio range.

The filters are 3rd order types sincethe first passive section of this type offilter provides much better r.f. suppres-sion than that of a 2nd order filter. Inthe latter, r.f. suppression depends onthe ratio of the impedance of the filternetwork and the output impedance ofthe relevant buffer op amp.

Switching between the two filters iseffected in each channel by a relaywith parallel-connected double-polechange-over contacts (Re2 and Re3respectively). The relays are 12 V typesthat are energized directly by the ana-logue +12 V line. The supply to therelays is separately filtered byR57-C57. The board layout is designedso that the return currents are separateup to the 0 terminal.

The relays switch the outputs of thetwo filters to the input of buffer IC10(one channel) or IC12 (other channel).Although the non-selected filter loadsthe relevant I/U converter and outputbuffer, it does not affect the response ofthe selected filter.

The relays are energized indirectlyby signal DBW from the GAL on thereceiver board. Since this signal is aTTL signal (5 V) and the relays need12 V, voltage conversion is needed,which is provided by darlington tran-sistor T2. The base current of this tran-sistor is low enough not to load theGAL to an unacceptable extent.

The only load is presented bypotential divider R47–R49, which isdecoupled by capacitor C56. ResistorR49 ensures that T2 is switched off atany residual voltage, which results in amuch better defined switching signalfor the transistor.

Diode D3 is a freewheeling diodethat provides a leakage path for theenergy in the circuit when the relay is

deenergized. Note that T2

switches both relays, since the coils ofthem are in parallel.

M U T E R E L A YThe mute relay, Re1, at the output ofthe DAC circuit, obviates switch-onclicks and other irregular pulses on thesupply lines. It is controlled by a signalfrom IC1 and switches the digital filterto the mute state when the receiverdetects an error.

Since the impedance of both out-puts is low, one relay suffices withoutany risk of deterioration of the channelseparation at high frequencies. If thereis a drawback, it is that the relay is notfast enough at switch-off, which maycause a loud click.

Like the output filters, the relay isswitched by a darlington transistor, T1.When the relay is not energized, theoutputs are in the mute state.

When the supply voltage isswitched on, or when an error hasbeen remedied, the relay is energizedgradually to ensure that all stages havebeen reset correctly before the relayoperates. The delay time is determinedby network R43-R44-C54, the time con-stant of which is 3 seconds in case of aswitch-on, but rather shorter after an

error has been reme-died.

Capacitor C1 is discharged viadiode D1 so that the relay changesstate immediately upon the receiverdetecting an error, such as the absenceof an input signal.

Network R46-C55 decouples the12 V supply lines to ensure that theswitching of the relay contacts does notcreate pulses on these lines.

Diode D2 is a freewheeling diodethat provides a leakage path for theenergy in the circuit when the relay isdeenergized.

[990059]

The third and last part of this article willdeal primarily with the printed circuitboards, the construction, and the testresults.


Table 1. Hardware modecontrols of the digitalinterpolation filter.

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P O W E R S U P P L YAlthough the summary implies that allparts of the digital-to-analogue con-verter (DAC) have been discussed, thisis not entirely true, because the powersupply has not yet been described.

It was seen in Part 2 of this articlethat the converter ICs need a symetri-cal ±5 V supply and that this wasderived via regulators IC13 and IC14from the ±12 V supply line for the ana-logue circuits. Since it is important tokeep the supply lines to the converterICs as short as possible, the regulatorsare housed on the DAC board.

The receiver section and some othercircuits on the DAC board need a sin-gle +5 V supply and a symmetrical±12 V supply. These voltages are pro-duced with the aid of regulatorsIC15–IC17, which, together with theother components of the power sup-ply, are housed on a separate board,the PSU board.

The circuit of the power supply isshown in Figure 5. Note that the +5 Vline for the digital circuits is isolated

from the ±12 V lines for the analoguecircuits.

The earth lines of the two suppliesare interlinked on the DAC boardbetween the digital filter and the con-verter ICs (that is, JP3).

Obviously, the supply consists ofnot only regulators, but also bridge rec-tifiers and smoothing capacitors. Resis-tors R55, R56, and R58 between the rec-tifiers and smoothing capacitors limitthe charging current to the capacitorsat power-on, and any resulting inter-ference.

The secondaries of the relevantmains transformers are linked to K11and K13 respectively. The choice oftransformer is up to the constructor,although some suitable models arespecified in the parts list.

The power supply is convenientlybuilt on the ‘transformer board’described elsewhere in this issue. Thisboard is designed to house all the com-ponents required for the present powersupply.

Readers who have studied and absorbed

Parts 1 and 2 of thisarticle will be fullyaware of how theAudio DAC 2000

works. What remainsto be discussed is theactual building of theconverter, and this isdone in this third and

final part.

12

Design by T. Giesberts

audio DAC 2000Part 3: practical matters

AUDIO & HI-FI

P R I N T E D - C I R C U I TB O A R D SAs already mentioned in Part 1, theAudio DAC 2000 is contained on fourindividual printed-circuit boards: onefor the ±12 V and +5 V power sup-plies; one for the digital audio receiverwith display driver; one for a 2-digitLED display; and one for thedigital/analogue circuits, the digital fil-ter, the DACs and the analogue outputstage. These boards are sections of thedouble-sided PCB shown in Figure 6.This high-quality board is availablethrough our Readers Services. Beforeany work is carried out, these four sec-tions should be separated from oneanother along the milled cutting lines,either by snapping or cutting along thelines

It is important to construct the var-ious circuits according to the board lay-outs and the parts list. It is importantthat the orientation of the ICs and thepolarity of the electrolytic capacitorsare strictly observed, since any devia-tion results unfailingly in a non-work-ing unit.

The DIP switches, S1–S4, are bestsoldered directly to the board. Anexception is S2 if it is foreseen thatprocessor (that is, software) controlmay be used at a later stage. In thatcase, the switch may be housed in agood-quality 8-way IC socket, but eventhen the board connector should besoldered in place at a later stage.

All supply lines are connected tothe boards via terminal blocks thatfacilitate the wiring or servicing of therelevant circuits. The +5 V line for thedigital section is linked to the DACboard. The receiver board is poweredvia the link between K3 and K5. Someprotection against (a too) high supplyvoltage is provided by diode D4 on theDAC board.

The LED display board is linked tothe receiver board via a 10-way flatca-ble. One end of this cable is connectedpermanently to the board via a 10-wayboard connector. The other end is ter-minated into a 10-way socket. Takegood care to use the correct length ofcable. The displays are soldereddirectly to the board.

The digital audio receiver, IC1, issoldered directly to the receiver board.Take care not to damage this IC by elec-trostatic discharges. Sockets may beused for IC4 and IC5. Crystal oscillatorIC3 is also best soldered directly to theboard, since it is then as close as possi-ble to the ground plane.

Start populating the DAC board bysoldering IC6 to the board — see Fig-ure 7. This tiny SMA (surface-mountassembly) IC is housed in a 28-pinSSOP case, whose pins are spaced atonly 0.65 mm. This requires extremecare, a tiny soldering iron tip, and pos-sibly a magnifying glass to check the

soldering work. Takegood care not to over-heat the IC: take a pausebetween soldering, say,2 or 3 pins at a time.

Next, solder the converter ICs, IC7and IC8, in place. These are housed in astandard 20-pin SMD case (SOIC), andare easily soldered. It is best to fitop amps IC9–IC12 in good-quality ICsockets.

Capacitors C27–C38 in the analoguesection are 1% close-tolerance types ina square radial format, with the termi-nals placed at two opposing corners.These types are manufactured byEMZ. Their pitch is standard (7.1 mm),so they could be replaced by metal-lized film polystyrene or polypropy-lene types. It should be borne in mind,however, that the larger tolerances ofthese types may result in significantchanges in the frequency and phaseresponses. The EMZ capacitors speci-fied carry a thin dash that indicateswhich terminal is linked to the outerlayer. Make sure that this pin is linkedto ground or to the output of anopamp: this makes the analogue sec-tion less sensitive to interference. Thesame applies to axial capacitors C25and C26: place the band on these at theoutput side of opamps IC9 and IC11.

The relays are soldered directly tothe board. Do not forget wire bridgesJP2 and JP3: these are permanent linkswhich may be made in rather thickerwire than usual.

A final practical hint. To improvethe channel separation at high fre-quencies, it is advisable to shield theleft- and right-hand sections of the ana-logue output filter from one another.

This is best done by placing a small(86×13 mm) tin-plate screen betweenRe2 and IC12. The screen stretchesfrom the edge of the board to DIPswitch S4: its position is indicated inFigure 6 by a dashed line. At the ends,scratch away some of the lacquer onthe board with a sharp pen knife toensure that the screen makes goodcontact with the copper area at the topof the board which functions asground plane — soldering the ends ofthe screen to the copper is even better.In the prototype, the addition of thescreen improved the channel separa-tion by 12 dB at 20 kHz.

E N C L O S U R EWhen the four boards have been com-pleted and checked for possible build-ing or soldering errors, they must becombined into a complete Audio DAC2000 and housed in a suitable enclo-sure. The most suitable enclosure is asturdy metal case, which, as far asappearance is concerned, shouldpreferably match the audio installationwith which it is to be used.

The prototype is housed in a Mona-cor Type UC251/SW enclosure. This is435 mm wide, 230 mm deep, and44 mm high — see Figure 8. In somecountries in which Elektor Electronicsappears, Monacor products are soldunder the brand name ‘Monarch’.

The manner in which the boardsare arranged in the enclosure is opti-mal and constructors are well advised


B1

B80C1500

C89 C86

C88 C87

R58

1Ω5

C85

1000µ25V

C83

10µ63V

C84

100n

C82

100n

K13

K12R57

3k

9

D7

POWER

B2

B80C1500

C81 C78

C80 C79

R55

3Ω3

C76

1000µ40V

C72

10µ63V

C74

100n

C70

100n

R56

3Ω3

C77

1000µ40V

C73

10µ63V

C75

100n

C71

100n

K11

K10

15V

15V

5V

12V

12V

4x 22n

4x 22n

*7805

IC17

7812

IC15

IC16

7912990059 - 3 - 16

8V

5

Figure 5. Circuit diagram of the power supply forthe Audio DAC 2000. The +5 V line for the digitalcircuits is isolated on the board from the ±12 Vline for the analogue section.


B1

B2

C1 C2

C3

C4C5

C6

C7

C8

C9

C10

C11

C12

C13

C14C15

C16

C17

C18

C19

C20

C21

C22

C23

C24C

25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41C

42

C43C44

C45

C46C47

C48

C49

C50

C51

C52

C53

C54

C55C56

C57

C58C59

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

C87

C88

C89

D1

D2

D3

D4

D5

D6

D7H1

H2 H3

H4

H5H6

H7 H8

H9

H10

H11

H1

2

H1

3

H14

H1

5

H16

IC1

IC2

IC3

IC4

IC5

IC6

IC7 IC8

IC9

IC10

IC11

IC12

IC13

IC14

IC15

IC16

IC17

JP1

JP2

JP3

K1

K2K3

K4K5

K6

K7

K8

K9

K10

K11

K12

K13

L1 L2

L3

L4

LD1LD2

OU

T1

OUT2

OUT3

OUT4 OUT5

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13R14R15

R16

R17R18

R19

R20

R21R22

R23R24

R25

R26

R27

R28

R29

R30

R31 R

32

R33

R34

R35

R36

R37 R

38

R39

R40

R41

R42

R43R44R45

R46

R47

R48R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

RE1

RE2 RE3

S1

S2 S3

S4

T1

T2

0

9V

15V

15V

12V

12V

5V

0

0

-

+

+

0

~

~

~

~

M0

M1M2

M3

0

+5V

0 1

+5V

0-1

2V

+12V

RL

MODECKO

LRIP(MD)(MC)(ML)

INV

LIN

VR

20b

it

S3-1 OW0-2 OW1-3 IW0-4 IW1-5 I2S-6 SF0-7 SF1-8 SRO

LH

H

L

990059-1

COMPONENTS LIST

Resistors:R1 = 75ΩR2 = 220ΩR3 = 470ΩR4,R50 = 4Ω7R5 = 4-way 10kΩ SIL-arrayR6 = 10kΩR7-R10 = 22ΩR11-R24 = 820ΩR25,R26 = 2kΩ49 1%R27,R30,R33,R36 = 3kΩ57 1%R28,R34 = 4kΩ12 1%R29,R35 = 3kΩ92 1%R31,R37 = 3kΩ65 1%R32,R38 = 3kΩ32 1%R39,R41,R45,R49 = 1MΩR40,R42 = 100ΩR43,R44,R47,R48 = 150kΩR46 = 10ΩR51,R53 = 249Ω 1%R52,R54 = 750Ω 1%R55,R56 = 3Ω3R57 = 3kΩ9R58 = 1Ω5

Capacitors:C1,C2 = 10nF ceramicC3 = 68nFC4,C6,C10,C16,C62-C65,C72,

C73,C83 = 10µF 63V radialC5,C7 = 47nF ceramicC8,C9,C11,C12,C15,C17,C46-C53,

C59,C60,C61,C66,C67,C70,C71,C74,C75,C82,C84 = 100nF ceramic

C13,C14,C23,C24,C44,C45,C54 = 47µF 25V radial

C18-C21,C39-C42 = 4µF7 63V radialC22,C43,C58,C68,C69 = 100µF 25V

grammed, order code 996530-1,see Readers Services pages)

IC6 = DF1704E (Burr-Brown)IC7,IC8 = PCM1704U (Burr-Brown)IC9...IC12 = OPA627AP (Burr-Brown)IC13 = LM317 (TO220)IC14 = LM337 (TO220)IC15 = 7812IC16 = 7912IC17 = 7805

Miscellaneous:JP1 = 2-way pinheader + jumperJP2,JP3 = wire link *K1,K6,K7 = cinch socket, PCB

mount (Monacor/Monarch type T-709G)K2 = 10-way boxheaderK4 = 10-way PCB-connector (for flat-

cable)K3,K5 = 16-way boxheaderK8,K12,K13 = 2-way PCB terminal

block, raster 5 mmK9,K10,K11 = 3-way PCB terminal

block, raster 5 mmS1,S2,S4 = 4-way DIP-switchS3 = 8-way DIP-switchB1,B2 = B80C1500, rectangular caseRe1,Re2,Re3 = V23042-A2003-B101,

12V/600 Ω (Siemens)Supply transformers: 2x15 V/4 VA

(e.g. Block FLD4/15; Hahn BVUI3020165; Monacor FTR-415), and2x8(or 9) V/4 VA (e.g.. Block FLD4/8;Hahn BVUI 3020161; Monacor FTR-49 –see transformer board elsewhere in thisissue)

PCB, order code 990059-1, seeReaders Services pages.

* see text

Figure 6. The double-sided board must be divided into four sub-boards along the fraised lines.

6

reproduced at 85% of

actual size

radialC25,C26 = 47pF 1 axial (EMZ )C27,C33 = 2nF2 1% 1 (EMZ )C28,C34 = 4nF7 1% 1 (EMZ )C29,C35 = 330pF 1% 1 (EMZ)C30,C36 = 1nF 1% 1 (EMZ)C31,C37 = 1nF5 1% 1 (EMZ)C32,C38 = 270pF 1% 1 (EMZ)C55 = 220µF 25V radialC56 = 1µF 63V radialC57 = 470µF 25V radialC76,C77 = 1000µF 40V radialC78-C81,C86-C89 = 22nF ceramicC85 = 1000µF 25V radial

1 polystyrene/polypropylene

EMZ, Elektromanufaktur ZangensteinHanauer GmbH & Co.Siemensstrasse 1D-92507 NabburgGermanyTel. +49 9433 898-0Fax +49 9433 898-188

Inductors:L1-L4 = 47 µH

Semiconductors:D1 = 1N4001D2,D3 = 1N4148D4,D5,D6 = 5V6 1W3 zener diodeD7 = LED, red, high-efficiencyLD1,LD2 = HDN1075O (Siemens)T1,T2 = BC517IC1 = CS8414-CS (Crystal)IC2 = TORX173 (Toshiba)IC3 = 6.144MHz SG531P (Seiko

Epson)IC4 = 74HCT32IC5 = GAL22V10B-25LP (ready-pro-


990059-1(C) ELEKTOR

to use the same arrangement: the DACboard in one corner, the receiver boardnext to it, the supply board in front ofthis, and the transformer board in theremaining corner.

The only items to be fitted on thefront panel are the mains on/off switchand the display that shows the sam-pling rate. If desired, power diode D7may be added to this, but this is notreally necessary since LD1 and LD2function very well as on/off indicator.

The interwiring may be gleanedfrom Figure 8, but is summarized forconvenience’s sake.• K2 on the receiver board is linked to

K4 on the display board just behindthe front panel via a 10-core flatca-ble.

• K5 on the DAC board is linked toK3 on the receiver board via a16-core flatcable. This link also con-nects power to the receiver board.Mind the orientation of pin 1 on theconnectors.

•• K12 (+5 V) on the supply board islinked to K8 on the DAC board viatwo cables.

• K10 (±12 V) on the supply board islinked to K9 on the DAC board viathree cables.

F I N A L L YTesting a digital-to-analogue converterby ear is hardly possible or sensible.Noticeable differences, such as can bedetected in the case of loudspeakers,cannot be expected. Nevertheless, atest audience felt that the DAC 2000sounded better than a number of otheravailable types of DAC. They found thesound cleaner and the stereo imageclearer.

The test results in the box give a fur-ther judgment of the quality of theconverter. They call for a few com-ments.• The bandwidth of sampling fre-

quencies 32 kHz, 44.1 kHz, and48 kHz, is exactly equal to half thesampling rate, since at these fre-quencies the bandwidth of the ana-logue filter is larger than that of thesteep-skirted digital filter. At88.2 kHz and 96 kHz, the band-width is determined by the ana-logue filter.

• The THD+N at a sampling rate of96 kHz is measured at a bandwidthof 22 kHz, because at lower sam-pling rates the analogue output fil-ter has a bandwidth of 26 kHz. Thereduction gives a more honest com-parison of the three measurements.

[990059-3]

Text: S. van Rooij


Figure 7. Soldering IC6 into placerequires a steady hand, goodeyesight and precision tools.

Figure 8. The completed prototype. The enclosureused provides more than enough space to housethe various boards in an optimum arrangement.


Technical specificationProperties• 1 coaxial input and 1 optical input• suitable for sampling rates of 32–96 kHz• 2-digit readout of sampling rate• 8× oversampling• 24-bit digital filter• 24-bit digital-to-analogue converters• digital de-emphasis• switchable third-order analogue output filter• isolated supply lines for digital and analogue sections

Electrical characteristicsNominal input voltage at coaxial input 0.5 Vpp into 75 ΩNominal output voltage 2.1 V r.m.s.Frequency range (–3 dB) 0–fs/2 (fs=32/44.1/48 kHz)

0–42 kHz (fs=88.2/96 kHz)Amplitude at 20 kHz –0.94 dB (fs=32, 44.1, 48 kHz)

–0.66 dB (fs=88.2, 96 kHz)Bandwidth analogue filter 26 kHz (Butterworth at fs=32/44.1/48 kHz)

42 kHz (Bessel at fs=88.2/96 kHz)Output impedance 100 ΩSignal-to-noise ratio ≥ 114 dBATHD+N (1 kHz, B=80 kHz) 0.0016% (44.1 kHz, 16-bit)

0.001% (48 kHz, 24-bit)0.0008% (96 kHz, 24-bit, B=22 kHz)

IMD (60 Hz/7 kHz, 0 dB) 0.0035%Linearity error <0.5 dB/–90 dB (according to datasheet)

0.2 dB/–110 dB (measured)Channel separation (1 kHz) >115 dBDynamic range >100 dB

Measurements were made with switch settings as followsS1 S2 S3 S4

-1 off -1 on -1 on -1 off-2 off -2 off -2 on -2 off-3 off -3 off -3 on -3 off-4 on -4 off -4 off -4 NC

-5 on-6 off-7 off-8 off

Performance characteristics

For completeness’ sake, the electrical specifications are complemented by aset of performance characteristics. Some comments on these are:

Curve a is the frequency response of the analogue output filters, measuredby injecting a current into the current-to-voltage converters, so that the first fil-tering by C25 and C26 is included.

Curve b is the THD+N characteristic at full drive. This was measured withthe aid of a test compact disk (16-bit, 44.1 kHz). The increase in distortion above3 kHz is small and remains below 0.005% up to 20 kHz. At higher audio fre-quencies the speed of the DACs will of course have an effect.

Curve c illustrates the linearity of the DACs. The amplitude sweep was car-ried out with test tones of 400 Hz, provided with dither to make measurementsup to –110 dB at 16 bit possible.

Curve d represents the channel separation between the two channels from40 Hz upwards. Below this only the noise threshold would be measured. Evenat 20 kHz the channel separation is >88 dB in both cases. Measurements weremade with the tin plate screen fitted as mentioned in the text.

Curve e shows the frequency spectrum at 1 kHz at full drive and a samplingrate of 48 kHz at 24 bit. Note that all harmonics are well below –100 dB.

-57

+3

-54

-51

-48

-45

-42

-39

-36

-33

-30

-27

-24

-21

-18

-15

-12

-9

-6

-3

-0

10 200k20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k

dBr

Hz990059 - 3 - A.eps

0.001

1

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

%

20 20k50 100 200 500 1k 2k 5k 10kHz

990059 - 3 - B.eps

CD Linearity

-1.4

+1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

+0

+0.2

+0.4

+0.6

+0.8

+1

+1.2

LINEARITY

ERROR

dB

-110 +0-100 -90 -80 -70 -60 -50 -40 -30 -20 -10CD Absolute amplitude dBFS

CD LINEARITY - Computed Results

990059 - 3 - C.eps

-150

+0

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dB

40 20k50 100 200 500 1k 2k 5k 10kHz 990059 - 3 - D.eps

-150

+0

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr

20 90k50 100 200 500 1k 2k 5k 10k 20k 50kHz 990059 - 3 - E.eps

a

b

c

d

e


In part 2 of the description of the AudioDAC 2000 (Elektor Electronics, December1999), we already briefly mentionedthat the DF1704 digital interpolation fil-ter includes a digital attenuator that canbe adjusted under software control. Wemore or less suggested that this featurecould be used very well in combinationwith an external processor to realise adigital volume control.

Actually, it wasn’t so clever to makethis suggestion, since we should haveknown that such a suggestion wouldonly arouse immediate requests. Wethus set to work straight away todevelop an extension circuit thatallows such a volume control to beadded to the Audio DAC.

The result is described in this article.This is a completely custom processorcircuit that includes software speciallydeveloped for this application.Together, these allow the volume andbalance to be precisely adjusted usingup/down and left/right pushbuttons.

The step size is so small (0.5 dB) thatthe adjustment is practically continu-ous over the full range. A fifth buttonallows the user to quickly select a pre-set volume level and ‘flat’ balance,while simultaneously pressing buttons1 and 5 activates a mute function.

The circuit is easy to build, and con-necting it to the Audio DAC circuitboard is simply child’s play.

A B I T O F H A R D W A R EIn order to control the digital attenua-tors in the DF1704, it is necessary toswitch this digital filter IC to the soft-ware mode. As noted in part 2 of theAudio DAC 2000 project description,this mode is selected by leaving pin 10of the DF1704 open. Pins 13, 12 and 11are then the ML, MC and MD inputs,respectively, of the three-wire softwarecontrol port. All that is needed to makethese inputs accessible on the DAC cir-cuit board is to remove DIP switch S2and replace it with an 8-pin flatcable

26

Design by T. Giesberts

for Elektor’s Audio DAC 2000

This circuit is especiallydesigned for those who

are not satisfied with a sin-gle, fixed volume level for

their Audio DAC 2000.Minimal modifications to

the DAC circuit board anda simple processor circuitare all that are needed toadd a de luxe pushbuttonvolume and balance con-trol. An adjustable preset

is even included!

AUDIO & HI-FI

digital volume control

connector in DIL format. The relevantpart of the Audio DAC circuit diagramis reproduced in Figure 1, for clarity.

The complete hardware of the vol-ume control is shown in Figure 2. Ascan be seen, this is truly a basic circuit,consisting of an 80C32 processor (IC1),an address latch (IC2), an EPROM(IC3) containing the necessary softwareand a RAM (IC4). The flatcable fromthe DF1704 is attached to connector K1.The five control switches S1 through S5are located on a separate part of the cir-cuit board, which can be separatedfrom the remainder of the board. Ashort piece of flat cable between K2and K3 interconnects the two parts ofthe circuit board.

The circuit also includes a 5-wayDIP switch (S6) for presetting a volumelevel for switch S3, and there is a placereserved for an optical receiver (IC5).Although there is presently no use forthis last component, it at least providesa route for hobbyists to add remotecontrol capability to the volume con-trol. Of course, suitable ‘home-made’software is required to support thiscapability.

All that’s left in Figure 2 is the powersupply. As can be seen, this is built in aconventional manner with a rectifier,filter and voltage regulator (IC6). Withan eye on possible future applications,the stabilised +5 V supply voltage isalso made externally available.

F O U R R E G I S T E R SThe DF1704 has four internal registers,called MODE0 through MODE3, thatdetermine the settings of the filter. Theattenuators can only be controlled inthe software mode, which means thatthe filters must be supplied with fixedsettings by the processor after the cir-cuit is switched on. The DIP switcheson the DAC circuit board no longerhave any function in the softwaremode. The detailed information that isneeded for programming the varioussettings can be found on page 10 of theoriginal Burr-Brown data sheet for theDF1704. If you are interested, you canview the data sheet at the Internet sitewww.burr-brown.com.

In addition to the settings that canalso be realised using hardware, thereare three settings that relate to how theattentuators are controlled. In theMODE3 register, bit 2 is the ATC (atten-uator control) bit. This bit controlswhether the left and right attentuatorswork with the same data or separatedata. If ATC is set to 0, the two attenu-ators can be set independently. If ATC isset to 1, both attenuators are coupledand are set by the data for the leftattenuator, contained in the MODE0register. With our volume control, wechose to use separate control data toallow the balance to be controlled,which means that ATC is always set to

0. Register MODE0 thus contains the 8-bit data for the left channel, and regis-ter MODE1 contains the 8-bit data forthe right channel.

In addition to two address bits,each of the attenuator registers con-tains an Attenuator Data Load Controlbit — LDL — for the left channel andLDR for the right channel. If LDL orLDR is set to 1, the associated attenu-ator can be set to a new value, whilesetting LDL or LDR to 0 prevents thesetting from being changed. LDL andLDR are always set to 1 by the proces-sor, so that the software determineswhether a given attenuator shouldreceive different data.

All registers work with 16-bit data,which is sent with the MSB (bit 15)first. The top five bits are alwaysreserved and have no function. Bits 9and 10 represent the address bits A0and A1, respectively.

S O F T W A R E D E S I G NThe software that is needed for the vol-ume control has been developed usinga higher programming languageknown as NiliPascal 3.0. Since the com-plete program listing takes up a lot ofspace, we have not printed it here. Ifyou are interested in reading it, have alook at our web site (www.elektor-elec-tronics.co.uk). The flow chart shown inFigure 3 provides enough informationto give you an idea of what the proces-sor does after being switched on, andhow it responds to pressing any of thefive buttons.

At the beginning, the program waits

two seconds after the power-up tomake sure that there are no longer anyresets active. After this, it initialises thedigital filter by writing data to all theregisters. Table 1 lists the settings thathave been chosen for MODE0 throughMODE3. The same data is written tothe MODE2 and MODE3 registers eachtime the Preset button is pressed. Mostof the settings correspond to those rec-ommended by Burr-Brown for thehardware mode (Soft Mute = OFF, De-emphasis = OFF, Input Data Format &Word Length = I2S 24 bit, Output DataWord Length = 24 bit, LRCIN PolaritySelection = Left Channel is HIGH andRight Channel is LOW, Digital FilterRoll-Off selection = sharp roll-off, Sam-pling Frequency Selection for De-emphasis function = 44.1 kHz). In thiscase, we have deliberately decided notto support the de-emphasis function(which would require an extra connec-tion to the de-emphasis output of theGAL IC), since CD recordings with pre-emphasis are rare.

In the initialisation procedure, thestate of the preset DIP switch S6 con-nected to port 3 is first read. The set-tings of S6 define the default volumelevel. This value is also read every timethe Preset button (S3) is pressed. AfterS6 has been read in, the byte value soobtained is adjusted such that the set-tings of S6 form the five MSBs for boththe left and the right attenuators. Thisamounts to multiplying the read-invalue by 4 and then adding 7 to theresult. The LSB of S6 (switch S6-1) thusforms the fourth bit of the attenuator


MC/LRIP

ML/RESV

DF1704

MD/CKO

BCKIN

LRCIN

WCKO

BCKO

IC6

CLKO

MODE

MUTE

DEM

SF0

SRO

I2S

IW0

DIN

XTI

XTO

RST

DOR

DOL

IW1

OW1

SF1

OW0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

990080 - 11

27

28

1

2

3

4

56

7

8

9

12

34

56

78

910

1112

1314

K5

1516

S3

S2

C16

10µ 63V

C17

100n

5VD

5VD

5VD

DBW

1

Figure 1. Switch S2 on theDAC circuit board must bereplaced by an 8-pin DIL flatcable connector.

data, and has a binaryweight of 8.

The step size of theattenuators in the digitalfilter is 0.5 dB, so the mini-mum step size of S6 is 4 dB.In practice, this providesadequate resolution toallow the desired averagelistening level to be set,even though the maximumdeviation in the level isnever more than±2 dBwhen a final amplifier isdriven directly. The maxi-mum level, which isobtained when all theswitches of S6 are ON, thuscorresponds to the level inthe hardware mode.

We have expressly cho-sen to use the same levelsfor the left and right chan-

nels (with no balance offset), sincepractice shows that balance controlsare almost always set to the middleposition. Otherwise there is somethingwrong with the rest of the installation,such as an incorrect placement of theloudspeakers or something similar. In

addition, you know for sure that thetwo channels are balanced after thepreset button has been pressed.

However, the possibility of attenu-ating one of the channels is providedby two pushbuttons (S4 and S5) thatact as a balance control. The software is


74HC573

IC2

12

13

14

15

16

17

18

19

EN

11C1

1D2

3

4

7

8

9

5

6

1

10A0

9A1

8A2

7A3

6A4

5A5

4A6

3A7

25A8

24A9

21A10

23A11

2A12

1422

OE

20CS1

28

11D0

12D1

13D2

15D3

16D4

17D5

18D6

19D7

IC4

RAM

26CS2

27

WE

626427C256

EPROM

IC3

A10

A11

A12

VPP

A13

A14

10A0

A1

A2

A3

A4

A5

A6

A725

A824

A921

23

14 22

OE

20

CS

28

11D0

12D1

13D2

15D3

16D4

17D5

18D6

19D7

26

27

9

8

7

6

5

4

3

2

1

12

34

56

78

910

K1

12

34

56

78

910

K2

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

S6

12

11

10

9

8

76

5

4

3

2

1

SFH506-36

IC5 2

3

1

X1

16MHz

C2

22p

C3

22p

A0

A1

A2

A3

A4

A5

A6

A7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

C8

100n

C7

100n

C6

100n

A8

A9

A10

A11

A12

A13

A14

A15

C4

220µ 25V

R2

47Ω

C1

10µ 63V

R1

8k

2

B1

B80C1500

C16

22n

C15

22n

C13

22n

C14

22n

K4

7805

IC6

C11

100n

C10

100n

C12

470µ25V

C9

10µ63V

C5

100n

5V

+5V>8V

(ML)

(MC)

(MD)

IC2

20

10

5V5V

5V5V

5V

*

*

*

INT0/P3.2

INT1/P3.3

TXD/P3.1

RXD/P3.0

RD/P3.7

WR/P3.6

T0/P3.4

T1/P3.5

EA/VP

ALE/P

RESET

80C32

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

IC1

39

38

37

36

35

34

33

32

21

22

23

24

25

26

27

28

31

19

X1

18

X2

20

40

17

16

29

30

11

10

12

13

14

15

1

2

3

4

5

6

7

8

9

990080 - 12a

DF1704

S1...S5

PRESET

12

34

56

78

910

K3

S3

S4

S5

S1

S2

VOLUME UP

VOLUME DOWN

PRESET

BALANCE RIGHT

BALANCE LEFT

990080 - 12b

(C) ELEKTOR990080-1

B1

C1

C2

C3

C4

C5

C6

C7C8

C9

C10C11C12

C13

C14

C15

C16

H1

H2H3

H4

H5

H6

H7

H8

H9

H10

IC1

IC2IC3IC4

IC5

IC6

K1

K2

K3

K4

OU

T

OU

T2

R1

R2

S1

S2

S3

S4

S5

S6

X1

990080-1

S1

..S

5

~

~

0+5

V

4

Figure 2. Only a very small amount of hardware is needed. Fivepushbutton switches are used to operate the volume control.


COMPONENTS LIST

Resistors:R1 = 8kΩ2R2 = 47Ω*

Capacitors:C1 = 10µF 63V axialC2,C3 = 22pFC4 = 220µF 25V radial*C5-C8,C10,C11 = 100nF ceramicC9 = 10µF 63V radialC12 = 470µF 25V radialC13-C16 = 22nF ceramic

Semiconductors:B1 = B80C1500 (rectangular case)IC1 = 80C32-16IC2 = 74HC573IC3 = 27C256 (programmed, order

code 006506-1)IC4 = 6264IC5 = SFH506-36*IC6 = 7805

Miscellaneous:K1,K2 = 10-way boxheaderK3 = 10-way PCB connector for

flatcableK4 = 2-way PCB terminal blockS1-S5 = pushbutton, 1 make

contact, e.g., ITT/Schadow D6-Q-BK + D6Q-BK-CAP

S6 = 5- or 6-way DIP-switchX1 = 16MHz quartz crystal PCB, order code 990080-1 (see

Readers Services page and Elektorwebsite)

PCB & programmed EPROM: ordercode 990080-C

*) if required

START

wait 2 sec

CHECK KEYPAD

initialisation

initialisationKEY=S3PRESET

mute

L + 1R + 1

KEY=S3& S5

Y

Y

N

N

N

KEY=S1VOLUME

UP

Y L < MAX&

R < MAX

Y

N

L - 1R - 1

N

KEY=S2VOLUMEDOWN

Y L > 0&

R > 0

Y

N

L + 1

N

KEY=S5BALANCE

LEFT

YR > 0

990080 - 13

N

Y L < R&

L < MAX

Y

R - 1Y

N

R + 1

N

KEY=S4BALANCE

RIGHT

YL > 0

N

Y R < L&

R < MAX

Y

L - 1YN

3 Figure 3. Flow diagram ofthe software. The com-plete listing is availableon the Elektor website.

(C) ELEKTOR990080-1

990080-2(C) ELEKTOR

D1 H1H2

IC1

R1 R

2

R3

990080-2

E 0+

R

990080-2(C) ELEKTOR

Figure 4. The ‘keypad’can be separated fromthe rest of the circuitboard.

written such that the balance controlworks the same way as a ‘real’ balancepotentiometer: if the balance isadjusted to the right the left channel isattenuated, and vice versa. In order tomaintain the same level when the bal-ance is adjusted back and forth, when-ever the direction of the adjustment ischanged the already attenuated chan-nel is first returned to the level of theother channel before the other channelis attenuated.

With the volume control, it is neces-sary to check that the control valuedoes not exceed the maximum levelwhen the volume is increased or theminimum level when the volume isdecreased. If the pushbutton in ques-tion is held depressed, a program looprepeatedly increments or decrementsthe attenuator value by 1. Of course,the maximum and minimum valuesmust be checked for the balanceadjustment as well.

Prior to the initialisation, the threeLSBs of port 1 are defined as outputsand the rest as inputs. After the initial-isation, an endless loop monitors port1. Each pushbutton switch has its ownfunction, and there is only one validcombination of two switches, which isS1+S5 for the mute function. The pro-gram checks in turn whether S3,S1+S5, S1, S2, S5 or S4 is pressed.Pressing any other combination ofswitches has no effect.

P R I N T E D C I R C U I TB O A R DThe printed circuit board for the digi-tal volume control is shown in Fig-ure 4. As already mentioned, this is laidout such that the part with the five

pushbutton switches can be sawedloose so that it can (for example) bemounted on the front panel of theenclosure.

What other practical advice can wegive regarding the circuit board? Apartfrom the four ICs, the voltage regula-tor and the two connectors, there’sactually very little on the board. Wecan thus limit ourselves to suggestingthat you use good-quality sockets, payattention to the polarisation of the elec-trolytic capacitors, and — don’t forgetthe wire bridges (yes, it’s still the mostcommonly made mistake…)!

As can be seen in the photograph(Figure 5), it is easy to build the volumecontrol into the enclosure of the AudioDAC 2000. Just mount the main circuitboard on the bottom of the enclosureusing stand-offs, and the pushbuttonboard at the front, possibly with the aid

of an angle bracket. Plug in the flatca-ble between K2 and K3 of the volumecontrol, and then the flatcable betweenK1 and the ‘S2 connector’ of the DACcircuit board, and you’re all done.Oops, not quite: naturally you have toconnect an 8-V supply voltage (AC orDC) to K4. However, if you have usedthe transformer board described in theJanuary issue of Elektor Electronics toprovide power to the Audio DAC, allyou have to do is connect two wires toconnector K4 on the transformer board!

(990080-1)


Table 1. Summary of thesettings for registersMODE0 through MODE3.

MODE0 MODE1 MODE2 MODE3

B0 1 1 1 1B1 1 1 0 0B2 1 1 0 (res) 0B3 S6-1 S6-1 1 0B4 S6-2 S6-2 0 0 (res)B5 S6-3 S6-3 1 0B6 S6-4 S6-4 1 0B7 S6-5 S6-5 0 (res) 0B8 1 1 0 (res) 0 (res)B9 0 1 0 1B10 0 0 1 1B11...B15 voor alle registers 0 (res)

(res = reserved)

Figure 5. It’s easy to fitthe volume control intothe enclosure of theAudio DAC 2000.

DAC2000

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