DAC Reconstruction Filter - EECS Instructional Support ...ee247/fa05/lectures/L17_2_f05.pdf · –...

EECS 247 Lecture 17: Data Converters © 2005 H.K.

EE247Lecture 17

DAC Converters (continued)– Reconstruction filter

• DAC self calibration techniques– Current copiers– Dynamic element matching

ADC Converters• Sampling

– Sampling switch induced distortion– Sampling switch charge injection

• Complementary switch• Use of dummy device• Bottom-plate switching

EECS 247 Lecture 17: Data Converters © 2005 H.K. Page 2

DAC Reconstruction Filter

• Need for and requirements depend on application

• Tasks:– Correct for sinc distortion– Remove “aliases”

(stair-case approximation)

B fs/2

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

DA

C In

put

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

sinc

0 0.5 1 1.5 2 2.5 3

x 106

0

0.5

1

DA

C O

utpu

t

Frequency


Reconstruction Filter Options

• Digital and SC filter possible only in combination with oversampling (signal bandwidth B << fs/2)

• Digital filter– Band limits the input signal à prevent aliasing– Could also provide high-frequency pre-emphasis to

compensate in-band sinc amplitude droop associated with the inherent DAC ZOH function

DigitalF ilter

DAC SCFilter

ZOH CTFilter


DAC Implementation Examples• Untrimmed segmented

– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC December 1986, pp. 983

– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter,” JSSC March 2001, pp. 315

• Current copiers:– D. W. J. Groeneveld et al, “A Self-Calibration Technique for

Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517

• Dynamic element matching:– R. J. van de Plassche, “Dynamic Element Matching for High-

Accuracy Monolithic D/A Converters,” JSSC December 1976, pp. 795


2µ tech., 5VsupplySegmented (6+2)8x8 array


Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistance


Current-Switched DACs in CMOS( )

( )

( )

( )

M 1

M 2 M 1 M 3 M 1

M 4 M 1 M 5 M 1

M 2

M 1

M 1

M 1

M 1

M 1

M 1

M 1

2GS th1

GS GS GS GS

GS GS GS GS2

2GS th2 1

GS th

1m

GS th2

m2 1 1 m

2m

3 1 1 m

V VI kV V 4RI, V V 7RIV V 9RI, V V 10RI

4RI1V VI k I

V V2I

gV V

4RgI I I 1 4Rg12

7RgI I I 1 7Rg12

I

−== − = −= − = −

−−= = − =

−

→ = ≈ −−

→ = ≈ −−

→ ( )

( )

M 1

M 1

M 1

M 1

2m

4 1 1 m

2m

5 1 1 m

9RgI I 1 9Rg12

10RgI I I 1 10Rg12

= ≈ −−

→ = ≈ −−

Iout

•Assumption: RI is small compared to transistor gate overdriveà Desirable to have gm small

Example: 5 unit element current sources

VDD

I1 I2 I3 I4

Rx4I Rx3I Rx2I

M1 M2 M3 M4 I5M5

RxI


Current-Switched DACs in CMOSExample: INL of 7 unit element DAC

Input

INL

[LS

B]

Example: 7 unit element current source DAC- assume gmxR=1/100•If switching of current sources sequential (1-2-3-4-5-6-7)

à INL= +0.25LSB•If switching of current sources symmetrical (4-3-5-2-6-7 )

à INL = +0.09, -0.058LSB

-0.1

0

0.1

0.2

0.3

1 2 3 4 5 6 7

Sequential current source switchingSymmetrical current source switching

0


Current-Switched DACs in CMOSExample: DNL of 7 unit element DAC

Input

DN

L [L

SB

]

Example: 7 unit element current source DAC- assume gmxR=1/100•If switching of current sources sequential (1-2-3-4-5-6-7)

à DNLmax= + 0.15LSB•If switching of current sources symmetrical (4-3-5-2-6-7 )

à DNL = + 0.15LSB

-0.2

-0.1

0

0.1

0.2

1 2 3 4 5 6 7

Sequential current source switchingSymmetrical current source switching


More recent published DAC using symmetrical switching built in 0.35µ/3V analog/1.9V digital, area x10 smaller compared to previous example

(5+5)



I

I/2 I/2

Current Divider

16bit DAC (6+10)- MSB DAC uses calibrated current sources



I

I/2 I/2

Ideal Current Divider

Current Divider Accuracy

I

I/2+dId /2

Real Current Divider

M1& M2 mismatched

d1 d 2d

d d1 d 2

d d

WLd

thWLd GS th

I II

2

dI I I

I I

ddI 2dV

I V V

+=

−=

= × +

−

I/2-dId /2

M1 M2M1 M2

àProblem: Device mismatch could severely limit DAC accuracy



Dynamic Element Matching

( ) ( )

(1) ( 2 )2 2

2

1 1o

o1

I II

21 1I

2 2I

for smal l2

+=

− ∆ + + ∆=

≈ ∆

( )( )

(1) 1 o 11 2(1) 1 o 12 2

I I 1

I I 1

= + ∆

= − ∆

/ 2 error ∆1

I1

During Φ1 During Φ2

I2

fclk

Io

Io/2Io/2( )( )

( 2 ) 1 o 11 2( 2 ) 1 o 12 2

I I 1

I I 1

= − ∆

= + ∆



Dynamic Element Matching

( )( )

( )( )( )214

1

2)1(

121)1(

3

121)1(

2

121)1(

1

11

1

1

1

∆+∆+=∆+=

∆−=

∆+=

o

o

o

I

II

II

II ( )( )

( )( )( )214

1

2)2(

121)2(

3

121)2(

2

121)2(

1

11

1

1

1

∆−∆−=∆−=

∆+=

∆−=

o

o

o

I

II

II

II

During Φ1 During Φ2

( )( ) ( )( )

( )21

2121

)2(3

)1(3

3

14

21111

4

2

∆∆+=

∆−∆−+∆+∆+=

+=

o

o

I

I

III

E.g. ∆1 = ∆2 = 1% à matching error is (1%)2 = 0.01%

/ 2 error ∆1

I1

I2

fclk

Io

Io/2

/ 2 error ∆2

I3 I4

fclk

Io/4Io/4


SummaryD/A Converter

• D/A architecture – Unit element – complexity proportional to 2B- excellent DNL – Binary weighted- complexity proportional to B- poor DNL– Segmented- unit element MSB(B1)+ binary weighted LSB(B2)à complexity

proportional (2B1-1) + B2 – DNL compromise between the two• Static performance

– Component matching• Dynamic performance

– Glitches• DAC improvement techniques

– Symmetrical DAC element switching rather than sequential switching– Current source self calibration– Dynamic element matching


MOS Sampling Circuits


Re-Cap

• How can we build circuits that "sample"

Analog Post processing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Anti-AliasingFilter

Sampling+Quantization

"Bits to Staircase"

Reconstruction Filter


Ideal Sampling

• In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage vIN onto the capacitor C

• Not realizable!

vIN vOUT

CS1

φ1

φ1

T=1/fS


Ideal T/H Sampling

vIN vOUT

CS1

φ1

• Vout tracks input when switch is closed• Grab exact value of Vin when switch opens• "Track and Hold" (T/H) (often called Sample & Hold!)

φ1

T=1/fS


Ideal T/H Sampling

ContinuousTime

T/H signal(SD Signal)

Clock

DT Signal

time


Practical Sampling

vIN vOUT

CM1

φ1

• Switch induced noise power à kT/C • Finite Rswà limited bandwidth• Rsw = f(Vin) à distortion• Switch charge injection • Clock jitter


kT/C Noise

In high resolution ADCs kT/C noise usually dominates overall error (power dissipation considerations).

2

2

1212

12

−≥

∆≤

FS

B

B

B

VTkC

CTk

0.003 pF0.8 pF13 pF

206 pF52,800 pF

812141620

Cmin (VFS = 1V)B


Acquisition Bandwidth

• The resistance R of switch S1 turns the sampling network into a lowpass filter with risetime = RC = τ

• Assuming Vin is constant during the sampling period and C is initially discharged

vIN vOUT

CS1

φ1

R

( )τ/1)( tinout evtv −−=


Switch On-Resistance

Example:B = 14, C = 13pF, fs = 100MHz

T/τ >> 19.4, R << 40Ω

vIN vOUT

CS1

φ1

φ1

T=1/fS

R

( )

( )

12

12

Worst Case:

12 ln 2 1

1 12 ln 2 1

s

in outs

fin

in FS

B

Bs

V V tf

V e

V V

T

Rf C

τ

τ

−

− = << ∆

<< ∆=

<< −−

<< −−


Switch On-Resistance

( ) ( )

( )

( )( )

0

1,

2

1 1

1 for

1

DS

D triodeDSD triode ox GS TH DS

ON DS V

ON

ox GS th ox DD th in

o

ox DD th

oON

in

DD th

dIW VI C V V V

L R dV

RW W

C V V C V V VL L

RW

C V VL

RR

VV V

µ

µ µ

µ

→

= − − ≅

= =− − −

=−

=−

−


Sampling Distortion

in

DD th

outT V

12 V V

in

v

v 1 e τ

− − −

= −

10bit ADC & T/τ = 10VDD – Vth = 2V VFS = 1V


Sampling Distortion

10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V

• SFDR is very sensitive to sampling distortion

• Solutions:• Overdesignà Larger

switchesà increased switch

charge injectionà increased switch

drain & source C• Complementary switch• Maximize VDD/VFSà decreased dynamic

range• Constant VGS ? f(Vin)à …


Practical Sampling

22 1

12B

BFS

C k TV

−≥

( )1 for inON o o ox DD th

DD th

WVg g g C V V

V V Lµ = − = − −

( )1 1

2 ln 2 1Bs

Rf C

<< −−

• kT/C noise

• Finite Rswà limited bandwidth

• gsw = f(Vin) à distortion

• Switch charge injection • Clock jitter

vINvOUT

CM1

φ1


Sampling DistortionEffect of Supply Voltage



• Effect of lower supply voltage on sampling distortionà HD3 increases by (VDD1/VDD2)2

à HD2 increases by (VDD1/VDD2)


Sampling Distortion

10bit ADC T/τ = 20VDD – Vth = 2V VFS = 1V

• SFDR à sensitive to sampling distortion -improve linearity by:

• Larger VDD • Higher sampling bandwidth

• Solutions:• Overdesignà Larger

switchesà Increased switch

charge injectionà Increased nonlinear S &D junction cap.

• Maximize VDD/VFSàDecreased dynamic range if VDD const.

• Complementary switch• Constant & max. VGS ? f(Vin)


Complementary Switch

φ1φ1B

φ1

φ1B

gon

gop

goT =go

n + gopgo

•Complementary n & p switch advantages:•Increases the overall conductance•Linearize the switch conductance for the range Vtp< Vin <Vdd-Vtn


Complementary Switch IssuesSupply Voltage Evolution

• Supply voltage scales down with technology scaling• Threshold voltages do not scale accordingly

Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.


Complementary SwitchEffect of Supply Voltage Scaling

gon

gop

goT =go

n + gopgo

φ1φ1B

φ1

φ1B

•As supply voltage scales down input voltage range for constant go shrinksà Complementary switch not effective when VDD becomes comparable to Vth


Boosted & Constant VGS Sampling

• Increase gate overdrive voltage as much as possible + keep VGSconstantØ Switch overdrive voltage is independent of signal levelØ Error from finite RON is linear (to first order)Ø Lower Ron achieved à lower time constant

VGS=const.


Constant VGS Sampling

(= voltage @ the switch source terminal)


Constant VGS Sampling Circuit

VP1100ns

M12

M8

M9

M6

M11VS1

1.5V1MHz

Chold

P

C1 C2

M1 M2

VDD=3V

M3

C3

M5

M4

P

P_N

This Example: All device sizes:10µ/0.35µAll capacitor size: 1pF

P_N

Vg

Va Vb

Sampling switch & C


Clock Voltage Doubler

C1 C2

M1 M2

VP1 Clock period: 100ns

P_N

P_Boost

VDD

2VDD

0

VDD=3V

R1 R2

*R1 & R2=1GOhmà dummy resistors added for simulation only

P


Constant VGS Sampler: Φ LOW

• Sampling switch M11 is OFF

• C3 charged to VDD

Input voltagesource

M3

C3

M12

M4

OFF

VS11.5V1MHz

Chold1pF

~ 2 VDD(boosted clock)

VDD

VDD

OFF M11OFF

DeviceOFF

VDD=3V


Constant VGS Sampler: Φ HIGH

• C3 previously charged to VDD

• M8 & M9 are on:C3 across G-S of M11

• M11 on with constant VGS = VDD

Constant Vgs Switch: P is HIGH

C31pF

M8

M9 M11

VS11.5V1MHz

Chold1pF

VDD


Constant VGS Sampling

Input Switch VGate

Input Signal

Chold Signal


Complete Circuit

Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.

Clock Multiplier

Switch

M7 & M13 for reliability


Advanced Clock Boosting

Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 1769-1780, Dec. 2000]


Advanced Clock Boosting Technique

• Gate tracks average of input and output, reduces effect of I·R drop at high frequencies

• Bulk also tracks signal ⇒ reduced body effect (technology used allows connecting bulk to S)

• SFDR = 76.5dB at fin=200MHz (measured)

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314

Sampling Switch


Switch Off-Mode Feedthrough Cancellation

Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 200MHz IF-sampling frontend," ISSCC 2002, Dig. Techn. Papers, pp. 314


Practical Sampling

vIN vOUT

CM1

φ1

• Rsw = f(Vin) à distortion• Switch charge injection


Sampling Switch Charge Injection

VIN VO

Cs

M1

VG

• First assume VIN is a DC voltage• When switch turns off à offset voltage induced on Cs• Why?

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t


SamplingSwitch Charge Injection

• Channel à distributed RC network• Channel to substrate junction capacitance à distributed & variable• Over-lap capacitance Cov = LDxWxCox associated with GS & GD overlap

MOS xtor operating in triode regionCross section view

Distributed channel resistance & gate & junction capacitances

S

G

D

B

LD

L

Cov Cov


Switch Charge InjectionSlow Clock

• Since clock fall time >> device speed à During the period (t- to toff) current in channel discharges channel charge into low impedance signal source

• Only source of error à Charge transfer from Cov into Cs

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

tt-


Switch Charge InjectionSlow Clock

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t

D

Cov

VG

( )

( )

( )

( )

ovi th L

ov s

ovi th L

s

o i os

ov ovos th L

s s

CV V V V

C C

CV V V

CV V 1 V

C Cwhere ; V V V

C C

ε

ε

∆ = − + −+

≈ − + −

= + +

= − = − −

t-

Cs


Switch Charge InjectionSlow Clock- Example

( )

' 2ov ox th

ov

s

ovos th L

s

C 0.3 fF / C 5 fF / V 0.5V

C 12 x0.3 fF /.36% 7 bi t

C 1pF

CV V V 1.8mV

C

µ µ

µ µε

= = =

= − = − = − → −

= − − = −

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t

VIN VO

Cs=1pF

M1

VG 12µ/0.35µ

t-


Switch Charge InjectionFast Clock

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t

VIN VO

Cs=1pF

M1

VG

• Sudden gate voltage drop à no gate voltage to establish current in channel àchannel charge has no choice but to escape out towards S & D


Switch Charge InjectionFast Clock

( )

( ) ( ) ( )( )

( )

( ) ( )

ov cho H L

ov s s

ox H i thov DH L

ov s s

o i os

ox

s

ov ox H thos H L

s s

C 1 QV V V

C C 2 C

WC V V VC 1 L 2LV V

C C 2 C

V V 1 V

1 WC Lwhere

2 C

C 1 WC L V VV V V

C 2 C

ε

ε

∆ = − − − ×+

− −−≈ − − − ×

+

= + +

= − ×

−= − − − ×

• Assumption à channel charge divided equally between S & D • Source of error à channel charge transfer + charge transfer from Cov into Cs

VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t


Switch Charge InjectionFast Clock- Example

( ) ( )

2ov ox th DD

ox

s

ov ox H thos H L

s s

C 0.3 fF / C 5 fF / V 0.5V V 3V

WLC 12 x0.35x5 fF /1 / 2 2.1% 4.5 bit

C 1pF

C 1 WC L V VV V V 9mV 26.3mV 45.3mV

C 2 C

µ µ

µ µε

= = = =

= − = = − → −

−= − − − × = − − = −

VIN VO

Cs=1pF

M1

VG 12µ/0.35µ VG

t

VH

VIN

VL

VIN +Vth

VO

VIN

toff

∆V

t


Switch Charge InjectionExample

à Both errors are a function of clock fall time, input voltage level, source impedance & sampling capacitance

Clock fall time

ε VOS

Clock fall time

2.1%

.36%

45mV

1.8mV


Switch Charge InjectionError Reduction

( )

( )

( )( )

sON s

ox GS th

cho

s

ox H i thso

sox GS th

2

CR C W

C V VL

1 QV

2 C

WC L V V VC 1FOM V W 2 CC V V

L

LFOM

µ

µ

µ

τ

τ

= =−

∆ = −

− −= ∆ ≈ ×

−

≈

× ×

• How do we reduce the error?àReduce switch?

àReducing switch size increases τ à increased distortionà not a viable solutionàSmall τ and ∆V à use minimum chanel lengthàFor a given technology τ x ∆V=conts.


Sampling Switch Charge InjectionSummary

• Extra charge injected onto sampling capacitor @ switch device turn-off– Charge sharing with Cov

– Channel charge transfer

• Issues:– DC offset– Input dependant error voltage à distortion

• Solutions:– Complementary switch?– Addition of dummy switches?– Bottom-plate sampling?


Switch Charge InjectionComplementary Switch

• In slow clock case if area of devices are equal à effect of overlap capacitor for n & p devices cancel to first order (matching n & p area)

φ1φ1B

φ1

φ1B

VG

t

VH

VIN

VL


Switch Charge InjectionComplementary Switch

Fast Clock

• In fast clock case §Offset cancelled for equal device area§Input voltage dependant error worse!

φ1

φ1B

VG

t

VH

VIN

VL

( )

( )

( )

ch n n ox n H i th n

th pch p p ox p i

ch p ch no

s s

o i os

n ox n p ox p

s

Q W C L V V V

VQ W C L V VL

Q1 QV

2 C C

V V 1 V

W C L W C L1

2 C

ε

ε

− −

−−

− −

= − −

= − −

∆ = −

= + +

+= − ×


Switch Charge InjectionDummy Switch

VIN VO

Cs

t

VH

VIN

VL

VG VGB

• Dummy switch same L as main switch but half W • Main device clock goes low, dummy device goes high à dummy switch acquires

same amount of channel charge main switch needs to lose§ Effective only if exactly half of the charge transferred to M2 and good matching

between clock fall/rise

WM2=1/2WM1

VG VGB

M1M2


Switch Charge InjectionDummy Switch

VIN VOM1

VG

M2

VGB

§ To guarantee half of charge goes to each sideà create the same environment on both sidesvAdd C equal to sampling capacitor to the other side of the switch +

add fixed resistor§ Degrades sampling bandwidth

CsCs

RWM2=1/2WM1


Dummy SwitchDummy Switch Effectiveness Test

Ref: L. A. BIENSTMAN et al, “ An Eight-Channel 8 13it Microprocessor Compatible NMOS D/A Converter with Programmable Scaling”, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980

• Dummy switch àW=1/2Wmain

• Note large Lsà good device

area matching


Switch Charge InjectionBottom Plate Sampling

VI+

VO+

M1A

VI-

VO-M1B •Switches M2A@ B are opened slightly earlier

compared to M1A&Bà Injected charge by the opening of M2AB is constant & eliminated when used differentially

•Since bottom plate of Cs is open when M1A&B are openedà no charge injected on Cs

φ1b

φ1a

M2B

M2A

φ1aVH

VL

t

φ1bCs

Cs

DAC Reconstruction Filter - EECS Instructional Support ...ee247/fa05/lectures/L17_2_f05.pdf · –...

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