BENEFITS

High-speed and high-resolution

Works with Xilinx and Altera FPGAs

Industry standard form factor

Rugged and reliable

FEATURES

Dual-channel 2.5 Gsps, 14-bit DAC

Up to 2.3 GHz output bandwidth

Works with carrier board of your choice

FMC/VITA 57 compliant FMC

Air and conduction-cooled

PERFORMANCE

1.6 Gsps to 2.5 Gsps sampling rate

Up to 2.3 GHz onput bandwidth

Power < 8 watts

DATASHEET

www.delphieng.com

DAC-D2500 Dual Channel 2.5 Gsps, 14-bit DAC FMC

The DAC-D2500 reaffirms DEG’s leadership position in the high

speed, high performance digital-analog conversion market. By

leveraging Analog Devices highest performance digital to analog

converter, Delphi engineers have created an FMC card the leads the

industry in both resolution and dynamic performance. This FPGA

mezzanine card (FMC) outputs two channels of up to 2.3 GHz

analog output at 2.5 Gsps and 14-bit resolution. Based on the

VITA57 specification, the DAC-D2500 enables direct coupling of

unparalleled digital-analog conversion capability with the

VME/VXS/AMC/VPX/PCIe carrier board of your choice. DEG

engineers have designed this product and associated HDL firmware

to work with both Altera and Xilinx FPGAs.

Leading high-performance DAC and a cost-effective solution

The DAC-D2500 is based on the latest offering by Analog Devices

and the proven FMC form factor. ADI’s latest innovation, with the

AD9739A, sets the benchmark for high performance analog-digital

conversion. By coupling this core architecture with the compact

and flexible FMC form factor, DEG has enabled customers to rapidly

and cost-effectively integrate the latest generation of digital-analog

conversion capability with very high performance DSP processing

carrier boards. This flexible approach reduces overall power con-

sumption, footprint, and cost while increasing ruggedness and relia-

bility.

Maximum Density and Rugged

The DAC-D2500 uses high-pin count (HPC) FMC connectors. The

HPC connector is required and fully utilized to accomplish the

bandwidth required at 2.5 Gsps and 14-bit.s of resolution. The

board is designed to perform in commercial, rugged, and

conduction-cooled environments.

Analog Output

The analog output is single-ended with a full-scale output

of .93 Vpp. The analog output signal bandwidth extends up

to 2.3 GHz.

Clocks and Triggers

The user can provide a clock input signal or use the onboard

PLL to provide the clock for the digital to analog converters.

The clock input accommodates frequencies of 1.6 GHz to 2.5

GHz but may operate at clock frequencies between 200 MHz

and 550 MHz.

The various PLL options can be locked to an external 10 MHz

to 100 MHz (divisible by 10 MHz increments) reference

provided through the external clock input connector. PLL

reference input must be a sine wave or square wave, with an

amplitude range of –2 dBm to +10 dBm at 10 MHz with a 50%

duty cycle.

Trigger input must be 800 mV to 3.3 V peak-to-peak signal.

Rise time of less than 10 nanoseconds is recommended. A

trigger event is initiated by a positive transition on the trigger

input.

DACLink

FMC modules are distinct and separate from the FPGA

devices that support them. Initiation and control of the

DAC-D2500 is accomplished with DACLink, Delphi’s VHDL

source code project. DACLink provides an interface between

the DAC-D2500 and a host FPGA board. Board support

packages are required for each unique host card.

Analog Specifications

Number of channels 2

Sampling rate 1.6 Gsps - 2.5 Gsps

Output bandwidth 5 MHz - 2.2 GHz, 650 MHz - 4 GHz

Output impedance 50 Ω, AC-coupled

Full-scale Output 1.1 mW (0.4dBm)

Resolution 14 bits

Phase delay bet channels < 1nz

SFDR -69 dBc @ 100 MHz; -60 dBc @ 950 MHZ

Noise Special Density (NSD) -160 dBm/Hz; 100 MHz - 850 MHz

Clock and Trigger Specifications

Connectors SMA front panel

Clock input 50 Ω, AC-coupled

Clock input frequency 1) Sampling Frequency 2) 10 MHz reference

Internal Reference Accuracy 1 ppm (-4°C to +85°C)

Std PLL frequency Variable PLL Frequency

Trigger threshold 12V ± 2V resolution, 11-bit

Part Number Coupling Rugged Level Conformal Coat

DAC-D2500 AC Commercial —

DAC-D2500-C AC Commercial √

DAC-D2500-R AC Rugged —

DAC-D2500-RC AC Rugged √

DAC-D2500-CC AC Conduction —

DAC-D2500-CCC AC Conduction √

www.delphieng.com

DAC-D2500 Performance Specifications

485 East 17th Street, Ste 400, Costa Mesa, CA 92627

Tel: 949.791.4000 Email: sales@delphieng.com

www.delphieng.com

DAC-D2500-DS-061714

Copyright © 2014 Delphi Engineering Group

A Signal of Greater Interest is a trademark of Delphi Engineering Group. Altera is a registered trademark of Altera Corporation. Xilinx is a registered trademark

of Xilinx Inc. Other products mentioned may be trademarks or registered trademarks of their respective holders.

ADF-D1000/D1600/D1800/D2000 Environmentals

Environmental Specifications

Commercial Rugged Conduction-Cooled

Operating temperature 0°C to +50°C (inlet air) -40°C to +71°C (inlet air) -40°C to +71°C (at card edge)

Storage temperature -55°C to +85°C -55°C to +125°C -55°C to +125°C

Humidity (non-condensing) 0 to 95% 0 to 100% 0 to 100%

Vibration (random) 0.01g2/Hz, 15-2,000 Hz 0.04g2/Hz, 15-2,000 Hz 0.04g2/Hz, 15-2,000 Hz

Shock 20 g peak 30 g peak 40 g peak

Based on MIL-STD-810F

DAC-D2500 Block Diagram

About DEG

The Delphi Engineering Group (DEG) provides a full range of high-performance COTS-based and customized digital receiver technology, products, and services for mission-critical applications in the aerospace, defense, and communications industries.