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Cyclone V Device Overview

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CV-51001 | 2018.05.07Latest document on the web: PDF | HTML

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Contents

Cyclone V Device Overview................................................................................................. 3Key Advantages of Cyclone V Devices............................................................................. 3Summary of Cyclone V Features.....................................................................................4Cyclone V Device Variants and Packages......................................................................... 5

Cyclone V E........................................................................................................5Cyclone V GX..................................................................................................... 7Cyclone V GT......................................................................................................9Cyclone V SE.................................................................................................... 12Cyclone V SX....................................................................................................14Cyclone V ST.................................................................................................... 15

I/O Vertical Migration for Cyclone V Devices...................................................................18Adaptive Logic Module................................................................................................ 18Variable-Precision DSP Block........................................................................................19Embedded Memory Blocks........................................................................................... 21

Types of Embedded Memory............................................................................... 21Embedded Memory Capacity in Cyclone V Devices................................................. 21Embedded Memory Configurations.......................................................................22

Clock Networks and PLL Clock Sources.......................................................................... 22FPGA General Purpose I/O...........................................................................................23PCIe Gen1 and Gen2 Hard IP....................................................................................... 24External Memory Interface.......................................................................................... 24

Hard and Soft Memory Controllers.......................................................................24External Memory Performance............................................................................ 25HPS External Memory Performance......................................................................25

Low-Power Serial Transceivers......................................................................................25Transceiver Channels......................................................................................... 25PMA Features................................................................................................... 26PCS Features....................................................................................................27

SoC with HPS.............................................................................................................28HPS Features....................................................................................................28FPGA Configuration and Processor Booting............................................................30Hardware and Software Development.................................................................. 31

Dynamic and Partial Reconfiguration............................................................................. 31Dynamic Reconfiguration....................................................................................31Partial Reconfiguration....................................................................................... 31

Enhanced Configuration and Configuration via Protocol....................................................32Power Management.................................................................................................... 33Document Revision History for Cyclone V Device Overview...............................................33

Contents

Cyclone V Device Overview2

Cyclone V Device OverviewThe Cyclone V devices are designed to simultaneously accommodate the shrinkingpower consumption, cost, and time-to-market requirements; and the increasingbandwidth requirements for high-volume and cost-sensitive applications.

Enhanced with integrated transceivers and hard memory controllers, the Cyclone Vdevices are suitable for applications in the industrial, wireless and wireline, military,and automotive markets.

Related Information

Cyclone V Device Handbook: Known IssuesLists the planned updates to the Cyclone V Device Handbook chapters.

Key Advantages of Cyclone V Devices

Table 1. Key Advantages of the Cyclone V Device Family

Advantage Supporting Feature

Lower power consumption Built on TSMC's 28 nm low-power (28LP) process technology and includes anabundance of hard intellectual property (IP) blocks

Up to 40% lower power consumption than the previous generation device

Improved logic integration anddifferentiation capabilities

8-input adaptive logic module (ALM) Up to 13.59 megabits (Mb) of embedded memory Variable-precision digital signal processing (DSP) blocks

Increased bandwidth capacity 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers Hard memory controllers

Hard processor system (HPS)with integrated Arm* Cortex*-A9MPCore* processor

Tight integration of a dual-core Arm Cortex-A9 MPCore processor, hard IP, and anFPGA in a single Cyclone V system-on-a-chip (SoC)

Supports over 128 Gbps peak bandwidth with integrated data coherency betweenthe processor and the FPGA fabric

Lowest system cost Requires only two core voltages to operate Available in low-cost wirebond packaging Includes innovative features such as Configuration via Protocol (CvP) and partial

reconfiguration

CV-51001 | 2018.05.07

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2008Registered

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Summary of Cyclone V Features

Table 2. Summary of Features for Cyclone V Devices

Feature Description

Technology TSMC's 28-nm low-power (28LP) process technology 1.1 V core voltage

Packaging Wirebond low-halogen packages Multiple device densities with compatible package footprints for seamless migration between

different device densities RoHS-compliant and leaded(1)options

High-performanceFPGA fabric

Enhanced 8-input ALM with four registers

Internal memoryblocks

M10K10-kilobits (Kb) memory blocks with soft error correction code (ECC) Memory logic array block (MLAB)640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IPblocks

Variable-precision DSP Native support for up to three signal processing precision levels(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the samevariable-precision DSP block

64-bit accumulator and cascade Embedded internal coefficient memory Preadder/subtractor for improved efficiency

Memory controller DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiverI/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP withmultifunction support, endpoint, and root port

Clock networks Up to 550 MHz global clock network Global, quadrant, and peripheral clock networks Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops(PLLs)

Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB) Integer mode and fractional mode

FPGA General-purposeI/Os (GPIOs)

875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS tran