Cyclone V Device Handbook Volume 2: Transceivers

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Transcript of Cyclone V Device Handbook Volume 2: Transceivers

  • Cyclone V Device HandbookVolume 2: Transceivers

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    CV-5V32016.01.28

    101 Innovation DriveSan Jose, CA 95134www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=CV-5V3mailto:TechDocFeedback@altera.com?subject=Feedback%20on%20Cyclone%20V%20Device%20Handbook%20Volume%202:%20Transceivers%20(CV-5V3%202016.01.28)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Transceiver Architecture in Cyclone V Devices................................................. 1-1Architecture Overview................................................................................................................................ 1-2

    Transceiver Banks............................................................................................................................ 1-36.144 Gbps CPRI Support Capability in GT Devices..................................................................1-8Transceiver Channel Architecture.................................................................................................1-8

    PMA Architecture........................................................................................................................................1-8Transmitter PMA Datapath........................................................................................................... 1-9Receiver PMA Datapath................................................................................................................1-16Transmitter PLL.............................................................................................................................1-21Clock Divider..................................................................................................................................1-26Calibration Block........................................................................................................................... 1-27

    PCS Architecture........................................................................................................................................1-29Transmitter PCS Datapath........................................................................................................... 1-30Receiver PCS Datapath..................................................................................................................1-36

    Channel Bonding....................................................................................................................................... 1-55PLL Sharing................................................................................................................................................ 1-55Document Revision History.....................................................................................................................1-55

    Transceiver Clocking in Cyclone V Devices....................................................... 2-1Input Reference Clocking........................................................................................................................... 2-1

    Dedicated Reference Clock Pins.................................................................................................... 2-2Fractional PLL (fPLL)......................................................................................................................2-4

    Internal Clocking......................................................................................................................................... 2-5Transmitter Clock Network........................................................................................................... 2-6Transmitter Clocking.................................................................................................................... 2-10Receiver Clocking.......................................................................................................................... 2-15

    FPGA FabricTransceiver Interface Clocking.......................................................................................2-18Transceiver Datapath Interface Clocking...................................................................................2-21Transmitter Datapath Interface Clocking.................................................................................. 2-21Receiver Datapath Interface Clock.............................................................................................. 2-25

    Document Revision History.....................................................................................................................2-29

    Transceiver Reset Control in Cyclone V Devices............................................... 3-1PHY IP Embedded Reset Controller.........................................................................................................3-1

    Embedded Reset Controller Signals.............................................................................................. 3-1Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

    Power-Up.....................................................................................................................................3-3Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

    Operation.....................................................................................................................................3-4User-Coded Reset Controller..................................................................................................................... 3-5

    User-Coded Reset Controller Signals............................................................................................3-6

    TOC-2 Cyclone V Device Handbook Volume 2: Transceivers

    Altera Corporation

  • Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up ................................................................................................................................................ 3-7

    Resetting the Transmitter with the User-Coded Reset Controller During DeviceOperation.....................................................................................................................................3-8

    Resetting the Receiver with the User-Coded Reset Controller During Device Power-UpConfiguration..............................................................................................................................3-9

    Resetting the Receiver with the User-Coded Reset Controller During Device Operation.....................................................................................................................................................3-10

    Transceiver Reset Using Avalon Memory Map Registers....................................................................3-11Transceiver Reset Control Signals Using Avalon Memory Map Registers............................3-11

    Clock Data Recovery in Manual Lock Mode......................................................................................... 3-12Control Settings for CDR Manual Lock Mode.......................................................................... 3-13Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13

    Resetting the Transceiver During Dynamic Reconfiguration............................................................. 3-14Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion

    Calibration is Required During Device Operation..............................................................3-14Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-15Transceiver Power-Down.........................................................................................................................3-16Document Revision History.....................................................................................................................3-16

    Transceiver Protocol Configurations in Cyclone V Devices..............................4-1PCI Express...................................................................................................................................................4-2

    PCIe Transceiver Datapath.............................................................................................................4-3PCIe Supported Features................................................................................................................ 4-4PCIe Supported Configurations and Placement Guidelines......................................................4-7

    Gigabit Ethernet......................................................................................................................................... 4-13Gigabit Ethernet Transceiver Datapath...................................................................................... 4-15

    XAUI............................................................................................................................................................4-19Transceiver Datapath in a XAUI Configuration....................................................................... 4-19XAUI Supported Features............................................................................................................ 4-21Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration........... 4-24

    Serial Digital Interface...............................................................................................................................4-26Configurations Supported in SDI Mode.............................................