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Transcript of Cyclone V Device Handbook - Intel Cyclone V Device Handbook Volume 2: Transceivers Subscribe Send...

  • Cyclone V Device Handbook Volume 2: Transceivers

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    CV-5V3 2018.10.24

    101 Innovation Drive San Jose, CA 95134 www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=CV-5V3 mailto:FPGAtechdocfeedback@intel.com?subject=Feedback%20on%20Cyclone%20V%20Device%20Handbook%20Volume%202:%20Transceivers%20(CV-5V3%202018.10.24)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Transceiver Architecture in Cyclone V Devices..................................................1-1 Architecture Overview................................................................................................................................ 1-2

    Transceiver Banks............................................................................................................................ 1-3 6.144 Gbps CPRI Support Capability in GT Devices..................................................................1-8 Transceiver Channel Architecture................................................................................................. 1-8

    PMA Architecture........................................................................................................................................1-9 Transmitter PMA Datapath..........................................................................................................1-10 Receiver PMA Datapath................................................................................................................1-16 Transmitter PLL............................................................................................................................. 1-21 Clock Divider..................................................................................................................................1-26 Calibration Block........................................................................................................................... 1-27

    PCS Architecture........................................................................................................................................1-29 Transmitter PCS Datapath............................................................................................................1-30 Receiver PCS Datapath................................................................................................................. 1-36

    Channel Bonding....................................................................................................................................... 1-55 PLL Sharing.................................................................................................................................................1-56 Document Revision History.....................................................................................................................1-56

    Transceiver Clocking in Cyclone V Devices....................................................... 2-1 Input Reference Clocking............................................................................................................................2-1

    Dedicated Reference Clock Pins.................................................................................................... 2-2 Fractional PLL (fPLL)......................................................................................................................2-4

    Internal Clocking......................................................................................................................................... 2-5 Transmitter Clock Network............................................................................................................ 2-6 Transmitter Clocking.....................................................................................................................2-10 Receiver Clocking.......................................................................................................................... 2-15

    FPGA Fabric–Transceiver Interface Clocking....................................................................................... 2-18 Transceiver Datapath Interface Clocking................................................................................... 2-21 Transmitter Datapath Interface Clocking...................................................................................2-21 Receiver Datapath Interface Clock.............................................................................................. 2-25

    Document Revision History.....................................................................................................................2-29

    Transceiver Reset Control in Cyclone V Devices................................................3-1 PHY IP Embedded Reset Controller......................................................................................................... 3-1

    Embedded Reset Controller Signals.............................................................................................. 3-1 Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

    Power-Up..................................................................................................................................... 3-3 Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device

    Operation.....................................................................................................................................3-4 User-Coded Reset Controller..................................................................................................................... 3-5

    User-Coded Reset Controller Signals............................................................................................3-6

    TOC-2 Cyclone V Device Handbook Volume 2: Transceivers

    Altera Corporation

  • Resetting the Transmitter with the User-Coded Reset Controller During Device Power- Up ................................................................................................................................................ 3-7

    Resetting the Transmitter with the User-Coded Reset Controller During Device Operation.....................................................................................................................................3-8

    Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration..............................................................................................................................3-9

    Resetting the Receiver with the User-Coded Reset Controller During Device Operation..3-10 Transceiver Reset Using Avalon Memory Map Registers.....................................................................3-11

    Transceiver Reset Control Signals Using Avalon Memory Map Registers.............................3-11 Clock Data Recovery in Manual Lock Mode......................................................................................... 3-12

    Control Settings for CDR Manual Lock Mode.......................................................................... 3-13 Resetting the Transceiver in CDR Manual Lock Mode............................................................ 3-13

    Resetting the Transceiver During Dynamic Reconfiguration..............................................................3-14 Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion

    Calibration is Required During Device Operation..............................................................3-14 Transceiver Blocks Affected by the Reset and Powerdown Signals.....................................................3-15 Transceiver Power-Down..........................................................................................................................3-16 Document Revision History.....................................................................................................................3-16

    Transceiver Protocol Configurations in Cyclone V Devices.............................. 4-1 PCI Express................................................................................................................................................... 4-2

    PCIe Transceiver Datapath............................................................................................................. 4-3 PCIe Supported Features.................................................................................................................4-4 PCIe Supported Configurations and Placement Guidelines...................................................... 4-7

    Gigabit Ethernet......................................................................................................................................... 4-13 Gigabit Ethernet Transceiver Datapath.......................................................................................4-15

    XAUI............................................................................................................................................................4-19 Transceiver Datapath in a XAUI Configuration........................................................................4-20 XAUI Supported Features.............................................................................................................4-21 Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration............ 4-24

    Serial Digital Interface...............................................................................................................................4-26 Configurations Supported in SDI Mode.................................