Cyclone V Device Handbook - Intel ... Cyclone V Device Handbook Volume 1: Device Interfaces and...

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Transcript of Cyclone V Device Handbook - Intel ... Cyclone V Device Handbook Volume 1: Device Interfaces and...

  • Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

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    CV-5V2 2020.07.24

    101 Innovation Drive San Jose, CA 95134 www.altera.com

    https://www.altera.com/servlets/subscriptions/alert?id=CV-5V2 mailto:FPGAtechdocfeedback@intel.com?subject=Feedback%20on%20Cyclone%20V%20Device%20Handbook%20Volume%201:%20Device%20Interfaces%20and%20Integration%20(CV-5V2%202020.07.24)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

  • Contents

    Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices......... 1-1 LAB ............................................................................................................................................................... 1-1

    MLAB ............................................................................................................................................... 1-2 Local and Direct Link Interconnects ............................................................................................1-3 LAB Control Signals........................................................................................................................ 1-4 ALM Resources ............................................................................................................................... 1-5 ALM Output .................................................................................................................................... 1-6

    ALM Operating Modes .............................................................................................................................. 1-8 Normal Mode ...................................................................................................................................1-8 Extended LUT Mode ...................................................................................................................... 1-8 Arithmetic Mode .............................................................................................................................1-8 Shared Arithmetic Mode ..............................................................................................................1-10

    Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Revision History............ 1-11

    Embedded Memory Blocks in Cyclone V Devices..............................................2-1 Types of Embedded Memory..................................................................................................................... 2-1

    Embedded Memory Capacity in Cyclone V Devices.................................................................. 2-1 Embedded Memory Design Guidelines for Cyclone V Devices............................................................2-2

    Guideline: Consider the Memory Block Selection...................................................................... 2-2 Guideline: Implement External Conflict Resolution...................................................................2-3 Guideline: Customize Read-During-Write Behavior.................................................................. 2-3 Guideline: Consider Power-Up State and Memory Initialization............................................. 2-7 Guideline: Control Clocking to Reduce Power Consumption...................................................2-7

    Embedded Memory Features..................................................................................................................... 2-7 Embedded Memory Configurations..............................................................................................2-9 Mixed-Width Port Configurations................................................................................................ 2-9

    Embedded Memory Modes...................................................................................................................... 2-10 Embedded Memory Clocking Modes..................................................................................................... 2-12

    Clocking Modes for Each Memory Mode.................................................................................. 2-12 Asynchronous Clears in Clocking Modes.................................................................................. 2-13 Output Read Data in Simultaneous Read/Write........................................................................2-13 Independent Clock Enables in Clocking Modes........................................................................2-13

    Parity Bit in Memory Blocks.....................................................................................................................2-14 Byte Enable in Embedded Memory Blocks............................................................................................ 2-14

    Byte Enable Controls in Memory Blocks.................................................................................... 2-14 Data Byte Output........................................................................................................................... 2-15 RAM Blocks Operations............................................................................................................... 2-15

    Memory Blocks Packed Mode Support...................................................................................................2-16 Memory Blocks Address Clock Enable Support.................................................................................... 2-16 Embedded Memory Blocks in Cyclone V Devices Revision History................................................. 2-18

    TOC-2 Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

    Altera Corporation

  • Variable Precision DSP Blocks in Cyclone V Devices........................................ 3-1 Features..........................................................................................................................................................3-1 Supported Operational Modes in Cyclone V Devices.............................................................................3-2 Resources.......................................................................................................................................................3-2 Design Considerations................................................................................................................................ 3-3

    Operational Modes.......................................................................................................................... 3-4 Internal Coefficient and Pre-Adder............................................................................................... 3-4 Accumulator..................................................................................................................................... 3-4 Chainout Adder................................................................................................................................3-4

    Block Architecture....................................................................................................................................... 3-4 Input Register Bank......................................................................................................................... 3-5 Pre-Adder..........................................................................................................................................3-7 Internal Coefficient.......................................................................................................................... 3-7 Multipliers......................................................................................................................................... 3-8 Adder................................................................................................................................................. 3-8 Accumulator and Chainout Adder................................................................................................ 3-8 Systolic Registers.............................................................................................................................. 3-9 Double Accumulation Register...................................................................................................... 3-9 Output Register Bank...................................................................................................................... 3-9

    Operational Mode Descriptions.............................................................................................................. 3-10 Independent Multiplier Mode......................................................................................................3-10 Independent Complex Multiplier Mode..................................................................................... 3-13 Multiplier Adder Sum Mode........................................................................................................ 3-15 18 x 18 Multiplication Summed with 36-Bit Input Mode.........................................................3-15 Systolic FIR Mode.......................................................................................................................... 3-16

    Variable Precision DSP Blocks in Cyclone V Devices Revision History............................................ 3-18

    Clock Networks and PLLs in Cyclone V Devices................................................ 4-1 Clock Networks............................................................................................................................................ 4-1

    Clock Resources in Cyclone V Devices...........................