Cyclone II Device Handbook - RS Components Altera Corporation v Cyclone II Device Handbook, Volume 1

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Transcript of Cyclone II Device Handbook - RS Components Altera Corporation v Cyclone II Device Handbook, Volume 1

  • 101 Innovation Drive San Jose, CA 95134 www.altera.com

    Cyclone II Device Handbook, Volume 1

    CII5V1-3.3

    http://www.altera.com

  • Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des- ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap- plication or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in- formation and before placing orders for products or services.

    ii Altera Corporation

  • Altera Corporation

    Contents

    Chapter Revision Dates ........................................................................... xi

    About This Handbook ............................................................................ xiii How to Contact Altera .......................................................................................................................... xiii Typographic Conventions .................................................................................................................... xiii

    Section I. Cyclone II Device Family Data Sheet Revision History .................................................................................................................................... 1–1

    Chapter 1. Introduction Introduction ............................................................................................................................................ 1–1

    Low-Cost Embedded Processing Solutions .................................................................................. 1–1 Low-Cost DSP Solutions ................................................................................................................. 1–1

    Features ................................................................................................................................................... 1–2 Referenced Documents ......................................................................................................................... 1–9 Document Revision History ................................................................................................................. 1–9

    Chapter 2. Cyclone II Architecture Functional Description .......................................................................................................................... 2–1 Logic Elements ....................................................................................................................................... 2–2

    LE Operating Modes ........................................................................................................................ 2–4 Logic Array Blocks ................................................................................................................................ 2–7

    LAB Interconnects ............................................................................................................................ 2–8 LAB Control Signals ......................................................................................................................... 2–8

    MultiTrack Interconnect ..................................................................................................................... 2–10 Row Interconnects .......................................................................................................................... 2–10 Column Interconnects .................................................................................................................... 2–12 Device Routing ............................................................................................................................... 2–15

    Global Clock Network & Phase-Locked Loops ............................................................................... 2–16 Dedicated Clock Pins ..................................................................................................................... 2–20 Dual-Purpose Clock Pins .............................................................................................................. 2–20 Global Clock Network ................................................................................................................... 2–21 Global Clock Network Distribution ............................................................................................ 2–23 PLLs .................................................................................................................................................. 2–25

    Embedded Memory ............................................................................................................................. 2–27 Memory Modes ............................................................................................................................... 2–30 Clock Modes .................................................................................................................................... 2–31 M4K Routing Interface .................................................................................................................. 2–31

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  • Contents

    Embedded Multipliers ........................................................................................................................ 2–32 Multiplier Modes ............................................................................................................................ 2–35 Embedded Multiplier Routing Interface ..................................................................................... 2–36

    I/O Structure & Features .................................................................................................................... 2–37 External Memory Interfacing ....................................................................................................... 2–44 Programmable Drive Strength ..................................................................................................... 2–49 Open-Drain Output ........................................................................................................................ 2–50 Slew Rate Control ........................................................................................................................... 2–51 Bus Hold .......................................................................................................................................... 2–51 Programmable Pull-Up Resistor .................................................................................................. 2–51 Advanced I/O Standard Support ................................................................................................ 2–52 High-Speed Differential Interfaces .............................................................................................. 2–53 Series On-Chip Termination ......................................................................................................... 2–55 I/O Banks ........................................................................................................................................ 2–57 MultiVolt I/O Interface ................................................................................................................. 2–60

    Chapter 3. Configuration & Testing IEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 3–1 Configuration ......................................................................................................................................... 3–5 Operating Modes ................................................................................................................................... 3–5 Configuration Schemes ......................................................................................................................... 3–6 Cyclone II Automated Single Event Upset Detection ...................................................................... 3–7

    Custom-Built Circuitry .................................................................................................................... 3–7 Software Interface ............................................................................................................................. 3–7

    Document Revision History ................................................................................................................. 3–8

    Chapter 4. Hot Socketing & Power-On Reset Introduction ............................................................................................................................................ 4–1 Cyclone II Hot-Socketing Specifications ............................................................................................ 4–1

    Devices Can Be Driven before P