Cyclone II Device Handbook - intel.com .101 Innovation Drive San Jose, CA 95134 Cyclone II Device

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Transcript of Cyclone II Device Handbook - intel.com .101 Innovation Drive San Jose, CA 95134 Cyclone II Device

101 Innovation DriveSan Jose, CA 95134www.altera.com

Cyclone II Device Handbook, Volume 1

CII5V1-3.3

http://www.altera.com

Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

ii Altera Corporation

Altera Corporation

Contents

Chapter Revision Dates ........................................................................... xi

About This Handbook ............................................................................ xiiiHow to Contact Altera .......................................................................................................................... xiiiTypographic Conventions .................................................................................................................... xiii

Section I. Cyclone II Device Family Data SheetRevision History .................................................................................................................................... 11

Chapter 1. IntroductionIntroduction ............................................................................................................................................ 11

Low-Cost Embedded Processing Solutions .................................................................................. 11Low-Cost DSP Solutions ................................................................................................................. 11

Features ................................................................................................................................................... 12Referenced Documents ......................................................................................................................... 19Document Revision History ................................................................................................................. 19

Chapter 2. Cyclone II ArchitectureFunctional Description .......................................................................................................................... 21Logic Elements ....................................................................................................................................... 22

LE Operating Modes ........................................................................................................................ 24Logic Array Blocks ................................................................................................................................ 27

LAB Interconnects ............................................................................................................................ 28LAB Control Signals ......................................................................................................................... 28

MultiTrack Interconnect ..................................................................................................................... 210Row Interconnects .......................................................................................................................... 210Column Interconnects .................................................................................................................... 212Device Routing ............................................................................................................................... 215

Global Clock Network & Phase-Locked Loops ............................................................................... 216Dedicated Clock Pins ..................................................................................................................... 220Dual-Purpose Clock Pins .............................................................................................................. 220Global Clock Network ................................................................................................................... 221Global Clock Network Distribution ............................................................................................ 223PLLs .................................................................................................................................................. 225

Embedded Memory ............................................................................................................................. 227Memory Modes ............................................................................................................................... 230Clock Modes .................................................................................................................................... 231M4K Routing Interface .................................................................................................................. 231

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Contents

Embedded Multipliers ........................................................................................................................ 232Multiplier Modes ............................................................................................................................ 235Embedded Multiplier Routing Interface ..................................................................................... 236

I/O Structure & Features .................................................................................................................... 237External Memory Interfacing ....................................................................................................... 244Programmable Drive Strength ..................................................................................................... 249Open-Drain Output ........................................................................................................................ 250Slew Rate Control ........................................................................................................................... 251Bus Hold .......................................................................................................................................... 251Programmable Pull-Up Resistor .................................................................................................. 251Advanced I/O Standard Support ................................................................................................ 252High-Speed Differential Interfaces .............................................................................................. 253Series On-Chip Termination ......................................................................................................... 255I/O Banks ........................................................................................................................................ 257MultiVolt I/O Interface ................................................................................................................. 260

Chapter 3. Configuration & TestingIEEE Std. 1149.1 (JTAG) Boundary Scan Support ............................................................................. 31Configuration ......................................................................................................................................... 35Operating Modes ................................................................................................................................... 35Configuration Schemes ......................................................................................................................... 36Cyclone II Automated Single Event Upset Detection ...................................................................... 37

Custom-Built Circuitry .................................................................................................................... 37Software Interface ............................................................................................................................. 37

Document Revision History ................................................................................................................. 38

Chapter 4. Hot Socketing & Power-On ResetIntroduction ............................................................................................................................................ 41Cyclone II Hot-Socketing Specifications ............................................................................................ 41

Devices Can Be Driven before Power-Up ..................................................................................... 42I/O Pins Remain Tri-Stated during Power-Up ............................................................................ 42

Hot-Socketing Feature Implementation in Cyc