Cyclic ADC based on a novel concept of Zero-Crossing … · Zero-Crossing Detection - Master Thesis...

Swiss Federal Institute of Technology, Lausanne, EPFL

Electrical and Electronics Engineering Section, SEL

Microelectronic Systems Laboratory, LSM

Cyclic ADC based on novel concept of Zero-Crossing Detection

- Master Thesis Report–

Student : Tamara Saranovac Supervisor : Nikola Katić

Professor : Alexandre Schmid

January 2012

Lausanne

Cyclic ADC based on a novel concept of Zero-Crossing Detection

ii

Table of Contents

Index of Figures ................................................................................................................... iv

Index of Tables .......................................................................................................................v

Abbreviations ....................................................................................................................... vi

Abstract ..................................................................................................................................1

1. Introduction ....................................................................................................................2

1.1 Motivation ....................................................................................................................2

1.2 Organization .................................................................................................................4

2. Comparator Based Switched Capacitor Circuits ..............................................................5

2.1 Introduction ..................................................................................................................5

2.2 CBSC Basic Principle of Operation...............................................................................5

2.3 CBSC Detailed Operation .............................................................................................7

2.3 Limitations and Advantages ........................................................................................ 10

2.4 State-of-Art Experimental Results ............................................................................... 11

3. Bootstrapped Switch ..................................................................................................... 13

3.1 Introduction ................................................................................................................ 13

3.2 Bootstrapped Switch-Principle .................................................................................... 13

3.3 Simulations ................................................................................................................. 15

3.3.1 Functional Simulation .......................................................................................... 15

3.3.2 Signal Spectrum Estimation ................................................................................. 18

4. Zero-Crossing Detector ................................................................................................. 22

4.1 Introduction ................................................................................................................ 22

4.2 Zero Crossing Detector-Principle of Operation ........................................................... 22

4.3 Simulations ................................................................................................................. 24

4.4 ZCD Improvement for 2 Phase CBSC ......................................................................... 27

4.4.1 Functional Simulation for a New ZCD ................................................................. 28

5. CBSC Gain Stage Implementation ................................................................................ 30

5.1 Introduction ................................................................................................................ 30

5.2 CBSC-Complete Schematic ........................................................................................ 30

5.3 Functional Simulation ................................................................................................. 30

5.4 Current Sources .......................................................................................................... 32

5.5 Performance Simulation .............................................................................................. 34

6. 1.5 Bit-per-Stage Architecture ...................................................................................... 35

6.1 Introduction ................................................................................................................ 35

6.2 Basic Concept ............................................................................................................. 35

6.2 Implementation of 1.5 Bit-per-Stage Algorithm in CBSC............................................ 37


iii

6.3 Functional Simulation ................................................................................................. 37

7. Cyclic ADC Implementation ......................................................................................... 39

7.1 Introduction ................................................................................................................ 39

7.2 Cyclic ADC CBSC Implementation ............................................................................ 40

7.3 Simulations ................................................................................................................. 41

7.3.1 8 Bits Implementation .......................................................................................... 41

8. Future Work ................................................................................................................. 44

8.1 Introduction ................................................................................................................ 44

8.2 Improvements Step-by-Step ........................................................................................ 44

8.2.1 Bootstrapped Switch ............................................................................................ 44

8.2.2 Zero-Crossing Detector ........................................................................................ 44

8.2.3 Current Sources .................................................................................................... 45

8.2.4 Residue Plots ....................................................................................................... 45

9. Conclusion .................................................................................................................... 46

Acknowledgments ................................................................................................................ 47

References ............................................................................................................................ 48

Appendix A .......................................................................................................................... 49

A.1 SNR and SNDR Calculation ...................................................................................... 49

A.2 ZCD Offset Calculation ............................................................................................. 50

A.3 DNL and INL Calculation ........................................................................................... 51

Appendix B .......................................................................................................................... 52

B.1 Data Acquiring for ZCD Offset Calculation ............................................................... 52

B.2 Output Code Acquiring for 8 Bits Cyclic ADC ........................................................... 53

Appendix C .......................................................................................................................... 55

C.1 Chapter 2, Equation (2) .............................................................................................. 55

C.2 Chapter 3, Equation (5) and (6 .................................................................................... 55

Appendix D .......................................................................................................................... 56

D.1 Logic for Generation of Control Signals E1 and E2.................................................... 56

D.2 Logic for Generation of Phase Signals for Switches, 2(D1, D0) ................................ 57


iv

Index of Figures

Figure 1.1-Architecture of Pipeline ADC. ...............................................................................2 Figure 1.2-Architecture of Cyclic ADC. .................................................................................3 Figure 1.3-SC Integrator Stage. ..............................................................................................3 Figure 2.1-Bottom Plate Input Sampling. ................................................................................5 Figure 2.2-Op-amp Based SC Gain Stage. ..............................................................................6 Figure 2.3-Comparator Based SC Gain Stage. ........................................................................7 Figure 2.4-Timing Diagram. ...................................................................................................7 Figure 2.5-Preset Phase. .........................................................................................................8 Figure 2.6-Coarse Charge Transfer Phase. ..............................................................................9 Figure 2.7-Fine Charge Transfer Phase. ................................................................................ 10 Figure 3.1-Basic Principle of Bootstrapping. ........................................................................ 13 Figure 3.2-Transistor Level Implementation of Bootstrapped Switch. ................................... 14 Figure 3.3-Input and Output Voltage. ................................................................................... 17 Figure 3.4-Input and Gate-Source Voltage. ........................................................................... 17 Figure 3.5-Input Voltage and Resistance. .............................................................................. 18 Figure 3.6-Realistic Testbench.............................................................................................. 20 Figure 3.7-Input Voltage and Capacitance Voltage for Testbench in Figure 3.6. ................... 20 Figure 3.8-Spectrum of Sampled Signal for Case a) and b), M=1024. ................................... 21 Figure 4.1-Functionality of Zero-Crossing Detector. ............................................................. 22 Figure 4.2- Implementation of Zero-Crossing Detector [6].................................................... 23 Figure 4.3-Timing Diagram of ZCD Based SC Circuits [5]. .................................................. 23 Figure 4.4-Functional Simulation of ZCD. ............................................................................ 24 Figure 4.5-ZCD Delay Simulation. ....................................................................................... 24 Figure 4.6-Offset Simulation of the Zero-Crossing Detector. ................................................ 25 Figure 4.7-Cumulative Histogram and Normal Probability Plot. ........................................... 26 Figure 5.1-Complete Schematic of CBSC Gain Stage. .......................................................... 30 Figure 5.2-Functional Simulation of CBSC Gain Stage. ........................................................ 31 Figure 5.3-Zoomed in One Charge Transfer of CBSC Gain Stage. ........................................ 31 Figure 5.4-Single Transistor Current Sources........................................................................ 32 Figure 5.5-Cascoded Current Sources. .................................................................................. 32 Figure 5.6-Spectrum of Sampled Signal for Cases a) and b), M=1024. ................................. 34 Figure 6.1-Residue Plot. ....................................................................................................... 35 Figure 6.2-Residue Plot for 1.5 Bit-per-Stage. ...................................................................... 36 Figure 6.3-Implemenation of a CBSC Gain Stage with 1.5 Bit-per-Stage Scheme................. 37 Figure 6.4- 1.5-Bit Gain Stage Functional Simulation. .......................................................... 38 Figure 6.5-Residue Plot for Single Ended Signals. ................................................................ 38 Figure 7.1-Architecture of Cyclic ADC with 1.5 Bit-per-Cycle Algorithm. ........................... 39 Figure 7.2-Complete Schematic of CBSC Cyclic ADC with 1.5 Bit-per-Cycle. .................... 40 Figure 7.3-Spectrum of Quantized Signal, M=1024. ............................................................. 41 Figure 7.4-ADC Transfer Curve. .......................................................................................... 42 Figure 7.5-Differential and Integral Non-Linearities. ............................................................ 42 Figure 7.6-SNR and SNDR versus Input Signal Amplitude .................................................. 43


v

Index of Tables Table 2.1-ADC Performance Summary [3]. .......................................................................... 11 Table 2.2-ADC Performance Summary [6]. .......................................................................... 12 Table 3.1-Sizing of Bootstrapped Switch. ............................................................................. 16 Table 3.2-Results of Performance Simulation. ...................................................................... 21 Table 5.1-Results of Performance Simulations. ..................................................................... 34 Table 7.1-8 Bit ADC Performance Summary ........................................................................ 41


vi

Abbreviations

ADC Analog to Digital Converter

CBSC Comparator Based Switched Capacitor

CIS CMOS Image Sensors

DAC Digital to Analog Converter

DFF D Flip-Flop

DNL Differential Non-Linearities

DTDL Dynamic Threshold Detecting Latch

ENOB Effective Number Of Bits

FFT Fast Fourier Transform

FOM Figure Of Merit

INL Integral Non-Linearities

LSB Least Significant Bit

MSB Most Significant Bit

Op-amp Operational amplifier

SC Switched Capacitor

SNR Signal to Noise Ratio

SNDR Signal to Noise and Distortion Ratio

ZCD Zero-Crossing Detector


1

Abstract

When interfacing digital systems with the real world input and output signals usually

have analog nature, meaning that they are continuous in both time and amplitude. In order to

link digital processing systems and analog signals, special circuits are used: analog-to-digital

converters (ADCs) and digital-to-analog converters (DACs). The basic function of ADC is

time and amplitude discretization.

Different categorizing of ADCs can be made. Based on the timing of the conversion,

division can be made to parallel converters, sequential converters and linear search

converters. For each of this divisions, additional subdivisions can be made, for example

sequential converters can be divided based on architecture to pipeline, cyclic, multi-step,

successive approximation converters etc. Each of these architectures has its potential

advantages and drawbacks depending on the intended purpose.

ADC usage always requires a certain trade-off between silicon area, speed and

accuracy, depending on desired purpose and a field of applications. For commercial CMOS

camera chips, where converters are usually implemented per each column of pixels, area and

power consumption are of most interest. Cyclic ADC was proposed as a solution which

requires small area and power, trading it however, for a relatively low operating frequency.

Crucial element of cyclic ADC circuit is analog sample- or track-and-hold circuit,

which performs sampling operation of analog input signal at a sampling moment. Depending

on the architecture of ADC, sampling phase is followed with more analog circuits which

implement addition, multiplication etc. In most practical cases, the best solution for

implementation of those analog circuits, binding them all together, is by using switched

capacitor circuits. Switched capacitor circuits consist of switches, capacitors and a gain

stage obtained through capacitor ratios. In CMOS technology switches and capacitors are

easy to implement, but the gain stage represents a problem when moving to deep submicron

technologies. In the latest technology nodes, one of the solutions for switched capacitor

circuit design is based on the novel concept of zero-crossing detection. This novel concept

simplifies the design of the gain stage, resulting in higher performance of SC circuits

especially in terms of power and operating frequency, making them more suitable for usage in

new technologies.

In this master thesis, firstly the principle of switched capacitor circuit design based on

zero-crossing detection has been presented. As a next step, integral part of the circuit, the

bootstrapped switch has been designed, with an emphasis on its performance. Sizing of

switches and capacitors was done taking care that the final switched capacitor circuit should

be implemented in an 8 bits ADC. The next step was designing zero-crossing detector and

implementing it in the gain stage of switched capacitor circuits, followed by detailed

simulations of the whole multiplying switched capacitor circuit. As a final step, 8 bits cyclic

ADC has been implemented in standard 0.18um CMOS technology that operates at 125kHz,

achieves 7.5 effective bits of accuracy and consumes 0.9mW of power.


2

1. Introduction

1.1 Motivation

The need for image acquisition is present in many fields of science and research, as

well as in industry and everyday life. It can be found in many applications such as medical or

space research, automation and robots, automotive industry, surveillance, but also in many of

today’s commercial devices: phones, web-cams, digital cameras, etc. The first stage of any of

these systems is the image acquisition stage. After the image has been obtained, various

methods of processing can be applied depending on needs and the application. However, if

the image was not acquired in a satisfactory level, intended purpose of the image cannot be

fulfilled even with aid of image enhancement techniques. Each next generation of image

processing devices requires increased performance for CMOS image sensors (CIS) in terms

of frame rate, dynamic range and pixel resolution.

Image data always needs to be digitalized by using an analog-to-digital Converter

(ADC), with the image dynamic range and frame rate being limited mainly by performance

of the ADC. Each of ADC topology has its benefits and drawbacks which are unique for that

specific architecture. For the required performances of the image sensor, choosing

appropriate ADC is the most important task, since ADC very often represents a crucial

performance bottleneck.

The pipeline ADC is an N-step converter, with N stages connected in series for N bit

resolution, and one bit being converted per stage [1]. Pipeline ADC has smaller area than for

example flash ADC, and it is able to achieve high resolution at a relatively high speed.

However, pipeline ADC has a disadvantage that even a slightest error in one stage propagates

to the following stages. A block diagram of pipeline ADC is shown in figure 1.1.

T&H +-

VIN

DN-1

VREF/2

+ -

+ T&H +-

DN-2

VREF/2

+ -

+ *2 T&H

D0

VREF/2

+ -

... *2

Figure 1.1-Architecture of Pipeline ADC.

Cyclic ADC has small area comparing to pipeline ADC, but it takes N cycles for one

conversion, and in that view it has lower speed comparing to pipeline or SAR ADC [1]. A

block diagram of cyclic ADC is shown in figure 1.2.


3

T&H +

-

...

VIN VOUT

Di

clk

LSB MSB

VREF/2

SHIFT

REGISTER

+ -

+ *2

Figure 1.2-Architecture of Cyclic ADC.

It can be seen from figures 1.1 and 1.2 that track and hold circuit has an extensive use

in data converter applications as a sampling gate [2]. Operations like addition and

multiplication are also required in data converters, and one way to combine sample-and-hold

with these operations is by using Switched Capacitor (SC) circuits [2]. SC circuits are very

commonly used in integrated circuits because their “output” depends only on the ratio

between capacitances rather than the value of the capacitance itself. Precise value

capacitances in an integrated circuit are not easy to implement in practice.

Traditional op-amp based switched capacitor integrator stage is shown in figure 1.3.

After each clock cycle a charge sample C2⋅Vin is transferred to C1, and the value of sampled

voltage in ideal case VOUT= C2⋅Vin/C1 depends on the ratio C2/C1.

VIN1

12

2-

+

C2

C1

VOUT

Figure 1.3-SC Integrator Stage.

A crucial element of traditional SC circuits is the operational amplifier (op-amp).

Therefore, conventional switched capacitor circuit design becomes very difficult as designs

move to scaled CMOS technologies. Op-amp design in that case represents the most difficult

task of CMOS switched capacitor design.

Lower supply voltages and lower output resistance in scaled devices, result in lower

dynamic range and lower gain, which leads to difficulty of realizing precise charge transfer

[3]. The most significant portion of error comes from inaccurate charge transfer.


4

The usual solutions are to increase the circuit capacitances to maintain the same

dynamic range which leads to an increase in power consumption in order to maintain high

speed. Cascoding or cascading of the amplifier stages is an option for keeping the same

amplifier gain. However, cascoding further decreases dynamic range, and cascading of

several stages brings up an issue of stabilizing such amplifier.

Another approach to deal with devices scaling and voltage reduction is an alternative

architecture called Comparator Based Switch Capacitor circuits (CBSC), which does not

require an op-amp in the signal path. This architecture uses a combination of a comparator

and a current source in order to perform the same charge transfer as an op-amp based

implementation [4]. CBSC circuits can be used in most of the applications which use

traditional op-amp SC circuits, as a very efficient alternative.

1.2 Organization

This report is organized into 9 chapters.

Comparator based switched capacitor circuits are explained in Chapter 2, with their

comparison to standard SC circuits. In addition, recent works in using CBSC for state-of-the-

art pipelined ADCs are presented.

The bootstrapped switch [5], as the switch that will be used in CBSC design, is

introduced in Chapter 3. Detailed simulations are also presented in this chapter, with

emphasis on signal-to-noise (SNR) and signal-to-noise-distortion ratio (SNDR).

The Zero-Crossing Detector (ZCD) [6] which replaces the comparator in CBSC is

introduced in Chapter 4. In this chapter the basic schematic with sizing and simulations is

given, followed by the improvement for usage in CBSC.

Comparator based switch capacitor gain stage is presented in Chapter 5. Detailed

simulations with results for both functionality and performance are also given in this chapter.

The 1.5 bit-per-stage CBSC gain stage is given in Chapter 6. The concept of adding

redundancy bits is explained, and the obtained simulation results are presented.

The cyclic 1.5 bit-per-cycle ADC implementation is given in Chapter 7, with principle

of operation and simulation results, including functionality and overall performance.

Future work and improvements are given in Chapter 8, while conclusion and the

summary of the overall work is given in Chapter 9.


5

2. Comparator Based Switched Capacitor Circuits

2.1 Introduction

The basic operation of CBSC circuits [3] will be introduced. After comparing the

basics with standard op-amp based switched capacitor circuits, a detailed and improved

transfer phase is described. Accuracy and limitations are introduced, as well as potential

advantages. Some new concepts from [3] and [6] are also presented here with obtained

results.

2.2 CBSC Basic Principle of Operation

A simple switched capacitor gain stage will be used to explain the functionality, and

compare op-amp based with comparator-based SC circuits. Their operation is very similar,

but the main difference is that op-amp forces virtual ground condition on summing node

while comparator detects the virtual ground condition, stops charge transfer, and triggers

sampling. Both circuits still have the same phases of operation sampling phase and charge

transfer phase [3].

Assume that both circuits use the same input sampling circuit given in figure 2.1.

During the sampling phase 1, input voltage is sampled onto both capacitors C1 and C2.

Bottom plate sampling, with opening the switch 1A, is used to minimize signal dependent

charge injection.

VIN

C1

VCM

C2

1

1

1A

1

1A

Figure 2.1-Bottom Plate Input Sampling.

For charge transfer phase in op-amp based SC circuits, capacitors are reconfigured in

following manner showed in figure 2.2.


6

C2

C1

CL

VCM

VCM

VCM

+

-VX

+ -VO

VO

VX0

VCM

VX

t

t

VO[n]

Figure 2.2-Op-amp Based SC Gain Stage.

The op-amp forces the virtual ground condition VX=VCM, which transfers all the

sampled charge from C2 to C1. During the transfer phase, both the output node voltage VO and

summing node voltage VX settle exponentially to their steady states, as shown in figure 2.2.

After certain numbers of time-constants, the output voltage is sampled on load capacitance

CL. The relationship between output and input sample in time instances n and n-1 is:

. (1)

During the charge transfer phase, the accuracy of output voltage is directly related to

accuracy of virtual ground condition. The op-amp forces virtual ground condition in

continuous time manner, but for the SC circuit accurate virtual ground condition is only

needed at the sampling instant. Therefore, it is possible to detect virtual ground condition at a

single point in time using a comparator, which should be more efficient than forcing it with an

op-amp [3].

For charge transfer phase in comparator based SC circuits, capacitors are reconfigured

like shown in figure 2.3.


7

C2

C1

CL

VCM

VCM

VCM

+

-

VX+ -

VO

VO

VX0

VCM

VX

t

t

VO[n]IX

Figure 2.3-Comparator Based SC Gain Stage.

The op-amp is replaced with a comparator and a current source. Insuring that VX

always starts bellow VCM, the current source IX turns on in the beginning of charge transfer,

charges up the capacitor network consisting of C1,C2 and CL which creates ramp waveforms

VO and VX shown in figure 2.3. The voltages continue to ramp until the virtual ground

condition is detected (VX= VCM) which disables the current source IX. In this way, the same

voltage is sampled on all capacitances as in the op-amp based case. All the charge from C2 is

transferred to C1, and the same output voltage is sampled on CL as in the op-amp based case.

2.3 CBSC Detailed Operation

To achieve high accuracy and linearity, the charge transfer phase has been divided into

three sub-phases: preset phase (P), coarse charge transfer phase (E1) and fine charge transfer

phase (E2) [4][7]. For higher accuracy charge transfer phase could be divided into more than

three phases, but that creates limitation in circuit speed. Timing diagram for these phases is

given in figure 2.4. The time spent on phases E1 and E2 is signal dependent because of self-

timed nature of comparator based circuit.

1 2

P E1 E2

Figure 2.4-Timing Diagram.

To ensure that voltage VX always starts below VCM, a brief preset phase P is used.

Preset phase is shown in figure 2.5.


8

C2

C1

CL

VCM

VCM

+

-

VX+ -

VO

VO

VX0

-VCM

VX

VO[n]

P

t

t

2

P

E1

E2

VCM

VCM

Figure 2.5-Preset Phase.

After the sampling phase 1, VX=VCM. During the preset phase the output node is

connected to the lowest system voltage, which ensures that VX starts below VCM, over a range

of input voltages. The preset value for the summing node [8], VX0 is:

. (2)

Using the constraint that the voltage VX0 should be less then VCM and greater than zero, valid

range for input signal is given with equation (3), assuming gain of two (C1=C2). This range is

also the range required to keep the output voltage between supply rails, assuming VCM is

halfway between supply rails:

. (3)

The first charge transfer phase is the coarse transfer phase E1. This phase is used to get

fast and rough estimate of output voltage and virtual ground condition. The current source I1

turns on in the beginning of charge transfer, charges up the capacitor network consisting of

C1, C2 and CL which creates ramp waveforms VO and VX shown in figure 2.6. The voltages

continue to ramp until the virtual ground condition is detected (VX=VCM) which disables the

current source I1. Finite delay of the comparator results in an overshoot of the correct value.

When the comparator makes its decision, the current source I1 is turned off. Charge transfer

phase E1 is shown in figure 2.6.


9

VO

VX0

-VCM

VX

2

P

E1

E2C2

C1

CL

VCM

VCM

+

-

VX+

VO

I1

E1 -

VCM

VCM

overshoot

overshoot

Figure 2.6-Coarse Charge Transfer Phase.

The second transfer phase, fine transfer phase E2 is used to obtain more accurate value

of output voltage and virtual ground condition, to correct overshoot from the coarse charge

transfer phase. For that reason current I2 is much less then current I1, and the opposite sign.

The current source I2 turns on in the beginning of this charge transfer, discharges the capacitor

network consisting of C1, C2 and CL which creates ramp waveforms VO and VX shown in

figure 2.7. The voltages continue to ramp until the virtual ground condition is detected for the

second time which disables the current source I2. Finite delay of the comparator results in an

undershoot of the correct value, but this error is much smaller then overshoot from transfer

phase E1. When the comparator makes its second decision, the current source I2 is turned off.

The fine transfer phase is given in figure 2.7.


10

VO

VX0

-VCM

VX

2

P

E1

E2C2

C1

CL

VCM

VCM

+

-

VX+

VO

I2

E2

-

VCM

VCM

Figure 2.7-Fine Charge Transfer Phase.

For good FOM, time spent on coarse charge transfer phase should be much smaller

than time spent on fine charge transfer phase, TE1>>TE2 and TE1+TE2+PT/2. It can be seen

that there are speed and linearity trade-offs. For higher precision at moderate speeds dual

phase CBSC is more suited while single phase is better suited for high speed although with a

price to pay at lower FOM

The time needed to finish the whole charge transfer is signal dependent. The time to

complete phase E1 depends of the value VX0 which depends from input signal (equation (2)).

For correct charge transfer, it has to be ensured that for any value of the input signal, there

will be enough time allocated for both charge transfer phases.

2.3 Limitations and Advantages

CBSC circuits do not have the output op-amp, therefore they can only drive switched-

capacitor loads. This limitation is not as severe as it may seem in the first look, because if a

resistive load should be driven, only adding of an output buffer is necessary.

In addition, CBSC cannot drive both sides of the sampling capacitor at the same tame

simultaneously, which makes them incompatible with conventional closed-loop offset

cancelation. But the comparator is still free during the sampling phase, and other techniques

should be possible to perform offset cancelation if necessary.

There are two mechanisms which create offset and nonlinearity in CBSC, output

voltage overshoot due to finite comparator delay and voltage drop across switches. Constant

portion of the error causes offset while signal dependent causes nonlinearity. Variation in

current source charge-current due to finite current source output resistance creates ramp rate

variations.


11

The output voltage nonlinearity is mostly due to overshoot variations which is a

consequence of ramp rate change. However, designing a constant current source in scaled

technologies should be easier than designing an op-amp.

On the other hand, CBSC circuits have a potential for significant power reduction

compared to op-amp designs. Since high amplifier gain is no longer a requirement, stability

issues are removed from design. With different design constraints for comparator and current

sources, comparing to op-amp, the CBSC are more applicable for scaled technologies.

Moreover, CBSC circuits are compatible with most known architectures which use op-amp

based design.

2.4 State-of-Art Experimental Results

The CBSC design applies not only to the gain stage described above, but to a number

of circuits, including ADCs, DACs, filters, integrators etc. As a proof of concept in this

section some experimental results will be given.

In [3] the CBSC method was applied to 1.5 bit-per-stage 10 bits pipeline ADC. The

prototype was designed as a single ended circuit in order to ease the implementation of CBSC

technique. Table 2.1 summarizes the performance of this prototype ADC.

In [6] the CBSC method was applied to differential 12 bits pipeline ADC, but it was a

single-phase charge transfer operation, more suitable for high speed. Table 2.2 summarizes

the performance of this prototype ADC.

Table 2.1-ADC Performance Summary [3].

fS 7.9MHz

Supply voltage 1V

DNL +0.33/-0.28 LSB

INL +1.59/-1.13 LSB

SFDR 62dB

SNDR 52dB

SNR 53dB

ENOB 8.6 b

Power 2.5mW

FOM=Power/(2⋅fin⋅2ENOB

) 0.8pJ/step


12

Table 2.2-ADC Performance Summary [6].

fS 50MHz

Supply voltage 2V

DNL +0.5 / -0.5 LSB

INL +3/-3 LSB

SFDR 68dB

SNDR 62dB

ENOB 10 b

Power 4.5mW


) 88fJ/step


13

3. Bootstrapped Switch

3.1 Introduction

In SC circuits capacitors and switches are the most important building blocks. The

switch has to provide fast and accurate charging of the sampling capacitor. An ideal switch

has zero ON resistance and infinite OFF resistance. A simple MOSFET can be used as a

switch with its source and drain as switch terminals, and its gate to control the conductivity.

The drawback of such implementation is that the on-resistance depends on the voltage

potential of terminals relative to channel potential. The simplified equation for on-resistance

in linear region is:

(4)

where VGS is the gate-source voltage, VTH is threshold voltage, COX the oxide capacitance and

W and L the width and length of transistor.

Another problem comes from scaling of technology because voltages and currents are

also being scaled, besides devices dimensions. Reducing the supply voltage for example,

increases drastically switch resistance. Also, charge injection of a simple switch is signal

dependent, which creates problems with scaled capacitors and introduces additional non-

linearities. With reducing supply voltages, reliable linear conduction is one more problem

when looking at the rail-to-rail operations. Threshold voltage does not scale at a same ratio as

supply voltage, which creates conduction gap; actually, the switch is not conducting in a large

part of input voltage range. One approach introduced to allow low voltage operation is

bootstrapping technique [2], which will be explained in this section.

3.2 Bootstrapped Switch-Principle

Bootstrapped switch is a circuit technique to surpass poor conduction and varying ON

resistance. Figure 3.1 shows the general idea of bootstrapping.

VIN

RIN

VDD

C

Chold

VIN

RIN

C

Chold

CHARGE BOOTSTRAP

Figure 3.1-Basic Principle of Bootstrapping.

Bootstrapped switches are realized with a single pass transistors, and additional

devices which provide constant gate-source voltage during ON state.


14

During the OFF state, the gate of the pass transistor is connected to ground and

transistor is cut off. The main difference comes in ON state, where the gate-source voltage is

kept constant. This voltage is obtained during the OFF state using pre-charged capacitor.

Therefore, charge injection of bootstrapped switch is much less signal dependent than for a

simple MOSFET.

The transistor level implementation is shown in figure 3.2 [5]. The switching

operation is controlled with external clock non-overlapping signal shown also in figure 3.2.

VDDVSS

VSS

VIN VOUT

A B

G

E

MN3

MP4MP7

MN1MN6S

MN6

MP2

MNT5 MN5

S D

2nVDD

1n

2n 2p

2n

2p

1n

Coffset

- +

MNSW

Figure 3.2-Transistor Level Implementation of Bootstrapped Switch.

Coffset is first charged to VDD, in phase f2n/f2p. Transistors MN3, MP7, MN5, MNT5

and MP4 are conducting, which sets negative plate of Coffset to VSS (through MN3) and

positive plate to VDD (through MP4). Transistor MP7 should be faster than transistor MN3,

so that when the bootstrap switch opens, the voltage in node E goes to VDD through MP7 and

not to VSS through MN3 and MN6. Transistors MN5, MNT5 should be large enough so that

the transistor gate voltage quickly goes to VSS in case of turning off the switch. In phase f1n

transistors MN1, MNSW, MN6S, MN6 and MP2 are conducting.

The gate voltage VG of bootstrapped switch MNSW at the end of f1n is:

(5)

and the value of Coffset voltage Voffset is:

. (6)

The capacitance Coffset must be large enough to supply enough charge to gate MNSW

when it is conducting. A significant offset reduction across Coffset due to capacitance division

might drive node B below VDD thus causing latch-up. The capacitance Coffset has to be

chosen to be at least 10⋅CG.


15

3.3 Simulations

3.3.1 Functional Simulation

3.3.1.1 Sizing Limitations

When sizing the bootstrapped switch, a many different factors should be taken into

account. Sizes of transistors in a switch cannot be calculated independently; instead one has to

take care of the load capacitance and desired sampling frequency.

The first issue that needs to be addressed is the thermal noise sampled on load

capacitance, known as kT/C noise. For example, if the final implementation of ADC requires

an 8 bits resolution, corresponding SNR level is 50dB (or 316). With maximum input voltage

peak-to-peak of 600mV, which corresponds to rms voltage of 0.6/2 V=213mV, the kT/C

noise must be lower than 0.673mVrms. This determines the minimum load capacitance value

of CL=9fF for this example.

The second issue refers to already mentioned charge injection. This effect comes

mainly from the generation and dissolution of charge from the conductive channel sitting

under transistor gate when transistor is in ON state. In addition parasitic capacitive coupling

should be taken into account. These two sources of error are such that if one of the switch

terminals is connected to a capacitance load, one fraction of the channel charge remains

trapped on that capacitance thus changing its voltage.

Channel of a MOS transistor working in triode region contains the following amount

of charge:

(7)

where Leff is the effective channel length Leff=L-2⋅xov with xov being the extent of source and

drain overlap. In addition to channel charge there is the charge in overlap capacitance:

. (8)

A fraction of the total charge Qch will affect one terminal of the switch and the rest

will influence the other. The splitting will depend on the speed of gate voltage variation. For

quick switching almost equal splitting between source and drain results. The voltage swing at

the gate produces an injection of charge in source and drain terminals because of the parasitic

coupling of Cgs,ov and Cgd,ov where Cgs,ov is the gate-source overlap capacitance and Cgd,ov is

gate-drain overlap capacitance. The fraction of this charge remains in the load capacitance

and its value depends from CL [9]. In literature this charge is usually referred to as clock

feedthrough.

Voltage error Uinj on load capacitance CL depends on the fraction of the charge that is

injected into the corresponding switch terminal Qinj and the value of load capacitance itself:

. (9)


16

For a given charge injection Qinj, voltage change is lower for higher capacitance value.

However, a large capacitance value will require large IC area and higher power budget, so it

needs to be chosen carefully.

In this project, the bootstrap switch was designed using 180nm UMC standard CMOS

technology. Sizes of transistors were chosen accordingly, depending on the load, and taking

into account on-resistance RON [5], as well as charge injection and clock feedthrough.

Simulation was used to determine the value of CG8fF, and the value of Coffset407fF

according to equation 3.3. The value for the load capacitance was chosen to be large enough

CL=4pF, to minimize the effect of charge injection, since as it was shown in performance

simulations, this effect was limiting final SNR and SNDR. For this value of capacitance and

input signal range of 600mV, kT/C noise is not a dominant noise in the circuit. Simulation

was used to determine values of overlap capacitances, being approximately Cgov0.5fF, thus

clock feedthrough did not represent a problem and was negligible compared to charge

injection.

Table 3.1 summarizes the final result of device sizing within the bootstrapped switch:

Table 3.1-Sizing of Bootstrapped Switch.

Transistor Size

MNSW 1.5um/0.18um

MNT5/MN5 2um/0.25um

MP2 1um/0.18um

MP4 1.05um/0.18um

MP7 1.6um/0.18um

MN6/MNS6 0.25um/0.18um

MN1 0.6um/0.18um

MN3 0.5um/0.35um

Coffset 407.1732fF

3.3.1.2 Simulation Results

Bootstrapped switch output for sine wave input at fin=94.7265625kHz, and amplitude

of 0.9V in a simple track-and-hold configuration is given in figure 3.3. Sampling frequency

was set to 1MHz. Voltage between the gate and the source in the same case is given in figure

3.4. It can be seen from figure 3.3 that for input peak-to-peak change of 1.8V, voltage gate-

source peak-to-peak is 20mV.


17

Figure 3.3-Input and Output Voltage.

Figure 3.4-Input and Gate-Source Voltage.


18

Switch resistance in ON state is given in figure 3.5, with values in Ohm. It can be seen

that the switch resistance is relatively low, R400Ω, and its variation with input signal is also

low ΔR=20%, so in these terms, the performance was found satisfying.

Figure 3.5-Input Voltage and Resistance.

3.3.2 Signal Spectrum Estimation

3.3.2.1 The Basics of Discrete Spectrum

Performance of an ADC is measured with its resolution determined by SNR and

SNDR, FOM, power and sampling frequency. In this project main focus was set to resolution,

so speaking of performance of a circuit means speaking of its SNR and SNDR. These

measurements were obtained using spectral simulations. Spectrum of sampled signals was

calculated and plotted using MATLAB functions and Fast Fourier Transform (FFT). The

number of samples in FFT was generally taken to be M=1024.

In order to reduce spectral leakage in simulations, coherent sampling was used.

Coherent sampling refers to a certain relationship between input frequency fin, sampling

frequency fs, number of cycles Ns and number of samples in FFT, M. With coherent sampling

it is always sure that signal energy for a single sinusoidal input signal falls into one FFT bin.


19

The condition for coherent sampling is:

(10)

where Ns/M is not integer number, smaller than 0.5 in order to avoid undersampling. Ns and

M are relatively prime numbers, and M is usually considered to be power of 2. Another way

of dealing with spectral leakage is “windowing” time samples prior to FFT, where the time

samples are multiplied with window function (Kaiser, Blackman, Hann) on a sample-by-

sample basis. In this project, for every performance simulation number of samples M was set

to 1024 and number of cycles was set to 97 in order to fulfill conditions for coherent

sampling. Windowing with Kaiser window function was used in order to obtain more accurate

results for SNR and SNDR.

3.3.2.1 Interpretation of Spectrum Figures

Calculation of SNR in this project was done including value for noise through entire

Nyquist bandwidth: from the dc component to fs/2. The same approach is used for all the SNR

and SNDR measurements through this work.

FFT acts as a narrowband spectrum analyzer with a bandwidth per bin of fs/M. This

has the effect of pushing down noise floor by an amount equal to process gain .The theoretical

noise floor of FFT is equal to theoretical SNR plus FFT process gain:

process gain=10⋅log10(M/2). (11)

This is relevant because calculated results for SNR can be confirmed from plotted

spectrum based on FFT of sampled signal, subtracting the signal amplitude and noise floor.

For correct and reliable spectrum interpretation, FFT plot should be either marked with

number of samples used, M, or the noise floor should be shifted up by amount equal to

process gain. In this report, for every plotted spectrum, noise floor stayed 10⋅log10512=27 dB

lower than calculated SNR, and the number of samples M=1024 is clearly specified.

3.3.2.3 SNR and SNDR Measurements

For the SNDR and SNR performance simulation of the switch, a more realistic

testbench than a simple track-and-hold circuit was used. That testbench is shown in figure 3.6.

Bootstrapped switch was marked with a special symbol, so it can be distinguished from a

regular switch. Sampling frequency was set to fs=1MHz, and according to equation (10)

frequency of the input sine wave was set to fin=94.7265625kHz.


20

1 12C C

Out1 Out2

VIN

Figure 3.6-Realistic Testbench.

Testbench shown in figure 3.6 is more appropriate for simulating SNR and SNDR of

the switch, since it resembles the conditions under which the switch will be in the final circuit.

Results of simulation are given in figure 3.7. It can be seen, that after the closing of the

bootstrapped switch there is a loss in capacitors charge due to charge injection.

Figure 3.7-Input Voltage and Capacitance Voltage for Testbench in Figure 3.6.

SNR and SNDR were calculated for two cases. The first one was using the samples of

VOut2 before the switch opens and charge injection distorts the charge sampled on capacitor a),

and the second one was after the switch opens b). This was done in order to determine if

charge injection is signal dependent, and estimate how much. The results are shown in table

3.2, along with on-resistance variation and VGS variation, for rail-to-rail (0-1.8V) sine wave

input signal.


21

Table 3.2-Results of Performance Simulation.

Case SNR [dB] SNDR [dB]

a) 61.7 61.2

b) 60.7 59.2

Max variation in VGS 1.14%

Max variation in RON 20%

From the values in table 3.2, it was concluded that switch performance is satisfying for

usage in an 8 bit cyclic ADC.

Spectrum of sampled signals for cases a) and b) are given in figure 3.8.

Figure 3.8-Spectrum of Sampled Signal for Case a) and b), M=1024.

Note that noise floor in figure 3.8 is around -90dB, which is 27dB lower than the SNR

from table 3.2.


22

4. Zero-Crossing Detector

4.1 Introduction

In previous chapters, comparator based switched capacitor circuits have been

introduced as alternatives to op-amp based switched capacitor circuits. That architecture

replaces op-amp with a combination of comparator and a current source as seen in Chapter 2.

Comparator is supposed to detect virtual ground condition. In this chapter zero-crossing

detector design [6], which replaces comparator for CBSC, is presented.

4.2 Zero Crossing Detector-Principle of Operation

Unlike regular clocked comparators that are comparing voltage at a specific point in

time, zero-crossing detectors, which should be used in CBSC, should determine only the

event of input voltage zero-crossing. Simplified operation of zero-crossing detector is shown

in figure 4.1.

VCM

+

-

VIN

Q

VX0

VIN

VCM

Q

VDD

Figure 4.1-Functionality of Zero-Crossing Detector.

As mentioned in Chapter 2, the role of virtual ground detection is of critical

importance for CBSC accurate charge transfer. In this implementation proposed zero-crossing

detector, based on work of Lane Brooks and Hae-Seung Lee [6], is shown in figure 4.2 with a

simplified timing diagram in figure 4.3. A basic difference between implemented ZCD in this

project and the one proposed in [6] is the transistor which in [6] shuts off ZCD after zero-

crossing detection. In implemented design in this project mentioned transistor was eliminated.

This is done in order to eliminate kick-back noise although previous was more power

efficient.


23

VDD

VDD

VO

M1 M2

M3 M4

M5

M6 M7

M8

M9

Vi+ Vi-

V1

2I

2I

Vbp

Figure 4.2- Implementation of Zero-Crossing Detector [6].

The first stage of the ZCD is differential to single-ended pre-amplifier. The pre-

amplifier is implemented with an NMOS differential pair M1 and M2. A current mirror M3

and M4 is used to convert from a differential signal to single-ended output. Pre-amplifier is

followed by a Dynamic Threshold Detecting Latch (DTDL). This DTDL is a dynamic logic

circuit that draws no static current. During the pre-charge phase when 2I is low, M9 turns on

and M8 turns off, and the latch is reset. When 2I begins to rise, voltage V1 begins to rise. The

zero-crossing is detected when the virtual ground condition is detected, and V1 raises enough

to flip the state of the latch. Simplified timing diagram ZCD based SC circuits is given in

figure 4.3.

1

2

2I

Vi+ Vi-=VCM

Sampling phase

Transfer phase

Zero-crossing

detected

Figure 4.3-Timing Diagram of ZCD Based SC Circuits [6].


24

4.3 Simulations

Functional simulation is given in figure 4.4. ZCD sensitivity was determined to be

12mV.

Figure 4.4-Functional Simulation of ZCD.

ZCD delay simulation is given in figure 4.5. Delay was determined to be 19ns.

Figure 4.5-ZCD Delay Simulation.


25

However, input signal of the ZCD will not be as fast ramp as in delay simulation in

figure 4.5; it will be a constant slow ramp with a ramp rate depending on the value of current

from current source I1. For that kind of slow input ramp testbench, delay was determined to be

6ns.

For the ZCD offset estimation, a specific testing had to be applied, because input

referred offset simulation is not possible in this case. Offset of interest in this case is a

dynamic offset which is not always equal to static offset measured via traditional techniques.

For the proposed method a specific testbench is used [10]. Additionally, dedicated input had

to be provided. The input signal x, of the ZCD has to be ladder-shaped, as in figure 4.6.

+

-

x

xth

y

xth

x

t

t

y

Figure 4.6-Offset Simulation of the Zero-Crossing Detector.

Input signal x from the figure 4.6, in testbench was provided with triangular input

ramp followed by track-and-hold circuit. For each input value xi output of the ZCD yi is

stored. For an ideal ZCD for all input values xi below xth output should be 0, and if xi greater

than xth output will be 1. Taking device parameter mismatch into account, this behavior will

randomly change.

To evaluate the influence of process variation and the random device mismatch

Monte-Carlo analysis was used. The results of each Monte-Carlo simulation, yi, were

collected. For each input value, the probability that output value is 1 is P (yi=1) =ni/N=zi,

where N is the number of Monte-Carlo iterations and ni is the number of runs where ZCD

output is 1 when xi is applied. That probability or cumulative normal distribution function

is the integral of xoff probability density function f(x). Since xoff can be assumed to have

Gaussian distribution:

(12)

. (13)

Hence, the statistical properties of xoff can easily be computed, by applying the inverse

of the cumulative normal distribution function to zi [10].


26

The results of 100 runs Monte-Carlo simulation are given in figure 4.7. Ideally, ZCD

threshold should be xth= 0.9 V, therefore for simulation purposes xi was set in interval:

xi [0.8V, 1V].

Figure 4.7-Cumulative Histogram and Normal Probability Plot.

The mean value and standard deviation , of offset calculated from normal

probability plot from figure 4.7, assuming that the points form approximately straight line

(green) are:

=-9.9mV

=0.11mV.

Mean value and standard deviation are acceptable for ZCD implementation in CBSC

circuit.


27

4.4 ZCD Improvement for 2 Phase CBSC

The configuration of ZCD presented in [6] and shown in figure 4.2 is not suitable for

usage in CBSC with two phase charge transfer shown in Chapter 2. For that reason, the circuit

was slightly changed, as shown in figure 4.8.

In this implementation, pre-amplifier is followed by two DTDLs. The modified circuit

works as follows: during the pre-charge phase when 2I is low, the latch is reset when M9

turns on and M8 turns off. When 2I begins to rise, voltage V1 begins to rise as well. The first

zero-crossing is detected when the virtual ground condition is achieved, and V1 raises enough

to flip the state of the latch. Because of finite ZCD delay there is an overshoot above virtual

ground condition. Correction of that overshoot by obtaining more accurate virtual ground

condition is done with the second latch. The rising edge of the ZCD output VO creates pulse

on 2I2 which resets second latch. When 2I2 drops, voltage V1 begins to drop. The second

zero-crossing is detected when the virtual ground condition is achieved for the second time

and voltage V1 has dropped sufficiently to flip the state of the second latch. The timing

diagram for new implementation is shown in figure 4.9.

VDD

VO

M1 M2

M3 M4

M5

M6 M7

M8

M9

Vi+ Vi-

V1

2I

2I

Vbp

VDD

VO2

M10 M11

M12

M132I2

2I2

Vbias

First DTDL

Second DTDL

Figure 4.8-Improved Implementation of Zero-Crossing Detector.


28

1

2

2I

Vi+ Vi-=VCM

Sampling phase

Transfer phase

VO

2I2

VO2

Figure 4.9-Timing Diagram for ZCD in Figure 4.8.

4.4.1 Functional Simulation for a New ZCD

Functional simulation of ZCD implementation from figure 4.8 is given in figure 4.10.

It can be seen that now the ZCD output function, with two outputs VO and VO2 is suitable for

implementation in CBSC circuits with two phase charge transfer.


29

Figure 4.10-Functional Simulation of Improved ZCD.


30

5. CBSC Gain Stage Implementation

5.1 Introduction

In previous chapters comparator based switched capacitor circuits and their

components have been introduced and simulated. In this chapter a complete CBSC

multiplying stage design will be presented with corresponding simulation results.

5.2 CBSC-Complete Schematic

Complete schematic of CBSC gain stage is given in figure 5.1.

VIN +

-

VX

VCM

1

1

2

VCM VCM

1A

E1

E2

I1

I2

n2I

C2

C1

CL CL

2

VCM

VOUT

2I2I2

Vbias

Vbp

VO

L

O

G

I

C

VO E1

E2

2I

CK2I2

Figure 5.1-Complete Schematic of CBSC Gain Stage.

All capacitances in figure 5.1 are set to 4pF and the gain of the stage is set to 2, C1=C2

(equation (1), Chapter 2). There are two capacitors at the output which is needed for the later

implementation of CBSC gain stage in cyclic ADC (Chapter 7). Logic circuits and several D

flip-flops (DFF) were used to provide control signals E1 and E2.

5.3 Functional Simulation

In figure 5.2 and figure 5.3 results of functional simulation are given for a triangular

signal at the input. Sampling frequency was set to 1MHz, so time allocated for a single

operation was 1us. Maximum input signal range was set to 0.6V. In theory maximum swing

could be 0.9V (equation (3)), but constraints for cascoded devices in current sources for

correct operation decrease signal range. The corresponding output signal range was then set to

1.2V. Figure 5.3 shows zoomed-in single charge transfer phase waveforms for VX,VOUT, E1

and E2. Signal E1 is inverted because it drives PMOS transistor current source. It can be seen

from figure 5.3 that all the relevant signal have the same behavior as described in Chapter 2.


31

Figure 5.2-Functional Simulation of CBSC Gain Stage.

Figure 5.3-Zoomed in One Charge Transfer of CBSC Gain Stage.


32

5.4 Current Sources

Variation in current source charge-current due to finite current source output

resistance creates ramp rate variations [4]. Also, reaching maximum output voltage swing

drives transistors in current sources in linear regime which also leads to ramp rate variations.

The output voltage nonlinearity is mostly due to overshoot variations which is a consequence

of ramp rate change. To reduce output voltage nonlinearity a constant ramp rate is required

across the full-scale output voltage range.

In the first version the current sources consisted of one transistor and additional

switches as shown in figure 5.4.

E2

nE2

VB2

OUT

OUT

E1

VDD

Figure 5.4-Single Transistor Current Sources.

Functional simulation was satisfying, but the results of performance simulations in

terms of SNR and SNDR were not acceptable, since they were under 50dB. Therefore, a

different solution had to be found for the implementation of the current sources.

One method of improving a current source is by increasing the output resistance.

Hence in the second version cascoded current sources were used as shown in figure 5.5. This

solution further decreased signal range.

E2

nE2

VB2

OUT

OUT

E1

VDD

VBIAS2

VBIAS1

Figure 5.5-Cascoded Current Sources.

As previously mentioned, in order to improve FOM, time spent on phase E1, TE1

should be much smaller then time spent on phase E2, TE2. Therefore, amplitude of current I2

should be much smaller than amplitude of current I1.


33

Delay of the ZCD output VO in this CBSC implementation was td6ns as explained in

Chapter 4. This latency generates an overshoot (compared to the ideal level) of around 18%.

For minimum amplitude of the input signal (worst case) TE2=8⋅TE1. With TE1=2⋅td, TE2=16⋅td.

This makes T/418⋅td=108ns, and fsMAX2.3MHz. In simulations, sampling frequency was set

to 1MHz.

Current source I1 (I2), is supposed to charge (discharge) capacitive network which

consists of capacitors C1, C2, CL and CL. Fraction of the current I1 (I2), I11 (I21) charges

(discharges) serial network of C1 and C2 with equivalent capacitance Ceq1=2pF, while the rest

of the current I12 (I22) charges (discharges) parallel network of CL and CL with equivalent

capacitance Ceq2=8pF. Current I11 should sweep through voltage ranges of ΔU11= 0.25V to

0.85V, while current I12 should sweep through voltage ranges of ΔU12=0.5V to 1.7V. Using

equations:

(14)

and

, (15)

the value for current I1 was calculated to be:

I1400uA.

Current I21 should sweep through range ΔU210.1V, and current I22 should sweep through

range ΔU220.2V. Using equations:

(16)

and

, (17)

the value for current I2 was calculated to be:

I215uA.

These values had to be adjusted during the implementation in the whole circuit because of

parasitic capacitances and switches resistances. The final values for currents were set to:

I1=530uA

I2=19uA


34

5.5 Performance Simulation

Results of performance simulations in terms of SNR and SNDR are given in table 5.1.

Sampling frequency was set to fs=1MHz, and according to equation (10) frequency of the

input sine wave was fin=94.7265625kHz. Results were calculated for two cases a) and b), as in

Chapter 3, to include the results before and after charge injection. Spectrum of sampled

signals for cases a) and b) are given in figure 5.6.

Table 5.1-Results of Performance Simulations.

Case SNR [dB] SNDR [dB]

a) 67.7 62.6

b) 66.5 59.4

Figure 5.6-Spectrum of Sampled Signal for Cases a) and b), M=1024.

Since performance in terms of SNDR is in both cases around 60dB, performance of

the gain stage is satisfying for implementation in proposed 8 bit cyclic ADC. Continuation of

the gain-stage design, including adding 1.5-bit architecture is followed, and introduced in the

next section.


35

6. 1.5 Bit-per-Stage Architecture

6.1 Introduction

A single bit decision comparator precision can be a limiting factor in ADC design for

high resolutions. In this chapter principle of adding redundancy bits, or over-range protection,

for relaxing bit decision comparator offset constraints will be presented.

6.2 Basic Concept

When using one comparator per stage (pipeline ADC) or cycle (cyclic ADC), there is

one bit which corresponds to two levels, D 0, 1. Transfer function for VOUT/VIN for a

simple fully-differential signals ADCs with decision bit D, is given in figure 6.1 [1]. This

transfer curve corresponds to:

(18)

where Vref is the output voltage range.

VIN

VOUTVref/2

-Vref/2

-Vref/2 Vref/2

0

D=0 D=1

Figure 6.1-Residue Plot.

The 1.5 bit-per-stage (-cycle) ADCs allow more relaxed requirements for bit decision

comparators. In this case, for each stage, two comparators are used, with three levels D1D0=

00, 01 and 11. Since two levels D=0 and D=1 make 1 bit per stage, with three levels, 1.5 bit-

per-stage is realized. In this case a signed digit set is used, D -1, 0, 1.The signed digit set

corresponds to comparator output codes respectively D1D0= 00, 01 and 11 [1]. Transfer curve

equation is:

. (19)


36

Transfer curve for this case is given in figure 6.2.

VIN

VOUTVref/2

-Vref/2

-Vref/2 Vref/2

0

D1D0=00 D1D0=11D1D0=01

-Vref/8 Vref/8

Figure 6.2-Residue Plot for 1.5 Bit-per-Stage.

Observing figure 6.2 it can be seen that the output range at bit decision boundaries is

reduced compared to the output range in figure 6.1. Moreover, an important property of 1.5

bit-per–stage algorithm is that the comparator offset up to –Vref/8<Voff<Vref/8 can be

corrected in digital domain [11]. This property significantly relaxes comparator precision

which leads to less power dissipation of comparators.

Generation of the final output code using 1.5 bit algorithm in an ADC requires special

data processing. The easiest way, which was used in this work, is to encode output bits D1D0=

00, 01 and 11 into D1’D0’=00, 01 and 10 respectively. Now, two encoded digital outputs

D1’D0’ from each stage are added together with one bit of overlap between adjacent stages.

Ignoring the far right digit, the final output code is this way obtained starting from the MSB.

For example, in the case of VIN taking the maximum value, in this case Vref/2 as in figure 6.2,

and assuming that the ADC has 3 bits, b2b1b0, output bits of the comparator would be:

(D1D0)2=11, (D1D0)1=11, (D1D0)0=11.

Encoded bits would be:

(D1’D0’)2=10, (D1’D0’)1=10, (D1’D0’)0=10.

Now the final output code would be:

10

10

+ 10

1 1 1 0

b2b1b0=111 which corresponds to maximum input voltage, VIN= Vref/2.


37

6.2 Implementation of 1.5 Bit-per-Stage Algorithm in CBSC

A complete schematic of CBSC gain stage with 1.5 bit-per-stage scheme is given in

figure 6.3. Since output and input signals are single ended (unlike example in previous

chapter where they are differential), comparator thresholds are set to VCM+VREF/4 and VCM-

VREF/4 where 2⋅VREF is input signal range. To generate phases for switches 2(D1,D0), which

implement three different reference voltages needed for 1.5 bit-per-stage scheme, logic

circuits in combination with SR latches, and DFFs were used. That logic was not presented in

figure 6.3 for simplicity.

VIN +

-

VX

VCM

1

1

VCM

VCM

1A

E1

E2

I1

I2

n2I

C2

C1

CL CL

2

VCM

VOUT

+

-

+

-

D1 D0

VIN VIN

VCM+VREF/4

2(D1,D0)

2I2I2

Vbias

Vbp

VCM-VREF/4

VCM+VREF VCM-VREF

L

O

G

I

C

VO

E1

E2

VO

2I

CK2I2

Figure 6.3-Implemenation of a CBSC Gain Stage with 1.5 Bit-per-Stage Scheme.

6.3 Functional Simulation

Bit decision comparators were implemented as ideal components using Verilog code.

The phases for switches 2(D1,D0) had to be carefully generated. When one switch is

conducting (its f1n is high), phases f2n of the other switches had to be high as well, meaning

that they must not be floating (f1n and f2n low), they had to be definitely in the state of non-

conduction. The results of functional simulation for the complete 1.5-bit gain stage are given

in figure 6.4. These results of correspond to transfer function shown in figure 6.5. Observing

figures 6.4 and 6.5, it can be concluded that 1.5 bit-per-stage scheme was successfully

implemented.


38

Figure 6.4- 1.5-Bit Gain Stage Functional Simulation.

VIN

VOUT

D1D0=00 D1D0=11

VCM

VCM-VREF/4 VCM+VREF/4

VCM-VREF VCM+VREF

VCM

VCM-VREF

VCM+VREF

VCM+VREF/2

VCM-VREF/2

D1D0=01

Figure 6.5-Residue Plot for Single Ended Signals.


39

7. Cyclic ADC Implementation

7.1 Introduction

In previous chapters all the components of the proposed ADC were presented and

simulated. In this chapter final implementation of cyclic ADC will be explained functional

and performance simulations presented in detail.

Cyclic ADCs usually have the small area, but they require N cycles for the N bit

resolution [1]. Typical block diagram of a cyclic ADC is given in Chapter 1, figure 1.2. In this

report cyclic ADC was implemented with 1.5 bit-per-cycle algorithm and the architecture of

ADC is given in figure 7.1 [11].

T&H + *2+

-

VIN VOUT

D1(i) D0(i)

Vref/8 -Vref/8

+ - + -

Vref/4 -Vref/4

D1(i)*

D0(i)

D1(i)*

D0(i)

D1(i)*

D0(i)

Figure 7.1-Architecture of Cyclic ADC with 1.5 Bit-per-Cycle Algorithm.

Architecture in figure 7.1 corresponds to residue plot in figure 6.2. Principle of

operation of the circuit is the following: in the first cycle, VIN is sampled, and corresponding

bits D1(0) and D0(0) are determined by bit decision comparators. Depending on the values of

D1D0, zero or Vref/4 are added or subtracted from the sampled input voltage. The final result

of this operation is multiplied by 2. This operation is repeated cyclically, along with the

sampling of the previous cycle’s VOUT instead of VIN. For an N bit resolution this operation is

repeated N-1 times.


40

7.2 Cyclic ADC CBSC Implementation

Complete schematic of CBSC based cyclic ADC with 1.5 bit-per-cycle is given in

figure 7.2.

VIN +

-

VX

VCM

1

1

VCM VCM

1A

E1

E2

I1

I2

n2I

C

C

C C

VCM

VOUT

2(D1,D0)

2I2I2

Vbias

Vbp

VCM+VREF VCM-VREF

VO

E2

+

-

+

-

D1 D0

VINVIN

VCM+VREF/4 VCM-VREF/4

VOUTVOUT

VCM

1A

2

2

2

VCM

Figure 7.2-Complete Schematic of CBSC Cyclic ADC with 1.5 Bit-per-Cycle.

Final implementation of the cyclic ADC included four capacitors, switching positions

from input to output, after each single cycle. The top-level circuit has both bootstrapped

switches and regular NMOS switches. NMOS switches were used only at those places where

they cannot introduce the additional distortion. In figure 7.2 phases are color-coded. The blue

phase represents sampling of input signal, and the red phase represents transfer charge phase.

To generate the phases for switches and control signals E1 and E2 combinational logic

with several DFFs were used. However, the additional digital circuitry is not presented in

figure 7.2 for the sake of simplicity; it is presented in Appendix D.


41

7.3 Simulations

7.3.1 8 Bits Implementation

The ADC converter was implemented as an 8 bit converter. Results of performance

simulation are summarized in table 7.1. Sampling frequency was set to fs=125kHz, and the

results are shown for the input sine wave at fin=11.8408203125kHz.

Table 7.1-8 Bit ADC Performance Summary

fS 125kHz

Supply voltage 1.8V

DNL +0.5/-0.5 LSB

INL +1/-1 LSB

SFDR 59dBc

SNDR 46.8dB

SNR 47.7dB

ENOB 7.48 b

Power 0.98mW


) 21pJ/step

Spectrum of quantized signal is given in figure 7.3

Figure 7.3-Spectrum of Quantized Signal, M=1024.

ADC simulated transfer curve compared with an ideal transfer curve of an 8 bit ADC

is given in figure 7.4.


42

Figure 7.4-ADC Transfer Curve.

Integral non-linearities (INL) and differential non-linearities (DNL) are given in figure

7.5.

Figure 7.5-Differential and Integral Non-Linearities.


43

SNR and SNDR versus input signal amplitude are given in figure 7.6. Input signal

amplitude level was calculated with respect to maximum input signal amplitude that is from

equation (3) equal to 450mV.

Figure 7.6-SNR and SNDR versus Input Signal Amplitude

All ADCs have minimum rms noise that the quantization error generates, thus ADC’s

ideal SNR for the noise that extends over the entire Nyquist bandwidth fs/2 is:

SNR=6.02⋅N+1.76 dB. (20)

Observing equation (20) for N=8 bit converter, it can be seen that SNR=49.92dB is the

maximum possible SNR for an 8 bit converter when only the quantization noise is present.

Results for SNDR of the implemented converter from table 7.1 being 3dB bellow maximum

suggest that there is no significant non-linearity that would dominate the noise. Therefore,

N=8 bits is not the maximum achievable resolution of this ADC, and expanding towards

higher number of bits N=9, 10 could definitely be a possible improvement.


44

8. Future Work

8.1 Introduction

Specification of this thesis required an 8 bit ADC, and the results from Chapter 7.3

shows that a satisfying performance was achieved. In this chapter some of the ideas for

improvement and possible implementation with higher number of bits will be presented.

8.2 Improvements Step-by-Step

Since from the beginning of this project, implementation of 8 bit cyclic ADC was

targeted, the full design flow was adjusted according to this requirement. Hence, the

improvements for the final design need to start from each individual building block and then

move on to the whole system.

8.2.1 Bootstrapped Switch

Observing the performance results from Chapter 3, it can be seen that sizing of the

transistors was done in order to satisfy final requirements for SNDR of over 60dB. Moreover,

size of the load was set to be large enough in order to reduce charge injection, clock

feedthrough, and of course kT/C noise, but small enough to have a reasonable die area and

acceptable power budget. Since there is a large number of switches in the final

implementation because of switching capacitors from input to output, more detailed sizing

and improving switch performance regarding SNDR can contribute to SNDR of whole circuit.

Regarding charge injection and clock feedtrough, larger capacitors could be used, however

with a price to pay in circuit area and power consumption. Furthermore, adding dummy

transistors to form a symmetric dummy switch for charge injection compensation [7] is one of

the options.

8.2.2 Zero-Crossing Detector

As the available maximum signal swing decreases in scaled technologies, offset

compensation is becoming a very important task in CBSC circuit design. Increasing

robustness of ZCD to process variations, device mismatches and ramp rate variations will

result in higher circuit performance. Traditional closed loop offset cancellation technique is

not possible here, because CBSC cannot drive both sides of the sampling capacitor at the

same time. Moreover, the offset in CBSC is dynamic and not always equal to static offset

measured by the closed loop technique. A comparator offset correction proposed in [5], by a

programmable pre-amplifier, can make charge transfer phase more accurate, and reduce

overshoot variations.


45

Proposed ZCD design is also suitable for fully-differential circuits, hence expanding

the ADC to a fully-differential topology instead of the single-ended circuit will definitely be

more suitable for high-resolutions.

8.2.3 Current Sources

Current source charge-current variations are the main source of overall circuit

nonlinearities. This can be seen in Chapter 5, where even a small improvement of transistor

cascoding in the current source resulted in a significant improvement of the final circuit

SNDR. For low supply voltages, cascoding of current sources, used in this work would not be

an option. Even for supply voltage of 1.8V, transistors in current sources at the output swing

limits, max VOUT and min VOUT, change their operating region from saturation to linear

region, which leads to the output resistance reduction and consequently increased

nonlinearity. One of the possible solutions for ramp linearity enhancement may be a simple

integrator implementation presented in [4].

8.2.4 Residue Plots

The reduction of the supply voltage in deep sub-micron technologies in addition to

design limitations such as the need for cascoded devices leaves a very low remaining output

range. On the other hand, input range may not be so limited, but as seen in residue plots from

Chapter 6, input range is usually shrank to match the output range. An alternative approach is

to change residue plots [5], and increase Vref until the output voltage of the interior step

transition reaches the maximum output range (in Chapter 6 it reaches half of the maximum

output range). With this approach input range can be increased 1.5 times, which leads to an

increase of overall SNR. The problem is then a bit more complicated decoding of output bits

[1] and their processing in order to obtain the final output code. In addition, adding more

redundancy is one of the options.


46

9. Conclusion

In this report, the comparator based switched capacitor circuit technique proposed in

[3] was explored and implemented as a 1.5 bit-per-cycle cyclic analog to digital converter in

180nm UMC standard CMOS technology. The proposed technique eliminates the need for an

op-amp in the signal path, and replaces it with a combination of a comparator and current

sources in order to realize the same charge transfer as the op-amp based implementation. This

technique can be applied to the majority of architectures that were previously based on an op-

amp, and it is more suitable for design in deep submicron technologies.

As the part that restricts the performance of track-and-hold circuits, bootstrapped

switch was designed as proposed in [5] with minor modifications. The sizing and simulation

results were presented, and the final performance proved to be more than satisfactory for an

8-bit implementation.

Proposed zero-crossing detector [6] that replaces the comparator in CBSC was

implemented, with an improved architecture for supporting two-phase charge transfer

scheme. Offset, delay, sensitivity and functional simulations were also presented.

Comparator based switched capacitor gain stage, with a gain of 2 was implemented, as

a first step towards the whole circuit. Both functional and performance estimation

simulations were presented, and results were analyzed and found satisfying.

The principle of adding redundancy for relaxation of bit decision comparator offset

constraints was explained, and its implementation in comparator based switched capacitor

circuit was presented with its functionality shown in simulation results.

Finally, the whole cyclic 1.5 bit-per-cycle analog-to-digital single-ended 8-bit

converter was implemented with a sampling frequency of 125kHz. Performance simulation

results were presented and analyzed. The ADC achieves 7.5 effective bits of accuracy, has

SNR of 47.7dB, SNDR of 46.8dB, SFDR of 59dBc and consumes 0.9mW of power. It is also

important to say that the sampling rate and effective number of bits are not the maximum

achievable for this design, they were determined based on specifications of this project.

Work previously done in this field [3] [4] [6] [7] was focused on pipeline converters.

Therefore some of the issues and their solutions regarding implementation of cyclic

converters in CBSC technique were addressed here for the first time.

Possible expansions and improvements towards higher resolution and higher speed

were also suggested. Those improvements should start from each individual block, including

more detailed sizing of bootstrapped switch, adding offset cancelation in ZCD and improving

linearity of current ramp rate, and then move towards the whole system, with possible

expansion to fully-differential design and adding of more redundancy. However, being a

relatively new technique, CBSC circuit performance limitation is not yet fully explored.


47

Acknowledgments

This work and this final report are the results of master thesis project carried out at

Ecole Polytechnique Federale de Lausanne (EPFL). This master thesis is also the final part of

Master of Science degree at EPFL. It has been done within Microelectronic Systems

Laboratory (LSM), lead by Professor Yusuf Leblebici, and under the supervision of Mr.

Nikola Katić and Dr.Alexandre Schmid.

The comparator based switched capacitor circuits are the solution of many problems

that standard op-amp based designs are facing in deep submicron technologies. They have

many potential advantages, but being a relatively new technique, their limitations are not

fully explored. They are described by many as the main future direction of SC circuit design.

This report firstly introduces switched capacitor circuits and their novel

implementation, based on a zero-crossing detection-CBSC. As a second point,

implementation of CBSC circuit in cyclic ADC is presented with its overall performance

results. Some future works regarding improvements of this project are also shortly presented.

In the end I would like to thank the LSM team for giving me the opportunity to work

on such an interesting project, and expand my knowledge in the field. I would especially like

to thank my supervisor Nikola Katić, for all the help, guidance and knowledge which he

shared during my work on this project, and also for having the patience to listen to me and to

answer all of my questions. I would also like to thank professors Alexander Schmidt and

Yusuf Leblebici from LSM, professor Alain Vachaux for taking care of all the technical

details regarding my work in LSM, and a former LSM member Vladan Popović who

suggested LSM as a great place to learn.

I would also like to thank my parents Lazar and Gordana, and my sister Tijana for

supporting me throughout my whole studies, my professors from ETF Belgrade, who gave

me excellent pre-requirements and needed knowledge for joining EPFL, my best friend

Jelena Popović for always being an example of how many things you can achieve when you

really want to, all my friends and colleagues here in Lausanne for the last year and a half

Nikola Veličković, Miloš Balać, Janko Katić and Marko Stojanović. And in the end, I would

like to thank the person who gave me the idea to come here in the first place, and being

always there for me, Nemanja Popović.


48

References

[1] R.Jacob Baker ,“CMOS Circuit design, layout and simulation”, third edition.

[2] Marcel J.M. Pelgrom, “Analog to digital conversion”.

[3] John K. Fiorenza, Todd Sepke, Peter Holloway, Charles G. Sodini and Hae-Seung Lee

“Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE

journal of solid-state circuits, vol. 41, no. 12, December 2006.

[4] Kush Gulati, “Ultra-Low Power Opamp/less ADCs”, Cambrige Analog Technologies,

July 2010.

[5] M. Dessouky, M.-M. Louerat and A. Kaiser, “Switch sizing for very low-voltage

switched-capacitor circuits”, IEEE, 2001.

[6] Lane Brooks and Hae-Seung Lee, “A 12b, 50 MS/s, Fully Differential Zero-Crosing

Based Pipelined ADC”, IEEE journal of solid-state circuits, vol. 44, no. 12, December 2009.

[7] Kush Gulati, “Ultra-Low Power Opamp/less ADCs”, Cambrige Analog Technologies,

July 2011.

[8] Todd C. Sepke, “Comparator Design and analysis for Comparator-Based Switched

Capacitor Circuits”, Massachusets institute of technology, September 2006.

[9] Franco Maloberti, “Analog Design for CMOS VLSI Systems”.

[10] Achim Graupner, “A Methodology for the Offset Simulation of Comparators”, 2006.

[11] Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori and Masanori

Furuta, “A Wide Dynamic Range CMOS Image Sensor With Multiple Exposure Time Signal

Outputs and 12 bit Column Parallel Cyclic A/D Converters”, IEEE journal of solid-state

circuits, vol. 40, no. 12, December 2005.


49

Appendix A

This appendix contains MATLAB code for all data processing such as SNR and SNDR

calculation etc.

A.1 SNR and SNDR Calculation function [s2nd,s2n,ydB] = fcn_sndr_v1(S,fvec) % % [S2ND, S2N, YDB] = SNDR(S,[M,Finput,Fband,Fs]) % % S : input signal % M : size of PSD vector % Finput : input sinusidal freq. % Fband : bandwith % Fs : sampling freq. M=fvec(1); Finput=fvec(2); Fband=fvec(3); Fs=fvec(4); df = Fs/M; f = [0:1:M-1]*df; win = kaiser(M,25); Ns = max(size(S)); x = S(Ns-M+1:Ns); y = x(1:M).*win(1:M); yfft = fft(y); ymag = sqrt(abs(yfft.*conj(yfft)))/(M/8); % Lobe calculation Asl=175 Asl=175; wml=(12*(Asl+12)/(155*(M-1)))*M; lobe=round(wml/2)+1; ymag2 = ymag.^2; ydB = 10*log10(ymag2); % find basic signal f1=round((Finput/Fs)*M); fb=round((Fband/Fs)*M); if (f1 < (lobe+1 ) ) [ymax,fmax]=max(ymag2(1:f1+5)); f2=fmax+lobe; spwr=sum( ymag2(1:f2) ); ndpwr=sum( ymag2(1:fb))-spwr; else [ymax,fmax]=max(ymag2(lobe+1:f1+10)); fmax=fmax+lobe; f1=fmax-lobe; f2=fmax+lobe; spwr=sum( ymag2(f1:f2) ); ndpwr=sum( ymag2(lobe:fb))-spwr+(f2-

f1)*(ymag2(f2)+ymag2(f1))/2; end fMain = round((Finput/Fs)*M)+1; fBW = fb+1; Nh = floor(fBW/fMain); dlobe = lobe; for jj = 2:Nh fh = jj*fMain-jj+1; fa = fh-dlobe; fb = fh+dlobe;


50

dpow_h(jj) = sum(ymag2(fa:fb)); rep_noi(jj) = (fb-fa)*(ymag2(fb)+ymag2(fa))/2; end dpow = sum(dpow_h)-sum(rep_noi); s2nd = 10*log10(spwr/ndpwr); s2n = 10*log10(spwr/(ndpwr-dpow));

function snr_sndr(S)

M = 1024; Fin = 11840.82031; Fs = 125000; Fbw = Fs/2;

Fvec = [M,Fin,Fbw,Fs];

[s2nd,s2n,ydB] = fcn_sndr_v1(S,Fvec);

s2nd s2n

freq_range = 0:Fs/(M-1):Fs/2; figure (1) plot(freq_range,ydB(1:M/2)); title('Spectrum of sampled output') xlabel('f [Hz]') ylabel('Amplitude [dB]')

end

A.2 ZCD Offset Calculation

function offset (xdata,ydata)

y=sum_up(ydata); for i=1:512 x(i) = xdata(i); end; figure (1) subplot(2,1,1) plot (x,y); title ('Result of Monte-Carlo simulation-cumulative histogram') xlabel('xi [V]') ylabel('ni/N') v = sqrt(2)*erfinv(y(1:512)*2-1); m=find(v>-2.5 & v<2.5); [p,s]=polyfit (x(m),v(m),1); subplot(2,1,2) plot(x(m),v(m), x(m),polyval(p,x(m))); title ('Normal probability plot') xlabel('xi [V]') ylabel('ni/N')

sigma=1/p(1); mu=-p(2)/p(1); sigma mu end


51

function y=sum_up(ydata)

for j=1:512

y(j)=0;

end

for j=1:512 for i=1:100 k=j+(i-1)*1024; y(j)=y(j)+ydata(k); end end for j=1:512

y(j)=y(j)/100; end end

A.3 DNL and INL Calculation

function DNL (in,out)

s=0; for i=1:512 if (out(i+1)>out(i)) dnl(i) = -(out(i+1)-out(i)-1-s); s=0; else s=s+0.5; dnl(i)=0; end end figure (1) plot(out(1:512),dnl(1:512)); title('Differential non-linearities') xlabel('Output code') ylabel('DNL') end

function INL (in,out)

x=-0.5:254.5; x1=reshape(x,256,1); [p,s] = polyfit (in,x1,1); plot(in(1:512),out(1:512),in,polyval(p,in),'r'); title('ADC transfer curve') xlabel('Input voltage') ylabel('Output code') for i=1:512 inl (i)= -(out(i)-p(1)*in(i)-p(2));

end figure (4) plot(out(1:512),inl); title('Integral non-linearities') xlabel('Output code') ylabel('INL') end


52

Appendix B

This appendix contains VERILOG code for all data acquiring and processing such as

gathering of output bits for ADC etc.

B.1 Data Acquiring for ZCD Offset Calculation

include "constants.vams"

include "disciplines.vams"

module monte_carlo ( CLK, Vout, Vin);

input CLK;

input Vout;

input Vin;

electrical CLK;

electrical Vout;

electrical Vin;

integer fileDesc;

integer fileDesc1;

real sampling_CLK;

real sum;

real s;

real sampling_Vout;

real sampling_Vin;

analog

begin

@(initial_step)

begin

if (analysis("tran"))

begin

sum=0;

s=0;

fileDesc =$fopen("/vol0/scratch/saranovac/ydata.csv", "a");

fileDesc1=$fopen("/vol0/scratch/saranovac/xdata.csv", "a");

end

end


begin

sampling_CLK = V(CLK)-0.9;

@(cross(sampling_CLK, +1))

begin

s=s+1;

sampling_Vout = ( V(Vout) > 0.9) ? 1 : 0;

sampling_Vin = V(Vin);


53

$fstrobe(fileDesc1, sampling_Vin);

$fstrobe(fileDesc, sampling_Vout);

end

end

@(final_step)

begin


begin

$fstrobe(fileDesc, s);

$fclose(fileDesc);

$fclose(fileDesc1);

end

end

end

endmodule

B.2 Output Code Acquiring for 8 Bits Cyclic ADC

include "constants.vams"

include "disciplines.vams"

module Bits(D0, D1, CLK, Vin);

input D0;

input D1;

input CLK;

input Vin;

electrical D0, D1;

electrical CLK;

electrical Vin;

integer fileDesc;

integer fileDesc1;

integer i;

integer s;

real sampling_CLK;

integer sampling_D0 [0:7] ;

integer sampling_D1 [0:7] ;

real sampling_Vin;

real out;

integer sum [0:7];

integer C [0:8];

analog

begin

@(initial_step)


54

begin


begin

fileDesc =$fopen("/vol0/scratch/saranovac/sampled_8bits3.csv", "a");

fileDesc1 =$fopen("/vol0/scratch/saranovac/sampled_8in3.csv", "a");

end

s=0;

end


begin

sampling_CLK = V(CLK)-0.9;

@(cross(sampling_CLK, -1))

begin

if (s==0) sampling_Vin = V(Vin);

sampling_D0[s] = ( V(D0) > 0.9) ? 1 : 0;

sampling_D1[s] = ( V(D1) > 0.9) ? 1 : 0;

if (( V(D0) > 0.9) && ( V(D1) > 0.9)) sampling_D0[s] = 0;

s = s+1;

if (s==8)

begin

s = s-8;

C[8] = 0;

out = 0;

for (i=7; i >0; i = i - 1)

begin

sum [i] = sampling_D1[i] ^ sampling_D0[i-1] ^ C[i+1];

C[i]= (sampling_D1[i] & sampling_D0[i-1]) |

(C[i+1]&(sampling_D1[i] ^ sampling_D0[i-1]));

out = out + sum[i]*pow(2,7-i);

end

sum [0] = sampling_D1[0] ^ C[1];

out = out + sum[0]*pow(2,7);

$fstrobe(fileDesc, out);

$fstrobe(fileDesc1, sampling_Vin);

end

end

end

@(final_step)

begin


begin

$fclose(fileDesc);

$fclose(fileDesc1);

end

end

end

endmodule


55

Appendix C

This appendix contains explanation with intermediate steps for final equations given in text.

C.1 Chapter 2, Equation (2)

.

C.2 Chapter 3, Equation (5) and (6)


56

Appendix D

This appendix contains schematics of logic circuits for generation of control signals.

D.1 Logic for Generation of Control Signals E1 and E2

VO

2I

VOpulse

rising

edge

detector

S

R

Q

Q

2I

CKnReset

E1

pulse

rising

edge

detectorCK

VO

nReset

2I2


57

D.2 Logic for Generation of Phase Signals for Switches, 2(D1, D0)

P1

P2

P3

D1

D0

D0

D1

D1

D0

P1

P2

P3

f1n

f1n

f1n

f1n_P1

f1n_P2

f1n_P3

P1

P2

P3

f2n

f2n

f2n

f2n_P1'

f2n_P2'

f2n_P3'

P2

P3

f2n_P1'f2n_P1

P1

P3

f2n_P2' f2n_P2

P2

P1

f2n_P3' f2n_P3

Cyclic ADC based on a novel concept of Zero-Crossing … · Zero-Crossing Detection - Master Thesis...

Documents

Transcript of Cyclic ADC based on a novel concept of Zero-Crossing … · Zero-Crossing Detection - Master Thesis...