Cycle Based Simulation - Ensiwiki · 2015. 2. 13. · • UVM is a methodology for the functional...
Transcript of Cycle Based Simulation - Ensiwiki · 2015. 2. 13. · • UVM is a methodology for the functional...
-
Cycle Based SimulationDesign Techniques
-
Code Coverage / Cycle Based Simulation / Property Checking - ABV…
RTL Verification 2
Circuit Validation
Equivalence Checking
Acceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL Verification
TestbenchCode Coverage
Cycle-based simulationProperty Checking
-
Code Coverage / Cycle Based Simulation / Property Checking - ABV…
Cycle-based simulation 3
Circuit Validation
Equivalence Checking
Acceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL Verification
TestbenchCode Coverage
Cycle-based simulationProperty Checking
-
Code Coverage / Cycle Based Simulation / Property Checking - ABV…
Motivation… 4
How can I run faster simulations ?
-
Code Coverage / Cycle Based Simulation / Property Checking - ABV…
…Motivation…
• Concept:• “traditional software simulation” = event driven
• Cycle-based concept reduce the number of calculation
• Cycle-based simulation is no more a specific technique, it is automatically integrated in every simulation tool when usable
• Used at RTL level only
5
INPUT
CLOCK
OUTPUT
-
Code Coverage / Cycle Based Simulation / Property Checking - ABV…
Deliverables
• Cycle-based simulation in the verification flow
6
Event driven
Cycle-basedSanity check (triggers, constructs,
Combinational loops)
Faster simulationFirst trials
Acceleration Emulation
Event drivengate levelsimulation
Logic Synthesis
-
Universal Verification MethodologyDesign Verification Techniques
-
Verification Techniques / UVM / Property Checking - ABV…
Overview 2
Introduction
RTL Verification
Circuit Validation
Verification Platform
Static Timing Analysis
-
Verification Techniques / UVM / Property Checking - ABV…
A Global Methodology 3
Circuit Validation
Equivalence Checking
Acceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL Verification
TestbenchCode Coverage
Cycle-based simulationProperty Checking
-
Verification Techniques / UVM / Property Checking - ABV…
Motivation… 4
How can I put in place a reusable
solution of verification?
-
Verification Techniques / UVM / Property Checking - ABV…
Motivation
• What is simulation versus functional verification?
• Simulation is the process of adding test vectors into a model of the Design-Under-Test then observing how that model behaves
• A traditional test bench reads test vectors or commands from a file to change the values of the signals in the DUT over time, then dumps output from the DUT to compare versus expected. This process is limited and cannot support the reliable verification of very complex systems.
• An effective Verification Methodology is necessary!
5
-
Verification Techniques / UVM / Property Checking - ABV…
…Motivation…
• Definition:• UVM is a methodology for the functional verification of digital
hardware• UVM is explicitly simulation-oriented, but UVM can also be
used alongside assertion-based verification, hardware acceleration or emulation
• The hardware to be verified would be described using Verilog, SystemVerilog, VHDL or SystemC
• This could be behavioral, register transfer level, or gate level
6
-
Verification Techniques / UVM / Property Checking - ABV…
…Motivation…
• Objective:• A good verification methodology starts with a statement of
the function the DUT is intended to perform. From this is derived a Verification Plan
• UVM test benches are more than traditional test benches• UVM test benches are complete verification environments
composed of reusable verification components, and used as part of an overarching methodology of constrained random, coverage-driven, verification
7
Ref. Doulos web introduction on UVM
(http://www.doulos.com/knowhow/sysverilog/uvm/)
-
Verification Techniques / UVM / Property Checking - ABV…
…Environment• Objective:
• UVM is using a library of components with defined role to describe the DUT environment
8
Uvm_subscriber
Uvm_agent
Uvm_sequencer
Uvm_driver Uvm_monitor
Uvm_envt
DUT
Uvm_subscriber
Uvm_agent
Uvm_sequencer
Uvm_driverUvm_monitor
-
Verification Techniques / UVM / Property Checking - ABV…
Where in the Flow
• RTL = main usage
• RTL simulation = mandatory
• Gate level: reuse same verification environment
9
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
+ Parasitics
TestbenchWith UVM
-
Verification Techniques / UVM / Property Checking - ABV…
Technique
• UVM drives a dynamic technique that is based on a functional simulation
• This methodology includes code coverage in order to check the ‘design under test’ is well covered
• The UVM must reflect the functional design environment of the DUT and can be re-used at any step of the design
10
-
Verification Techniques / UVM / Property Checking - ABV…
Turning Simulation into Verification
• A good verification methodology starts with a statement of the function the DUT is intended to perform. From this is derived a verification plan
• Verification of complex systems must be automated. Along with the verification plan, automated checking, functional coverage and analysis are explicitly addressed by SystemVerilog and UVM.
• Checkers and functional coverage model take time to create but result in better quality of verification.
11
-
Verification Techniques / UVM / Property Checking - ABV…
Verification Process1. Start with classical directed tests to bring up the design
2. Move to fully random tests to explore the state space and flush out as many bugs as possible with minimum human effort devoted to test writing. This will typically achieve much less than 100% functional coverage
3. Define a series of tests, where constrains can shape the random stimulus to push the design into interesting corner cases. • Random stimulus alone is not enough to explore all the key use cases• Directed or highly constrained tests can be too narrow to give good overall
coverage• Constrained random stimulus is a compromise between the two extremes
12
-
Verification Techniques / UVM / Property Checking - ABV…
Checkers, …
• Constrained random verification relies on Checkers, Coverage and Constraints
• Automatic checkers ensure functional correctness
• Checkers can be implemented using SystemVerilogassertions or using regular procedural code.
• Assertions can be embedded within the design-under-test, placed on the external interfaces, or can be part of the verification environment (supported in UVM)
13
-
Verification Techniques / UVM / Property Checking - ABV…
…, Coverage ...
• Coverage provides a measure of the functional completeness of the testing, and tells you when the goals defined in the verification plan are met.
• SystemVerilog offers two mechanisms for coverage:• property-based coverage (cover directives) • sample-based coverage (cover groups). • The specification and execution of the coverage model is tied to
the verification plan, annotated by simulation tools
14
-
Verification Techniques / UVM / Property Checking - ABV…
… and Constraints
• Constraints provide the means to reach coverage goals by shaping the random stimulus to push the DUT into interesting corner cases.
• Constrained random stimulus is still random, but the statistical distribution of the vectors is shaped to ensure the DUT is pushed into those interesting corner cases.
• SystemVerilog offers dedicated features for expressing constraints, when UVM provides mechanisms that allow constraints to be part of a test rather then embedded within verification components.
15
-
Verification Techniques / UVM / Property Checking - ABV…
Verification Reuse• UVM facilitates the construction of verification environments (VE), by
providing reusable components within a library of SystemVerilogclasses, and by providing a set of guidelines for best practice
• Verification productivity is enhanced by reuse. UVM enable it by:• Having a modular VE where each component is clearly defined, • Allowing flexibility since each components are configured and used, • Allowing imported components to be customized to the application,• Having well-defined coding guidelines to ensure consistency.
• Verification components at all layers can be reused in different environments. Low-level driver and monitor components can be reused across multiple DUT. The whole verification environment can be configured top-down by multiple tests
16
-
Verification Techniques / UVM / Property Checking - ABV…
Test sequence• UVM is based on OVM (Open-source Verif Method), using system-
verilog language (structure close to verilog)
• A Verification Environment sequence:
17
Define the different steps in systemV
- Interface to the design-under-test - Design-under-test (or DUT) - Verification environment (or test bench) - Transaction - Sequencer (stimulus generator) - Driver - Top-level of verification environment - Instantiation of sequencer and driver - Top-level module - Instantiation of interface, DUT, Test (which
instantiates the verification environment)- Process to run the test
-
Verification Techniques / UVM / Property Checking - ABV…
Inputs
• Design Under Test (DUT)
• Key signal drivers (clocks, resets)
• Components (models)
• Test (=stimuli vectors)
18
-
Verification Techniques / UVM / Property Checking - ABV…
Inputs: DUT…
• Design Under Test (DUT)
• RTL/gate description (VHDL , Verilog)
• Same code as for synthesis (except for hard blocks where a model for simulation should be provided)
• The hardware to be verified can be described using Verilog, SystemVerilog, VHDL or SystemC
• It can be behavioral, register transfer level, or gate level. • UVM is based on system-verilog languages
19
-
Verification Techniques / UVM / Property Checking - ABV…
Limitations…
• Same as TB with less restriction
• Exhaustive tests do not exist! …• UVM includes random test to increase coverage
20
-
Verification Techniques / UVM / Property Checking - ABV…
Automated Verification 21Verification Environment
AutomaticStimulus
GenerationData and AssertionCheckers
Physical Layer
Device
CoverageMonitor
StimulusScenarios
stimulusScenarios
StimulusScenarios
Generation Self Checking
Coverage
-
Verification Techniques / UVM / Property Checking - ABV…
Tools…
• Same as TestBench!
• Classical functional simulators (Ncsim, Questa, Vcs…)
• Language: systemVerilog• Object language• Mixed of classes (software, dynamic object) and module
(hardware component, hierarchy)
22
-
Verification Techniques / UVM / Property Checking - ABV…
Deliverables
• Same as TB!
• Result of the test• Should clearly state the passing test cases and the failing ones (if
any and why!)• Coverage report to deliver as an evidence for test completeness
• Sign-off criterion• Execution of test cases on RTL and gate with no difference
• Good verification = high coverage with no test failing
23
-
Property Checking - ABVDesign Verification Techniques
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
RTL Verification 2
Circuit Validation
Equivalence Checking
Acceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL Verification
TestbenchCode Coverage
Cycle-based simulationProperty Checking
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Assertion Based Verification 3
Circuit Validation
Equivalence Checking
Acceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL Verification
TestbenchCode Coverage
Property CheckingCycle-based simulation
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Motivation… 4
of How can I ensure properties of my design are valid under all
circumstances ?
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
…Motivation…
• Property
• Expected behavior of a circuit based on existing specifications
• Safety: a condition that is always true or false• Liveness: a condition that must happen regardless of timing
• A property sometimes is hard to prove with simulation• e.g. bus arbiter managing many masters -> heavy TB!
5
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
…Motivation…
• Under all circumstances
• The verification should ensure the property would never violate, regardless of any stimulus
• Assertion technique is use to describe the property then check this property is correctly applied in the circuit
• Property Checking uses the Assertion Based Verification technique (ABV)
6
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Why assertions ?
• Assertions can find ‘hard to find’ bugs (deep in the design)
• Reduce debug time: assertions are very close to the root of bugs and stop on error
• Improve re-use by communicating design intent (embedded in IP)
• Travel with the design (executable specification)
• Improve verification efficiency• Increase debugging productivity• assertions are “alive” all the time• Could be tool independent : both static and dynamic
7
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
…Motivation
• Protocol compliancy• “A grant must be generated at max 3 cycles after a request is
asserted”
• Operation• “CPU_READ and CPU_WRITE must never be asserted at the
same time”
• Design quality• “all flip-flop can be reset”• “no flip-flop get stuck”• “an enumerated signal goes through all values”
8
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Where in the Flow 9
Micro-architecture:to check the behavior(mainly protocols)RTL = main target(operation or design quality)
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Micro-Architecture
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Inputs…
• Design• model for micro-architecture (usually C language)• RTL (written in hdl)
• Assumptions about the design environment• To limit the set of admissible sequences, the strategy is to
specify valid operation mode:• “X and Y are never asserted at the same time”• “once a request has been asserter, no other request is
asserted before a grand is asserted”
10
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
…Properties
• Properties to check• Signals in property are those seen in the architecture document or
at the block boundary• The verification plan should include:
• The properties & environment in natural language• Property: “Req persists until ack is asserted”• Environment: “Ack is asserted one cycle after req”
• The properties & environment in the tool language• PSL (Property Specification Language)• SVA (System Verilog Assertion)
11
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Assertion Based Verification Technique
• ABV can be a Dynamic verification• Property is verified during a simulation• Overhead during simulation
• Or a Static verification = model checking• Exhaustive and semi-exhaustive formal property checking• No need to provide stimuli
12
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Technique
• Property checking process: Assertion• Describe the environment and the properties to be checked
(can/should be done before the DUT!)• The tool determines whether a property holds under the adopted
assumptions• If a property is violated, a counterexample is automatically
generated by the tool• Different languages are involved for DUT, environment, property
and tool
13
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Technique
• How to define an Assertion• If constraints are too strong, a misbehaviour can be missed (false
positive)• If constraints are too weak, non-significant misbehaviours can be
spotted out (false negative)
14
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Who should write assertions ?
• Architect• Transitions
• Verification Engineer• “Black-box” assertions: interface• Use of separate assertions to verify protocols or “interface”
assertions
• Designer• “White-Box” assertions, prefer inline assertions• Comment assumptions on the interface and ensure they will be
fulfilled when integrated• Verify some implementation invariants
15
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Assertion Languages• Many languages exist today:
• VHDL – assert statement• Only combinational
• OVL (Open Verification Library)• Very simple, but not powerful
• PSL (IEEE1800 - Property Specification Language)• OVA• SVA• HVL like e
• No static tools, running during TB simulation• Others proprietary languages
• Tools specific (PEC, HPL, ITL…)
16
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Using existing HDL functionality• VHDL – assert statement
assert a= b) begin$display(“error: a must be smaller than b”;$finish;end
end
• Pros• Use of existing language and tools
• Cons• No temporal expressions ; limited to Boolean logic only
17
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Limitations• RTL coding style for property checking
• No unstable combinational loops• Tri-state signals can be a problem• Deep FIFO makes issues:
• Strategy is to use shallow FIFO for debug purpose• An easy way to do that: declare FIFO size as a top level constant• The FIFO can be verified separately and then replaced by a black-box
• Design size limit:• Block-level• Property checking is CPU (fixed point) and Memory intensive task
18
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Tool
• RuleBase (IBM)• Historical tool on the market • Still leading edge technology…
• Many EDA tools today• Magellan (Snps), IFV (Cadence Incisive), 0-in (Mentor)• A lot of start-up
19
-
Cycle Based Simulation / Property Checking – ABV / Equivalence Checking …
Deliverables
• The implementation report should state• Property has been fully checked and passes• Property has been checked under certain restrictions and passes• Property is known to fail under specified conditions
• Note:• design may be correct for a given implementation. Violation
conditions may be used in other systems
20
-
Equivalence CheckingDesign Verification Techniques
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Overview 2
Introduction
RTL Verification
Circuit Validation
Verification Platform
Static Timing Analysis
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Circuit Validation 3
Verification PlatformAcceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Circuit Validation
Equivalence Checking
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Equivalence Checking 4
Verification PlatformAcceleration
Emulation FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Circuit Validation
Equivalence Checking
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Motivation… 5
How can I prove that my two netlists keep the same
functionality ?
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Motivation• Goal
• To check a new implementation step preserves the functionality, fastest than a full simulation
• Advantage:• Equivalence is ensured whatever the stimuli are• Equivalence is an exhaustive technique
• Example• Compare two different implementations of the same architecture• Compare two successive releases of the same design• Compare between two steps of implementation along the flow
6
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Where in the Flow… 7
Equivalence Checking (EC) can be performed between:
RTL vs RTLRTL vs gateGate vs gate(the fastest and most used verification)
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
+ Parasitics
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Where in the Flow…
• RTL sign-off flow• Effort is put on the RTL simulation (the reference)• EC is then used to prove the netlist after synthesis, place and
route behaves the same
8
RTL Gate1(hierarchical)Gate2(flat)
Equivalence Checking Equivalence Checking
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Where in the Flow
• Validation after every design modification• RTL optimization, scan chain or clock tree insertion, timing
optimization: EC can prove the function remain unchanged
• Design Migration• EC is a fast way to compare two designs mapped on two different
libraries
9
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Inputs• Design (HDL)
• Recommendation: keep the reference structure (hierarchy, naming scheme) for implementation to speed up the process
• Assumptions• To limit the exploration space and speed up the process (e.g test
mode disabled to avoid discrepancies on the scan chain)
• Name mapping• If name changed for the same functionality, provide a mapping file
that allows EC to retrieve the points to compare
10
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Technique
• Equivalence Checking is a static mode verification
• No stimuli are required
• That make an exhaustive verification of the whole design
• EC does not check the functionality versus the specification
• The goal is to insure the functionality does not change between to design descriptions
11
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Technique…
• Comparison• Made on memory points (flip-flop, latches, memories) and the
output of both designs• The logic cones ending to these points are compared
12
Netlist A
Netlist B Logic equivalenceNot Gate equivalence!
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Technique
• Checking result• Pass implementation matches the reference• Fail implementation is different (function)
• Tool provides vectors to prove the difference• Abort runtime or memory capacity overflow or too difficult to
compare
• Check is:• successful if all compare points passes• Partially successful if pass or abort only
13
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Limitations…
• RTL coding style for equivalence checking• No combinational loops• No bus keeper for maximum efficiency
• Design complexity• Strategy: to perform hierarchical verification (check low level
blocks, black-box, go to upper level…)
14
Run TimeMemory
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Limitations…
• Retiming• EC is a combinational process. Thus the designs must match from
a sequential point of view• Some basic retiming is admissible
15
+
+ x
- + -
x+VS
Clock cycle boundary
-
Property Checking – ABV / Equivalence Checking / Acceleration …
…Limitations
• Netlist sign-off• EC must be completed with Static Timing Analysis
• In some cases (reset, combinational loops, non synchronism), the gate level simulation remains mandatory
16
Netlist A
Netlist B +Clock period = 5 ns
Arc1Arc2
Equivalence Checking Static Timing Analysis
=Simulation
~
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Tools
• Cadence Conformal LEC
• Synopsys Formality
• Some other EDA tools
17
-
Property Checking – ABV / Equivalence Checking / Acceleration …
Deliverables• Documentation
• Views checked (RTL, gate) and the result• Views partially checked
• e.g memory, transistor view,• e.g assumptions used to achieve EC and methods to prove those
assumptions (e.g. test enable)• Memory/CPU usage: to reproduce the run
• Scripting:• List of compare points + compare points removed because known
to be different
18
-
AccelerationDesign Verification Techniques
-
Equivalence Checking / Acceleration / Emulation …
Overview 2
Introduction
RTL Verification
Circuit Validation
Verification Platform Static Timing Analysis
-
Equivalence Checking / Acceleration / Emulation …
Verification Platform 3
Circuit Validation
Equivalence Checking
FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Verification Platform
AccelerationEmulation
-
Equivalence Checking / Acceleration / Emulation …
Acceleration 4
Circuit Validation
Equivalence Checking
FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Verification Platform
AccelerationEmulation
-
Equivalence Checking / Acceleration / Emulation …
Motivation… 5
Man!This simulation lasts forever…
How can I simulate faster ?
-
Equivalence Checking / Acceleration / Emulation …
…Motivation• Goal
• Improve Software simulation run time which is too slow for today chips
• reach higher simulation cycles/s using Acceleration
• Performances• Software simulation: ~100 cycle/s• Accelerated simulation: ~3000 cycle/s
Note: cycle/s = simulation cycle/clock wall second
6
-
Equivalence Checking / Acceleration / Emulation …
Where in the Flow 7
Anytime the design has reached a minimum maturity(netlist is roughly stable)
Targets:– RTL– Gate level
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
-
Equivalence Checking / Acceleration / Emulation …
Inputs• Design:
• RTL/gate level• A sub-system or the whole DUT is mapped onto the acceleration
box • Memories are usually mapped onto physical on-accelerator
memories
• TestBench and test• The same TB and stimuli as for classical simulation• If TB is synthesizable can be mapped too (emulation)
8
-
Equivalence Checking / Acceleration / Emulation …
Technique: Principle…
• Acceleration implements the software simulation kernel on dedicated hardware (CPU + memories, FPGA,…)
• Simulation is then run on a workstation connected to hardware boxes
9
Software simulation
Acceleration
Triggers:-process P_1 (a,b)=> z-Process clock (every 10ns)-…-Process alu (opcond, z)=> accu
-
Equivalence Checking / Acceleration / Emulation …
…Technique…
• Accelerating the design
10
MA
PP
ING
If (a=‘1’) thenZ
-
Equivalence Checking / Acceleration / Emulation …
…Technique: Usage…
• Simulation speed-up (2X – 20X)
• Non regression tests• Acceleration is used to prove that a new netlist behaves as the
previous release throughout long test sequences
• Toggle count• Acceleration is used to count the flip-flop toggle (hence the
coverage at gate level)
• Manufacturing Tests• Accelerating ATPG vectors (very long sequences)
11
-
Equivalence Checking / Acceleration / Emulation …
…Technique: Usage…
• Interesting tests with acceleration• Reset and clock generator
• To ensure the validity of these critical blocks that cannot be verified outside of simulation
• Debug port verification• To ensure the TAP controller
can control and observe everything required for test
12
TAP
-
Equivalence Checking / Acceleration / Emulation …
Limitations…
• RTL coding for acceleration• X, U and Z states are supported• Metastability should be handled properly at design level
(synchronization stage)• Asynchronous designs simulate poorly: gated clock may introduce
skew problems hard to solve
13
data
clock
enable
-
Equivalence Checking / Acceleration / Emulation …
…Limitations…
• RTL coding for acceleration• Behavioral RTL cannot be accelerated (not synthesizable)• Testbench should be synthesizable for maximum efficiency
(emulation)
14
Accelerator
Testbench Triggers:
-Process clock (every 10ns)-Process reset(after 100 ns)-Process tb (read file) => a API link
-
Equivalence Checking / Acceleration / Emulation …
…Limitations…• Debug cycle
• Any change in the design requires a re-mapping on the accelerator• Debugging is not so easy as in software simulation• Acceleration should be used whenever the design has reached a
minimum maturity
• Acceleration box capabilities• Number of I/O• On-board Memory Size• Gate count
15
-
Equivalence Checking / Acceleration / Emulation …
Tools
• Example: AXIS (without back-annotation)
• Capacity• Up to 8 boards of 448k cells + 32MByte memory
16
300k300k300k300k300k300k300k300k448k
+ 32 Mbyte memory
1 single huge design(2.5 Mcells)
OR
448k 448k 448k
448k
448k448k448k
448k
8 smaller designs in parallel
+ 32 Mbmemory
-
Equivalence Checking / Acceleration / Emulation …
Deliverables
• The same as for simulation
• Report on test completeness:
• Table of failing/passing test cases
• Toggle count for flip-flops (optional)
17
-
EmulationDesign Verification Techniques
-
Acceleration / Emulation / Stating Timing Analysis…
Verification Platform 2
Circuit Validation
Equivalence Checking
FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Verification Platform
AccelerationEmulation
-
Acceleration / Emulation / Stating Timing Analysis…
Emulation 3
Circuit Validation
Equivalence Checking
FunctionalVerification
TemporalVerification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
Verification Platform
AccelerationEmulation
-
Acceleration / Emulation / Stating Timing Analysis…
Motivation… 4
How can I ensure the design will be working in the context
of the real system ?
-
Acceleration / Emulation / Stating Timing Analysis…
…Motivation…
Goals
• Hardware checks: functional verification• to ensure the hardware is interacting correctly with the actual
application with all nets debug capability• Accuracy: the testbench is the actual application!
• Software / Hardware Co-simulation• To offer a software development platform before the silicon is
ready
• Run Time: Fast!• Up to 1 M cycle/s
5
-
Acceleration / Emulation / Stating Timing Analysis…
…Motivation
• Platform example: a video coding/decodingsystem
6
Display
User interface:-Host program loading-Stimuli provider (data in)-Checker (data out)
Host board:-Host CPU tocontrol the chip
Emulator:-The design ismapped here
Camera
Interface:-Actual devices
-
Acceleration / Emulation / Stating Timing Analysis…
Where in the Flow… 7
RTL Level: design synthesis is handled by emulation tool
Gate level: a “translation” library must be provided GTECH (Synopsys) CORELIB (ST) Others
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
+ Parasitics
-
Acceleration / Emulation / Stating Timing Analysis…
Inputs
• Design• A minimum maturity is required
• fine debug on the emulator is hard to conduct• Mapping onto the emulator is not an easy task: it does takes time
(several hours for a typical design)
• Planning• Long and complex task to map a design onto the emulator.
Verification engineer is required!• Some physical environment must be built
8
-
Acceleration / Emulation / Stating Timing Analysis…
Technique…• Principle
• Dynamique technique as Simulation• Emulator = sea of programmable devices (FPGA)
• Evolution: mapping of the gate on processors (Palladium)
9
If (a=‘1’) thenZ
-
Acceleration / Emulation / Stating Timing Analysis…
…Technique
• Modes of operation• In-circuit: good coverage
• emulator connected to the actual application platform• Non-regression: easy debug
• “Accelerated platform” Everything (including TB) is mapped onto the emulator. Speed is higher but the TB must be often simplified (less coverage)
• Co-emulation: fast simulation• When the TB is not synthesizable, emulator (as accelerator with a
simulator) can co-emulate with an external TB. It offers a very fast simulation
10
-
Acceleration / Emulation / Stating Timing Analysis…
Limitations…
• Cost• Price: up to 1 M US$• Less shareable than a SW simulator (but under continuous
improvement)• Time: expertise to map and drive the emulator
• Signals• 2-state (0,1) behavior only
11
-
Acceleration / Emulation / Stating Timing Analysis…
…Limitations
• RTL coding for emulation• Memories are mapped to their emulation model
• Need to write specific memory models• Non-synthesizable constructs are not supported
• e.g. absolute time construct (pulse, delay)• Signals crossing clock domains
• must always be re-synchronized• Clock gating limited to “clean” gating (and-like)• No X,U propagation in emulation• Z is supported (must be resolved)• All flip-flops must be controllable by reset
12
-
Acceleration / Emulation / Stating Timing Analysis…Tool
• Old: Mentor Celaro (until 2002)
• Up to 192 slots for 6M gates• 128Mbyte memory (SRAM)• Shareable: up to 4 designs in
parallel• Speed: up to 1 M cycle/s• Size: up to 8 m3, 2.5 Tons
• Cadence Palladium• 16 M gates on 8 Gbytes
memory• Shareable: up to 16 designs
in parallel• Speed up to 1.8 M cycles/s• Size: 1.4 m3 , 500 kg
• Mentor Veloce (2007) • 16 M gates on 1 Gbytes
memory per user• Shareable: up to 4 users in
parallel (128MG/8GB)• Speed up to 1.5 M cycles/s• Size: 1.3 m3 , ~450 kg
13
-
Acceleration / Emulation / Stating Timing Analysis…
Deliverables
• The same as for simulation!
14
-
Acceleration / Emulation / Stating Timing Analysis…
Prototyping
Goal:
• MAIN: early SW development - Validation• To offer a SW development platform before the silicon is ready in
order to debug the final application• The testbench can be the actual application!
• HW/SW• HW debugging is still possible (minor refinement)
• Speed:• Up to 30 M cycle/s
15
-
Acceleration / Emulation / Stating Timing Analysis…
…Prototyping
• Platform example: an ARM7/Entry Level Navigation Project
16
User interface:-Host program loading-RTOS (Nucleus)-SW Drivers
Prototyping Platform
ARM Integrator(ARM7TDMI)
The ASIC ismapped onto FPGAs
I2S Audio
CDROM Drive
LCD Display
SRAM and SDRAMonto custom boards
-
Acceleration / Emulation / Stating Timing Analysis…
Limitations…
• Cost• Price: ~$US 400K
• Need for external equipments: LSA, Oscilloscope, Clock and Pattern Generator, …
• Not sharable as a SW simulator• Time: expertise to map and drive the tool
• Debug Environment• Poor visibility of internal nodes• Observation nodes are decided at mapping time• Limit = number of I/O, resources to make a node observable
17
-
Acceleration / Emulation / Stating Timing Analysis…
Tool
• Aptix MP3/MP4• Up to 8 Mgates (10 Xilinx Virtex2V8000)• Up to 10k visible nets at a time• Custom Modules
• Aptix: SRAM, SDRAM, DPRAM, Integrator I/F, …• Replicas available, Speed: up to 30 M cycle/s
• ProDesign (Platinium)
• Eve (Zebu)
• …
18
-
Acceleration / Emulation / Stating Timing Analysis…
Emulation vs Prototyping
• Emulation• Easy to map a design (1 week) but request a good expertise of the
tool (expert)• Easy for debug• Available for huge design
• Prototyping• High Speed simulation• Long to map (1 to 3 months)• More for early SW development than design validation
19
-
Static Timing AnalysisDesign Verification Techniques
-
Emulation / Stating Timing Analysis / Conclusion …
Overview 2
Introduction
RTL Verification
Circuit Validation
Verification Platform
Static Timing Analysis
-
Emulation / Stating Timing Analysis / Conclusion …
Temporal Verification 3
Circuit Validation
Equivalence Checking
Verification PlatformAcceleration
Emulation FunctionalVerification
Temporal Verification
Static Timing Analysis
RTL VerificationTestbenchCoverageProperty Checking
-
Emulation / Stating Timing Analysis / Conclusion …
Motivation… 4
How can I ensure my design will work
at the target frequency under all
circumstances ?
-
Emulation / Stating Timing Analysis / Conclusion …
Motivation• Goal:
• To check the design will reach the expected timing performances
• How:• By ensuring any timing path meets the timing requirements• Warning: STA does not check functionality!
5
-
Emulation / Stating Timing Analysis / Conclusion …
Motivation
• Concept• Check the data are available at the right time around the clock
edge signal through static timing calculation
6
INPUT
CLOCK
OUTPUT
CLOCK
INPUT
SETUPHOLD
-
Emulation / Stating Timing Analysis / Conclusion …
Where in the Flow… 7
Pre layout gate level:to set up the timing environment
Post layout gate level:main target
Synthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
+ Parasitics
-
Emulation / Stating Timing Analysis / Conclusion …
…Where in the Flow
• Pre layout accuracy
• Post layout accuracy
8
Statistics based(Wire Load Model)
R,C = f(Area)
R,C = extractedfrom layout
-
Emulation / Stating Timing Analysis / Conclusion …
Inputs…
• Design• Gate level (Verilog, EDIF, VHDL)• Analog blocks, memories have their own timing model
• Timing Annotation• Gate and/or wire annotation
• As extracted from Place & Route• Or as estimated in pre-layout analysis
9
R1 C1 R2 C2
-
Emulation / Stating Timing Analysis / Conclusion …
…Inputs…
• Design constraints• Environment
10
Driving cell
Input transition
Load
Operating conditions
DSPFSDF
-
Emulation / Stating Timing Analysis / Conclusion …
…Inputs…
• Design constraints• About environment
11
Process
Quantifies the manufacturing dispersion(oxide & metal thickness, …)
Voltage
Temperature
Timing model for devices (transistors,…) is available for a range of voltage supply
Timing model for devices (transistors,…) is available for a range of temperature
-
Emulation / Stating Timing Analysis / Conclusion …
…Inputs
• Design Constraints• Timing Constraints
12
Combo Logic
Combo Logic Combo Logic Combo Logic
Clock period, waveform and phase shift
Arrival Time Departure Time
-
Emulation / Stating Timing Analysis / Conclusion …
Technique
• Static Timing Analysis is a static technique, no stimuli are required
• STA insures the timing performances are reached on the functional design
• Note: The goal is NOT to check the functionality of the design: it must be associated with a verification technique to insure the full verification
13
STA + EQ Check ~ TB simulation(static) (static) (dynamique)[Timing] + [No change on function] = OK!
-
Emulation / Stating Timing Analysis / Conclusion …
Technique: Delay Calculation…
• For gate level designs
14
Input transitionOutput capacitance
0.4 ns
A Z
" 0.04046, 0.15501, 0.40826, 0.53434",
"0.04465, 0.15978, 0.41281, 0.67763",
"0.10748, 0.26067, 0.51005, 0.76346",
"0.16294, 0.42466, 0.73709, 1.04356",
"0.17673, 0.43920, 0.87670, 1.23678
library.lib (STF)" 0.04046, 0.15501, 0.40826, 0.78816",
"0.04465, 0.15978, 0.41281, 0.79198",
"0.10748, 0.26067, 0.51005, 0.88492",
"0.16294, 0.42466, 0.73709, 1.10670",
"0.20836, 0.55820, 0.99390, 1.42270
Library (characterization)
0.09 pF
Inpu
t tra
nsiti
on
Output capacitance
Transition = 0.78773 ns
Delay = 0.51005 ns
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Delay Calculation…
• For custom blocks (analog, memories)• Using timing models
15
Min, Max timing
CLOCK
Setup, hold time Access time
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Block Level…
• Goal: • check any timing path is within the constraints (min < TPath < max)
• Timing path
16
Combo Logic
Input port Output port
Clock pin of asequential device
Data pin of asequential device
Start Point End Point
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Block Level…
• Clock management
17
Clock pin
Tdelay
skewFFx
FFy
Transition at the end points
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Issuing reports…
• DRC issues• Timing values reported by the tool are reliable if transition and
capacitance are within the maximum used for library characterization
18
library.lib (STF)" 0.04046, 0.15501, 0.40826, 0.78816",
"0.04465, 0.15978, 0.41281, 0.79198",
"0.10748, 0.26067, 0.51005, 0.88492",
"0.16294, 0.42466, 0.73709, 1.10670",
"0.20836, 0.55820, 0.99390, 1.42270
Library (characterization)
Inpu
t tra
nsiti
on
Output capacitance
0.93709
Max capacitance violation
1.00274 Max transition violation
Manufacturing yield
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Issuing Reports…
• Coverage
Type of Check Total Met Violated Untested---------------------------------------------------------------------setup 3119 1176 ( 38%) 9 ( 1%) 1934 ( 62%)hold 3120 1168 ( 37%) 17 ( 3%) 1935 ( 62%)
...--------------------------------------------------------------------All Checks 11379 6753 ( 59%) 40 ( 7%) 4586 ( 34%)
19
May be due to:
- Environment assumption (e.g. report done in functional mode)- Design constructs (e.g. combinational loops cannot be verified)
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique:Top level…
• Hierarchical analysis is based on timing models for blocks• Timing model may be extracted from the netlist• Or “carved” netlist may be used
20
Combo Logic
Combo Logic Combo Logic
Internal paths are removed
-
Emulation / Stating Timing Analysis / Conclusion …
…Technique: Top Level
• Clock tree impact at top level• Clock tree balancing
between blocks, IPscan be checkedonly at top level
21
Block 1Clock tree depth = 1.3 ns
IPClock tree depth = 0.7 ns
PAD
-
Emulation / Stating Timing Analysis / Conclusion …
Limitations…
• RTL coding for Static Timing Analysis• Asynchronous constructs cannot be verified
• Asynchronous inputs• Paths between asynchronous clock domains• Combinational loops
22
-
Emulation / Stating Timing Analysis / Conclusion …
…Limitations
• Accuracy of timing models• Need a continuous improvement in the accuracy of timing
models at standard cell level! (from linear -> NLDM -> CCS)• Need a strong verification of timing model at block or IP level
(ILM models)
• Runtime• More than 1 day for flat chip level analysis• Can be done in a hierarchical mode (if accurate models!)
• Note: always fastest than a simulation!
23
-
Emulation / Stating Timing Analysis / Conclusion …
Tools
• Primetime (Synopsys)• Accuracy proven versus transistor level timing analyzers• Chip level capability (timing models management)• Runtime: more than 1 day for large chips
24
-
Emulation / Stating Timing Analysis / Conclusion …
Deliverables
• Reports• Max capacitance, transition• Coverage: including details about the untested nodes• Clock skews all over the chip
25
-
ConclusionDesign Verification Techniques
-
Stating Timing Analysis / Conclusion …
Training Objective
• At the end of this class you are able to :
• Understand what is a Functional Verification• What is the basic taxonomy of functional verification• Discover the different Verification Techniques with a list of tools
and languages• Understand how to apply Vtechniques on a design
• Understand what is a temporal verification and the link with the functional verification
2
-
Stating Timing Analysis / Conclusion …
Verification in the Design Flow 3
Acceleration
Emulation
PrototypingSynthesis
Floorplan
Place & Route
Extraction
RTL Entry
Gate Level Netlist(Pre layout)
Gate Level Netlist(Post layout)
+ Parasitics
Layout
Architecture
Transistor
Testbench Coverage
Property Checking
Equivalence Checking
Static Timing Analysis
Equivalence Checking
-Architecture
-
Stating Timing Analysis / Conclusion …
People involved in Verification 4
Architect- chip analysis- block partitioning- detailed specifications
Designer (HW, SW)- block description (C, HDL)- block synthesis (Ass, Gate)- block validation (Simulation,Timing)- block implementation (P&R)- block verification (LVS, DRC)
Block & IP Integrator-chip assembly- chip verification vs spec
Verification Engineer- coverage driven verification- emulation- acceleration- equivalence checking- ABV (property checking, ..)
CAD Support- CAD tools, flow- Training
- simulation, acceleration- ABV - equivalence checking- Static Timing Analysis
-
Stating Timing Analysis / Conclusion …
5