Cutting Power Consumption in HDD Electronics9 HDD Performance Impacting Power Consumption zHDD...

Cutting Power Consumption in HDD Electronics

Duncan Furness

Senior Product Manager

2

Situation Overview

The industry continues to drive to lower power solutions• Driven by:

— Need for higher reliability— Extended battery life for mobile and handheld devices

• Performance requirements continue to increase

Being competitive requires IP directed at reducing power consumption• Process shrink is an enabler, but not the driver

• Innovations focused in two key pieces of IP— Read channels— Serial interface

3

Storage IC Technology Explained

VCM

Disk Platter

SpindleMotor

PreampPreampInterfaceController Read

Channel

Read/Write Head

HardDisk

Controller MotorController

MotorController

System on a Chip (SoC)

Memory

Host

ExternalMemory

4

Sample HDD Power Budget

Roughly ½ the budget is electronics• A large opportunity for improving power savings

SoC

Power

PA SpinUp

SteadyStateSpin

Seek

Electromechanical

And MechanicalElectronics

5

Reliability Driver

With higher data rates, increasing the power in a given form factor increases temperature

• Decreases inherent electronics reliability— Failure rate is exponential

with temp

• Results in a rich system failure pareto— head / disk failures in the

system– …

Semi Failure vs Junction Temp

Junction Temperature

Failu

re R

ate

Dec

reas

e

Power

(T)

λ~exp(ФKT)

Decreasing power (temperature) improves reliability

6

Extending Battery LifeMajor factor in handheld devices

• Translates into extended ‘live-time’

In order to minimize storage power the host utilizes a data buffer:

• Reduces on-time of HDD

With advent of video:• Battery ‘live-time’

expectation set from audio— Reduce power dramatically

and/or— Increase buffer size –costs

more

Must reduce storage power and operate at low battery voltage

2.7V

4.2V

Operation time

Full charged

0

CF 3.0V

A Consumer Electronicsproducts battery voltage characteristics example

DRAM Buffer

HDD

Native Speed

Application Speed

MP3or

MPEGFAST SLOW

7

Process-Enabled Power Reduction

Reduction in operating power through process shrink:• Dynamic power shrinks with process

— Applies to digital logic

— Analog doesn’t scale

• Resulting mixed signal power reduction is less.

Dynamic Power = C V2 f

’01-’04 ’04-’06 ’06-’09

130 nm 90 nm 65 nm

• Additional wrinkle:—Leakage current increases with

process shrink

—With finer geometries, leakage becomes more significant.

Dynamic Power

Leakage Power

8

Handheld Device Challenge

Leakage power is an important aspect of battery-operated handheld devices

• Standby mode needs extremely low power

Requires higher threshold devices

• Thresholds required for 65 nm are high, requiring a high core voltage

Cannot take full advantage of:

• (Core Voltage)2 related power reduction

Drives the need for innovation in:

• Process

• Architecture

• Implementation

9

HDD Performance Impacting Power Consumption

HDD transfer rates driven by density increases:• Every double of capacity results in:

~1.4X transfer rate

~1.4X number of servo fields

• Results in channel clocks scaling proportionally and processor speed requirements increasing.

Areal Density

1990 1992 1994 1996 1998 2000 2002 2004

60% CAGR10

0% C

AGR

Driving towards increased ECC capabilities• Results in more area/logic.

All of these increase power…

40%

CAGR

10

Power Solutions –Read Channel

New 90 nanometer read channel designs offer 70 percent power reduction over 130 nm

The IP improvements are architectural in scope across all product segments

Power optimization must preserve signal-to-noise ratio performance

100%

30%

130nm 90nm

-55% Intellectual Property

-15% Process Shrink

Next Gen

Relative Power

11

Serial Interface Adoption Impacting Power Consumption

Seeing adoption of High-speed SATA interface across product segments:• Used widely in desktop drives

— Desktop is converging on 3 Gb/s

• Transitioning to the mobile market — ~1 year behind desktop— Mobile will probably hold at 1.5 Gb/s for the near term due

to power sensitivity

• Enterprise will spearhead 6 Gb/s on SAS (~2008)

Most significant power consuming block is the Physical Layer Interface block (PHY)

Data rates are moving higher, so how can we maintain or reduce power budgets?

PowerPerformance

Area

Pin count

12

Power Solutions -Serial Interface PHYRelative Power

100%

60%

-30% Intellectual Property

-10% Process Shrink

Next Gen

90nm130nm

New 90 nm serial PHY’s offering 40 percent power reduction over 130 nm design

Still able to produce performance improvements (6 Gb/s)

13

Summary –Mixed Signal Power

Increasing Performance requirements, Reliability and Battery live-time push the need for power reduction.

Mixed signal analog power improvements are best addressed by design innovation.• Target architectural improvements to span product

segments

HDD silicon and system manufacturers will continue to be challenged to reduce or maintain power.• Be aligned with a silicon provider producing the necessary

innovation.

IDEMAAdvances in HDD Electronics

IDEMAAdvances in HDD Electronics

Dave MosleyVP – Emerging Products DevelopmentDave MosleyVP – Emerging Products Development

December, 2005December, 2005

© Seagate ConfidentialIDEMADecember 2005

1997 2001 2005 Beyond

DR

AM

Flash

Read Channel

Servo & Spindle Control

VoltageRegulators

Interface

uProcessor

Formatter

Interface Block

Buffer

Manager SR

AM

Glue

Logic

DRAM

Servo & Spindle

Control + Volt. Regs

Interface

uProcessor

Formatter

Interface Block

Buffer Manager

SRAM

ReadChannel

Glue

Logic

Servo & Spindle Control +

Voltage Regs

Interface

uProcessor

Formatter

Interface Block

Buffer M

anager

SRA

M

ReadChannel

Glue

Logic

DR

AM

A multitude of technologies A multitude of technologies have been used to enable have been used to enable dramatic reductions in the dramatic reductions in the

footprint and power of HDD footprint and power of HDD electronics!electronics!

DR

AM

Flash

Read Channel


VoltageRegulators

Interface

Formatter

Glue

Logic

uProcessor

Interface Block

Buffer Manager

SRA

M

InterfaceInterface

Interface

Interface

275Components

150Components

75Components

35Components


HDD Electronics Advances• Silicon Integration

• ECC

• Packaging

• Buffer memory utilization

• Functional Integration

DR

AM

Flash

Read Channel


VoltageRegulators

Interface

Formatter

Glue

Logic

uProcessor

Interface Block

Buffer Manager

SRA

M

DR

AM

Flash

Read Channel


VoltageRegulators

Interface

uProcessor

Formatter

Interface Block

Buffer

Manager SR

AM

Glue

Logic

DRAM

Servo & Spindle

Control + Volt. Regs

InterfaceuProcessor

Formatter

Interface Block

Buffer Manager

SRAM

ReadChannel

Glue

Logic


Voltage Regs

Interface

uProcessor

Formatter

Interface Block

Buffer M

anager

SRA

M

ReadChannel

Glue

Logic

DR

AM

• Pull read channel into SoC

• Incorporate voltage regulators into spindle control device

• Eliminate flash by storing code on disc

• Combine controller, formatter & glue logic• Embed SRAM

• Embed DRAM in SoC• Reduce Power to allow SoC• Reduce Pads/connections

Interface

Interface

Interface

Interface



• ECC

• Packaging


• Functional Integration

• Faster DRAM• Code moved from Flash

to Disc. Executed out of DRAM

• Faster DRAM enabled smaller SRAM which was moved internal to SoC

• Future designs will have the DRAM buffer embedded in the SoC. This supports very high bandwidth and very low power.

Gains made with improved ECC schemes enable the use of smaller less powerful read channels

Du=2.0, 18dB 69/70 CCE

Du=2.0, 18dB 30/31 ECC

Du=2.0, 19dB 69/70 CCE

Du=2.0, 19dB 30/31 ECC

Du=2.0, 20dB 69/70 CCE

Du=2.0, 20dB 30/31 ECC

Du=2.0, 21dB 69/70 CCE

Du=2.0, 21dB 30/31 ECC

69/70 CCE vs 30/31 ECC,Du=2.0, 18-22dB, 90%Jitter, S=10, I=1

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

0 2 4 6 8 10 12 14 16 18 20 22 24 26

Correction capability, T

CB

ER (S

ecto

r per

bit)

Gain in error rates with

reverse ECC

DR

AM

Buf

fer

uPuP

uP

SRA

MD

RA

MB

uffe

rFl

ash

SRAM SRAM

DRAM



• ECC

• Packaging


• Functional Integration.

TQFP

COB

Flip Chip


Optimization at the system level is the key to the future!


Voltage Regs

Interface

uProcessor

Formatter

Interface Block

Buffer M

anager

SRA

M

ReadChannel

Glue

Logic

DR

AM

HDD optimization is reaching it’s minimum point

The storage device is the largest factor to BOM cost in many CE

devices

• Functional integration of system and storage device(s)

• Fully utilize HDD electronics to eliminate redundant system functions

• Take an HDD centric approach to optimize system BOM cost and reduce power usage

• Allows more flexibility for data

– Storage

– Usage and delivery

AND

The answer

is…..

Interface

Optimize the system around the

storage device!

PMP BOM Cost Break-down

ApplicationElectronics

20%

Battery2%

Mechanical5%

HDD54%

LCD19%


What’s next : Increased functionality in the HDD!

In a typical compressedaudio player the HDD is

spun up and transferring data less than 1% of the time.

An average personal video player has the

HDD active only 5 seconds out of every 11 minutes.

• In many systems the processing capability of the HDD electronics is predominantly idle

• Future system design will take advantage of this available capability; moving more functionality into the HDD and further minimizing the overall design

Downloadfrom hdisk

Power off

Music Playback

Personal Video Player Current

0

200

400

600

800

1000

1200

5 505 1005 1505 2005 2505 3005

Time (s)

Cur

rent

(mA

)

Optimized Semiconductor Optimized Semiconductor Process Choices for MixedProcess Choices for Mixed--Signal Signal

HDD DevicesHDD Devices

Deames DavisDeames DavisManager, Marketing/Manager, Marketing/

Business DevelopmentBusiness DevelopmentStorage Products GroupStorage Products Group

12/06/0512/06/05 Deames DavisDeames Davis

Myths about MixedMyths about Mixed--signal Processessignal Processes

••Device in next generation process is Device in next generation process is alwaysalways::–– Smaller die sizeSmaller die size–– Lower costLower cost–– Better power handlingBetter power handling–– Better performanceBetter performance


HDD Segment ConsiderationsHDD Segment Considerations

SegmentSegment CostCost Die SizeDie Size PowerPower PerformancePerformance

EnterpriseEnterprise 33 44 22 11

DesktopDesktop 11 44 33 22

NotebookNotebook 22 44 11 33

MicrodriveMicrodrive 33 11 22 44


Die Size ImpactDie Size Impact•• Minimum feature size shrinks with each Minimum feature size shrinks with each

successive process nodesuccessive process node•• Digital functions get full entitlement of shrinkDigital functions get full entitlement of shrink•• Analog functions are sized based on Analog functions are sized based on

voltage/current requirementsvoltage/current requirements–– Many analog functions need transistors larger than Many analog functions need transistors larger than

minimumminimum--featurefeature--sizesize–– Die area for given block may not change in successive Die area for given block may not change in successive

process nodesprocess nodes

•• Die size reduction is probable, but not Die size reduction is probable, but not guaranteedguaranteed


MixedMixed--Signal Process Roadmap Enables Signal Process Roadmap Enables Increased Integration, Performance, and Increased Integration, Performance, and FunctionalityFunctionality

LBC4 LBC6LBC3s LBC7

-22%-40%

-40%

Production ~1997

Production~1999

Production~2002

Production~2005

Ex: 12V Combo Motor Driver IC

1µm .72µm .45µm .35µm

Mixed-signal lithography follows in digital process footsteps Smaller chip plus increased integration

Preamp: Head Heaters, ADCs, Vertical Recording, etc.Servo: Dual Stage Actuation, Shock interface, Vreg FETs, etc.


Cost ImpactCost Impact

•• Wafer prices tend to be set by complexityWafer prices tend to be set by complexity–– Mask levels, process steps, etc.Mask levels, process steps, etc.–– Metallization technologyMetallization technology–– Manufacturing cycle time is also set by Manufacturing cycle time is also set by complexitiycomplexitiy

•• New processes may need new New processes may need new fabfab equipmentequipment–– Depreciation costDepreciation cost–– Highest cost during early productionHighest cost during early production

•• Volume/time will reduce cost, but device cost at Volume/time will reduce cost, but device cost at process transition is ~parityprocess transition is ~parity


TI Motor Driver Process RoadmapTI Motor Driver Process Roadmapmetal

system

DECMOS

core logic

HV

DMOS

analog

bipolar

R & C

2000 2001 2002 2003 2004

A12 A07 A07s

LBC7

LBC8LBC5

LBC6

LBC

LinEPIC

LBC4

LV

HV

1533C035 1218C027

1533A035

1833C05ASIC / CMOS

Bubble Positions indicate approx Process QUAL dates

2005


Power ImpactPower Impact

•• DissipationDissipation–– For like feature set and performance, device in next For like feature set and performance, device in next

generation process tends to use less powergeneration process tends to use less power

•• Power DensityPower Density–– Processes can be optimized to handle higher power Processes can be optimized to handle higher power

density (e.g. topdensity (e.g. top--layer copper)layer copper)

•• HandlingHandling–– Small die handles less power than larger die due to Small die handles less power than larger die due to

less physical contact with thermal path less physical contact with thermal path


ConclusionsConclusions••Device in next generation process is Device in next generation process is alwaysalways::

–– Smaller die sizeSmaller die size (Mostly, Yes)(Mostly, Yes)–– Lower costLower cost (Over time, Yes)(Over time, Yes)–– Better power handlingBetter power handling (Match power to die size)(Match power to die size)–– Better performanceBetter performance (Mostly, Yes)(Mostly, Yes)

••Process choice involves tradeProcess choice involves trade--offs and timing within offs and timing within process lifeprocess life--cyclecycle

•• It is important to have a “quiver” of processes to It is important to have a “quiver” of processes to provide the right process for the right productprovide the right process for the right product

–– Need to consider all aspects of performance (speed, Need to consider all aspects of performance (speed, power, voltage, current) before choosing process power, voltage, current) before choosing process

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