Customer Training Workshop Traveo™ II Interrupts
Transcript of Customer Training Workshop Traveo™ II Interrupts
Traveo™ II Interrupts
Q4 2020
Customer Training Workshop
Target Products
› Target product list for this training material:
2Copyright © Infineon Technologies AG 2020. All rights reserved.
Family Category Series Code Flash Memory Size
Traveo™ II Automotive Body Controller Entry CYT2B6 Up to 576 KB
Traveo II Automotive Body Controller Entry CYT2B7 Up to 1088 KB
Traveo II Automotive Body Controller Entry CYT2B9 Up to 2112 KB
Traveo II Automotive Body Controller Entry CYT2BL Up to 4160 KB
Traveo II Automotive Body Controller High CYT3BB/
CYT4BB
Up to 4160 KB
Traveo II Automotive Body Controller High CYT4BF Up to 8384 KB
Traveo II Automotive Cluster CYT3DL Up to 4160 KB
Traveo II Automotive Cluster CYT4DN Up to 6336 KB
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Introduction to Traveo II Body Controller Entry
3Copyright © Infineon Technologies AG 2020. All rights reserved.
› The interrupt controller is in the CPUSS block
Review TRM chapter 12 for additional details
Hint Bar
002-22198 *C, 2020-12-10
I/O Subsystem
Peripheral Interconnect (MMIO, PPU)
IOSS G
PIO
PCLK
7x S
CB
I2C
, SP
I, UA
RT
CPU Subsystem
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
CRYPTOAES, SHA, CRC,
TRNG, RSA,
ECC
Initiator/MMIO
High-Speed I/O Matrix, Smart I/O, Boundary Scan
1x S
CB
I2C
, SP
I, UA
RT
CYT2BLMXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVDBOD
OVD
LDO
ClockClock Control
IMOWDT
CSV
1xPLL
ECO2xILO
FLL 83x T
CP
WM
TIM
ER
, CT
R, Q
D, P
WM
SWJ/MTB/CTI
MUL, NVIC, MPU
Arm Cortex
M0+100 MHz
5x Smart I/O
8x C
AN
FD
CA
N-F
D In
terfa
ce
eF
US
E1
02
4 b
it
SWJ/ETM/ITM/CTI
Arm Cortex M4160 MHz
FPU, NVIC, MPU
eCT Flash4160 KB Code-flash +
128 KB Work-flash
FLASH Controller
8 KB $ 8 KB $
SRAM0256 KB
SRAM Controller
ROM32 KB
ROM Controller
12x L
INL
IN/U
AR
T
Prog.Analog
SAR ADC(12-bit)
x3
SARMUX64 chWCO
SRAM1256 KB
SRAM Controller
M-D
MA
04
Ch
an
ne
l
P-D
MA
14
4 C
ha
nn
el
P-D
MA
09
2 C
ha
nn
el
DeepSleep
Hibernate
Active/SleepLowePowerActive/Sleep
Power Modes
Up to 148x GPIO_STD, 4x GPIO_ENH
EV
TG
EN
Even
t Gen
era
tor
4x C
XP
IC
XP
I Inte
rface
RTC
Introduction to Traveo II Body Controller High
4Copyright © Infineon Technologies AG 2020. All rights reserved.
› The interrupt controller is in the CPUSS block
Review TRM chapter 12 for additional details
Hint Bar
I/O Subsystem
Up to 196x GPIO_STD, 4x GPIO_ENH, 40xHSIO
High Speed I/O Matrix, Smart I/O, Boundary Scan
CYT4BFMXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System ResourcesPower
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVD
BOD
DeepSleep
Hibernate
Active/Sleep
LowPowerActive/Sleep
Power Modes
OVP
LDO
ClockClock Control
IMO
WDT
CSV
4xPLL
ECO
2xILO
FLL
5x Smart IO
WCO
RTC
Peripheral Interconnect (MMIO,PPU)
IOSS G
PIO
PCLK
CPU Subsystem
System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
115
x T
CP
WM
TIM
ER
,CT
R,Q
D, P
WM
10x C
AN
FD
CA
N-F
D In
terfa
ce
EF
US
E
1x F
LE
XR
AY
Fle
xR
ay In
terfa
ce
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7350 MHz
FPU(SP/DP)
D$16KB
I$16KB
AHBSAHBP
ITCM
16 KB
DTCM
16 KB
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7350 MHz
FPU(SP/DP)
D$16 KB
I$16 KB
AHBSAHBP
ITCM
16 KB
DTCM
16 KB
eCT FLASH8384 KB Code flash
+ 256 KB Work flash
FLASH Controller8 KB $
10x S
CB
I2C
,SP
I,UA
RT
,LIN
1x S
CB
I2C
,SP
I,UA
RT
,LIN
20x L
INL
IN/U
AR
T
CRYPTOAES,SHA,CRC,
TRNG,RSA,ECC
Initiator/MMIO
SWJ/MTB/CTI
MUL, NVIC, MPU
Cortex M0+100 MHz
SRAM0512 KB
SRAM Controller
ROM64 KB
ROM Controller
M-D
MA
08
Ch
an
ne
l
P-D
MA
16
5 C
ha
nn
el
P-D
MA
01
43
Ch
an
ne
l
1x S
MIF
Se
rial M
em
ory
Inte
rface
(Hyp
erb
us, S
ing
le S
PI,
Dua
l SP
I, Qu
ad
SP
I, Octa
l SP
I)
2x E
TH
10
/10
0/1
00
0 E
the
rnet +
AV
B
SD
HC
SD
/SD
IO/e
MM
C
EV
TG
EN
Even
t Gen
era
tor
3x A
UD
IOS
SI2
S/T
DM
In/O
ut
SRAM1256 KB
SRAM Controller
SRAM2256 KB
SRAM Controller
Prog.Analog
SAR ADC(12-bit)
x3
SARMUX96 ch
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Introduction to Traveo II Cluster
5Copyright © Infineon Technologies AG 2020. All rights reserved.
› The interrupt controller is in the CPUSS block
Review TRM chapter 12 for additional details
Hint Bar
IO Subsystem
Peripheral Interconnect (MMIO,PPU)
IOSS G
PIO
PCLK
52x GPIO_STD, 8x GPIO_ENH, 26x GPIO_SMC, 70x HSIO_STD, 22x HSIO_ENH, 4x HSIO_ENG_DIFF
CPU Subsystem
System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
High Speed I/O Matrix, Smart I/O, Boundary Scan
CYT4DNMXS40-HT
ASIL-B
Digital DFT
Test
Analog DFT
System Resources
Power
Reset
Sleep Control
PWRSYS-HT
REF
POR
Reset Control
TestMode Entry
XRES
LVDBOD
DeepSleepHibernate
Active/SleepLowePowerActive/Sleep
Power Modes
OVP
ClockClock Control
IMOWDT
CSV
8xPLL
ECOFLL 8
2x T
CP
WM
TIM
ER
,CT
R,Q
D, P
WM
, SM
C
1x Smart IO
4x C
AN
FD
CA
N-F
D In
terfa
ce
EF
US
E
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7320 MHz
FPU(SP/DP)
D$16KB
I$16KB
AHBSAHBP
ITCM
64 KB
DTCM
64 KB
SWJ/ETM/ITM/CTI
NVIC, MPU, AXI
Cortex M7320 MHz
FPU(SP/DP)
D$16 KB
I$16 KB
AHBSAHBP
ITCM
64 KB
DTCM
64 KB
eCT FLASH6336 KB Code-flash
+ 128 KB Work-flash
FLASH Controller8 KB $
Prog.Analog
SAR ADC(12-bit)
x1
11x S
CB
I2C
,SP
I,UA
RT
,LIN
1x S
CB
I2C
,SP
I,UA
RT
,LIN
2x L
INL
IN/U
AR
T
RTC
2xILO
SARMUX48 ch
CRYPTOAES,SHA,CRC,
TRNG,RSA,ECC
Initiator/MMIO
SWJ/MTB/CTI
MUL, NVIC, MPU
Cortex M0+100 MHz
SRAM0256 KB
SRAM Controller
ROM64 KB
ROM Controller
M-D
MA
08
Ch
an
ne
l
P-D
MA
18
4 C
ha
nn
el
P-D
MA
07
6 C
ha
nn
el
2x S
MIF
Se
rial M
em
ory
Inte
rface
(Hyp
erb
us, S
ing
le S
PI,
Dua
l SP
I, Qu
ad
SP
I, Octa
l SP
I)
1x E
TH
10
/10
0/1
00
0 E
the
rne
t + A
VB
EV
TG
EN
Even
t Gen
era
tor
LDO
WCO
SRAM1256 KB
SRAM Controller
GFX Subsystem
GFX Interconnect (AXI)
1x R
GB
/MIPI In
pu
t
2x R
GB
/LVD
S Ou
tpu
t
2.5
D E
ng
ine
VRAM4096 KB
VRAM Controller
Vecto
r Gfx
2x C
XP
IC
XP
I Inte
rface
4x I2
S
2x P
CM
-PW
M
5x S
G
2x M
ixe
r
Audio
DA
C
4x T
DM
LPECO
SRAM2128 KB
SRAM Controller
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Interrupts Overview
› Interrupts are events generated by peripherals of each CPU
› Exceptions are events generated by each CPU
› Features
– Up to 10231 system interrupts
– Any of the system interrupts can be mapped to each CPU NMI (up to four)
– Vector table is placed in either flash or SRAM
– Configurable priority levels (eight levels for Cortex-M4/M7 and four levels
for Cortex-M0+) for each interrupt
– All the available system interrupt sources are usable in Active power mode
and wake up from Sleep power mode
– Wakeup interrupts are capable of waking the device from DeepSleep
power mode
6Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.1 for additional details specific to Interrupts
Refer to each device datasheet for the list of system interrupts
Refer to the CPUSS Training Section for additional Vector Table Relocation details
Hint Bar
1 The total number of system interrupts varies depending on the devicec
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Components in Interrupt Architecture
› The interrupt architecture consists of the following components.
7Copyright © Infineon Technologies AG 2020. All rights reserved.
Arm provides additional reference material on their webpage at:infocenter.arm.com
Nested Vectored Interrupt Controller (NVIC)
Interrupt request (IRQ)
Hint Bar
CM7_1
CPU Interrupt
Generation
Cortex-M7_1
Processor CoreNVIC
CM7_1 Processor
Cortex-M0+
Processor CoreNVIC
CM0+ Processor
IRQ1
IRQ2
IRQ7
N
Interrupt Sources
(Peripherals)
System INT Source 1
System INT Source 2
System INT Source 0
IRQ0
Cortex-M4/ M7_0
Processor CoreNVIC
CM4/ CM7_0 Processor
System INT Source N-1
M
CM0+ Settings
CM4/ CM7_0/ CM7_1 Settings
CM
0+
Wa
ke
up
CM
4/ C
M7
_0
/ C
M7
_1
Wa
ke
up
DeepSleep
Interrupt
Sources (M)
IRQ1
IRQ2
IRQ7
IRQ0
CM4/ CM7_0/ CM7_1 Wakeup
From WIC
N
N
CM0+ Wakeup
From WIC
Interrupt
Synchronizer
CM0+ CPU
Interrupt
Generation
CM4/ CM7_0
CPU Interrupt
Generation
Wakeup Interrupt
Controller (WIC)
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Interrupt Architecture Block Diagram
› Interrupt Architecture Components– Interrupt sources
– System interrupts
– Wakeup interrupts
8Copyright © Infineon Technologies AG 2020. All rights reserved.
Number of system interrupts (N)
Number of wakeup interrupts (M)
Refer to the Appendix for the number of system interrupts, listed by device
Refer to each device datasheet for the list of system interrupts
Hint Bar
CM7_1
CPU Interrupt
Generation
Cortex-M7_1
Processor CoreNVIC
CM7_1 Processor
Cortex-M0+
Processor CoreNVIC
CM0+ Processor
IRQ1
IRQ2
IRQ7
N
Interrupt Sources
(Peripherals)
System INT Source 1
System INT Source 2
System INT Source 0
IRQ0
Cortex-M4/ M7_0
Processor CoreNVIC
CM4/ CM7_0 Processor
System INT Source N-1
M
CM0+ Settings
CM4/ CM7_0/ CM7_1 Settings
CM
0+
Wa
ke
up
CM
4/
CM
7_
0/
CM
7_
1
Wa
ke
up
Deep Sleep
Interrupt
Sources (M)
IRQ1
IRQ2
IRQ7
IRQ0
CM4/ CM7_0/ CM7_1 Wakeup
From WIC
N
N
CM0+ Wakeup
From WIC
Interrupt
Synchronizer
CM0+ CPU
Interrupt
Generation
CM4/ CM7_0
CPU Interrupt
Generation
Wakeup Interrupt
Controller (WIC)System interrupts
Wakeup interrupts are mapped to
the same number of CPU interrupts
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Interrupt Sources
› System Interrupts
– Originate from peripheral interrupts
– Include wakeup interrupts
› Wakeup Interrupts
– Wakes CPU up from DeepSleep mode
› Use Case
– The GPIO can be used as a CAN wakeup interrupt
9Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.5 for additional details about system interrupts
Refer to each device datasheet for the list of system interrupts
Review TRM section 12.10 for additional details about wakeup interrupts
Wakeup from DeepSleepmode involves the WIC
Review TRM section 12.10 for additional details specific to WIC
Review the Device Power Modes training section for additional Wakeup Interrupts details
Hint Bar
TXCAN TX
CAN
NVIC
Pin 1
GPIO
Pin 2RXCAN RX
CAN Wakeup Signal
CAN RX Interrupt
Wakeup Interrupt
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Interrupt Synchronizer
› Interrupt Architecture Components
– Interrupt synchronizer
10Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.5 for additional details about system interrupts
Refer to each device datasheet for the list of system interrupts
Review TRM section 12.10 for additional details about wakeup interrupts
Wakeup from DeepSleepmode involves the WIC
Review TRM section 12.10 for additional details specific to WIC
Review the Device Power Modes training section for additional Wakeup Interrupts details
Hint Bar
CM7_1
CPU Interrupt
Generation
Cortex-M7_1
Processor CoreNVIC
CM7_1 Processor
Cortex-M0+
Processor CoreNVIC
CM0+ Processor
IRQ1
IRQ2
IRQ7
N
Interrupt Sources
(Peripherals)
System INT Source 1
System INT Source 2
System INT Source 0
IRQ0
Cortex-M4/ M7_0
Processor CoreNVIC
CM4/ CM7_0 Processor
System INT Source N-1
M
CM0+ Settings
CM4/ CM7_0/ CM7_1 Settings
CM
0+
Wa
ke
up
CM
4/
CM
7_
0/
CM
7_
1
Wa
ke
up
Deep Sleep
Interrupt
Sources (M)
IRQ1
IRQ2
IRQ7
IRQ0
CM4/ CM7_0/ CM7_1 Wakeup
From WIC
N
N
CM0+ Wakeup
From WIC
Interrupt
Synchronizer
CM0+ CPU
Interrupt
Generation
CM4/ CM7_0
CPU Interrupt
Generation
Wakeup Interrupt
Controller (WIC)
Synchronizes the interrupts to the CPU clock frequency
as the peripheral interrupts can be asynchronous to the
CPU clock frequency
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CPU Interrupt
› Interrupt Architecture Components
– CPU interrupt– Each system interrupt can be mapped to exactly one CPU interrupt of each core
– Achieved using the register setting– CM0/CM4/CM7_0/CM7_1_SYSTEM_INT_CTL.CPU_INT_IDX[2:0]
– CM0/CM4/CM7_0/CM7_1_SYSTEM_INT_CTL.CPU_INT_VALID
11Copyright © Infineon Technologies AG 2020. All rights reserved.
Refer to each device datasheet for the list of system interrupts
CM7_0 and CM7_1 represent the first and the second CM7 core in the TVII-B-H device, respectively
Hint Bar
CM7_1
CPU Interrupt
Generation
Cortex-M7_1
Processor CoreNVIC
CM7_1 Processor
Cortex-M0+
Processor CoreNVIC
CM0+ Processor
IRQ1
IRQ2
IRQ7
N
Interrupt Sources
(Peripherals)
System INT Source 1
System INT Source 2
System INT Source 0
IRQ0
Cortex-M4/ M7_0
Processor CoreNVIC
CM4/ CM7_0 Processor
System INT Source N-1
M
CM0+ Settings
CM4/ CM7_0/ CM7_1 Settings
CM
0+
Wa
ke
up
CM
4/
CM
7_
0/
CM
7_
1
Wa
ke
up
Deep Sleep
Interrupt
Sources (M)
IRQ1
IRQ2
IRQ7
IRQ0
CM4/ CM7_0/ CM7_1 Wakeup
From WIC
N
N
CM0+ Wakeup
From WIC
Interrupt
Synchronizer
CM0+ CPU
Interrupt
Generation
CM4/ CM7_0
CPU Interrupt
Generation
Wakeup Interrupt
Controller (WIC)
System interrupts are mapped to
8 CPU interrupts for each CPU
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Interrupt Handler Processing (1/3)
› Sequence of a normal interrupt request handling
– Interrupt request asserts IRQn
– When the IRQn request can be accepted, the
NVIC sets the pending status
– Jumps to the interrupt handler
– Entering the interrupt handler clears the
pending status
– Clears the interrupt flag of the peripheral
register
– Reads the interrupt flag of the peripheral
register to drain the Write Buffer
– Return
12Copyright © Infineon Technologies AG 2020. All rights reserved.
1
2
3
4
5
6
7
CPU
NVIC
AHB-Lite Bridge
Write Buffer
Peripheral
Interrupt Flag
IRQn Pending = 1 0
Interrupt Handler
Register
Clear Flag
Return
IRQn Request
Read flag
1
2
3
4
7
6
5
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Interrupt Handler Processing (2/3)
› The CPU interrupt handler uses the SYSTEM_INT_IDX field to index a system
interrupt lookup table and jump to the system interrupt handler
› Read after write (RAW) is important in the interrupt handler processing to
ensure completion of the write buffer
13Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.5 for additional details
The lookup table is usually located in one of the system memories
Hint Bar
002-22198 *C, 2020-12-10
Interrupt Handler Processing (3/3)
– void CM4/CM7_0/CM7_1_SystemIntr0_Handler (void)
– {
– // Clear the peripheral interrupt request flag by register write
– // Read back the register to ensure completion of register write access
– // Handle system interrupt 0.
– }
– …
– void CM4/CM7_0/CM7_1_SystemIntr1022_Handler (void)
– {
– // Clear the peripheral interrupt request flag by register write
– // Read back the register to ensure completion of register write access
– // Handle system interrupt 1022.
14Copyright © Infineon Technologies AG 2020. All rights reserved.
› The following code illustrates the sequence:
void CM4/CM7_0/CM7_1_CpuIntr0_Handler (void){
uint32_t system_int_idx;SystemIntr_Handler handler;if(CPUSS_CM4/CM7_0/CM7_1_INT_STATUS[0].SYSTEM_INT_VALID){
system_int_idx = CPUSS_CM4/CM7_0/CM7_1_INT_STATUS[0].SYSTEM_INT_IDX;handler = SystemIntr_Table[system_int_idx];handler(); // jump to system interrupt handler
}else{
// Triggered by software or due to software cleared a peripheral interrupt flag// but did not clear the Pending flag at NVIC
}}…void CM4/CM7_0/CM7_1_CpuIntr7_Handler (void){
uint32_t system_int_idx;SystemIntr_Handler handler;if(CPUSS_CM4/CM7_0/CM7_1_INT_STATUS[7].SYSTEM_INT_VALID){
system_int_idx = CPUSS_CM4/CM7_0/CM7_1_INT_STATUS[7].SYSTEM_INT_IDX;handler = SystemIntr_Table[system_int_idx];handler(); // jump to system interrupt handler
}else{// Triggered by software or due to software cleared a peripheral interrupt flag// but did not clear the Pending flag at NVIC}
}
002-22198 *C, 2020-12-10
NVIC
› Interrupt Architecture Components
– NVIC– CPU interrupt priority
– Nested interrupts
15Copyright © Infineon Technologies AG 2020. All rights reserved.
Arm provides additional reference material on their webpage at:infocenter.arm.com
Hint Bar
CM7_1
CPU Interrupt
Generation
Cortex-M7_1
Processor CoreNVIC
CM7_1 Processor
Cortex-M0+
Processor CoreNVIC
CM0+ Processor
IRQ1
IRQ2
IRQ7
N
Interrupt Sources
(Peripherals)
System INT Source 1
System INT Source 2
System INT Source 0
IRQ0
Cortex-M4/ M7_0
Processor CoreNVIC
CM4/ CM7_0 Processor
System INT Source N-1
M
CM0+ Settings
CM4/ CM7_0/ CM7_1 Settings
CM
0+
Wa
ke
up
CM
4/
CM
7_
0/
CM
7_
1
Wa
ke
up
Deep Sleep
Interrupt
Sources (M)
IRQ1
IRQ2
IRQ7
IRQ0
CM4/ CM7_0/ CM7_1 Wakeup
From WIC
N
N
CM0+ Wakeup
From WIC
Interrupt
Synchronizer
CM0+ CPU
Interrupt
Generation
CM4/ CM7_0
CPU Interrupt
Generation
Wakeup Interrupt
Controller (WIC)
NVIC receives IRQs, evaluates the
priority, and communicates with the
CPU core
002-22198 *C, 2020-12-10
Exception Vector Table (1/2)
› The exception vector tables store the entry point addresses for all exception
handlers in Cortex-M0+, Cortex-M4, and Cortex M7 cores
16Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.3.3 for additional details
IRQ0-IRQ7 are connected to the System Interrupt generation logic
IRQ8-IRQ15 can be triggered by software only and are not connected to any peripheral
Hint Bar
Cortex-M0+ Exception Vector Table
Exception # Exception Exception Priority Vector Address
– Initial stack pointer value Not applicable (N/A) Start_Address = 0x0000 or CM0P_SCS_VTOR1
1 Reset –3, highest priority Start_Address + 0x04
2 Non-maskable Interrupt (NMI) –2 Start_Address + 0x08
3 Hard fault –1 Start_Address + 0x0C
4–10 Reserved N/A Start_Address + 0x10 to Start_Address + 0x28
11 Supervisory call (SVCall) Configurable (0–3) Start_Address + 0x2C
12–13 Reserved N/A Start_Address + 0x30 to Start_Address + 0x34
14 Pend supervisory (PendSV) Configurable (0–3) Start_Address + 0x38
15 System tick timer (SysTick) Configurable (0–3) Start_Address + 0x3C
16 External interrupt (IRQ0) Configurable (0–3) Start_Address + 0x40
… … … …
23 External interrupt (IRQ7) Configurable (0–3) Start_Address + 0x5C
24 Internal (SW only) interrupt (IRQ8) Configurable (0-3) Start_Address + 0x60
… … … …
31 Internal (SW only) interrupt (IRQ15) Configurable (0-3) Start_Address + 0x7C
1 Start Address = 0x0000 on reset and is later modified in the user code by updating the CM0P_SCS_VTOR register
002-22198 *C, 2020-12-10
Exception Vector Table (2/2)
17Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.3.3 for additional details
IRQ0-IRQ7 are connected to the System Interrupt generation logic
IRQ8-IRQ15 can be triggered by software only and are not connected to any peripheral
Hint Bar Cortex-M4/M7 Exception Vector Table
Exception # Exception Exception Priority Vector Address
– Initial stack pointer value –Start_Address = 0x0000 or
CM4/CM7_0/CM7_1_SCS_VTOR1
1 Reset –3, highest priority Start _Address + 0x0004
2 Non-maskable Interrupt (NMI) –2 Start _Address + 0x0008
3 Hard fault –1 Start _Address + 0x000C
4 Memory management fault Configurable (0–7) Start _Address + 0x0010
5 Bus fault Configurable (0–7) Start _Address + 0x0014
6 Usage fault Configurable (0–7) Start _Address + 0x0018
7–10 Reserved – –
11 Supervisory call (SVCall) Configurable (0–7) Start _Address + 0x002C
12–13 Reserved – –
14 Pend supervisory (PendSV) Configurable (0–7) Start _Address + 0x0038
15 System tick timer (SysTick) Configurable (0–7) Start _Address + 0x003C
16 External interrupt (IRQ0) Configurable (0–7) Start _Address + 0x0040
… … … …
23 External interrupt (IRQ7) Configurable (0–7) Start _Address + 0x005C
24 Internal (SW only) interrupt (IRQ8) Configurable (0–7) Start _Address + 0x60
… … … …
31 Internal (SW only) interrupt (IRQ15) Configurable (0-7) Start _Address + 0x7C1 Start Address = 0x0000 on reset and is later modified by the user code by updating the CM4/CM7_0/CM7_1_SCS_VTOR register
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CPU Interrupt Priority
› The priority of each interrupt can be configured to eight levels for both Cortex-
M4 and M7 and four levels for Cortex-M0+
› Use case for CPU interrupt priority
– Example of priority levels and interrupts for body application
18Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.5 for additional details
Refer to each device datasheet for the list of system interrupts
Hint Bar
Priority Level
-2 : Fault NMI exception, protection violation
0 : GPIO Ignition detection, wakeup use
1 : CAN Communication with other ECU
2 : LIN Communication with other ECU
3 : SCB Communication with external IC
4 : TCPWM Task management
5 : Event Generator Wakeup use
6 : ADC Sensor data acquisition
7 : RTC Real-time clock alarm
Main routine
High
Low
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Nested Interrupts
› Depending on the interrupt priority level, nested interrupts are possible
› Use case for nested interrupts
19Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.5 for additional details
CAN is serviced before LIN based on the index order of system interrupts
Refer to each device datasheet for the list of system interrupts
Hint Bar
Main
ADCCAN
ReturnLIN
Priority Level = 6
ADC Interrupt
CAN Interrupt
Priority Level = 1
Priority Level = 1
Return
LIN Interrupt
Return
Main Routine
Resumes
1
2
3
11
4
10
9
6
8
7
5
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Enabling and Disabling Interrupts
› The NVICs of CM0+, CM4, and CM7 cores provide registers to individually
enable and disable the CPU interrupts in software
› CM0+, CM4, and CM7 interrupts are enabled and disabled using the ISER and
ICER
› If an interrupt is not enabled, the NVIC will not process the interrupt requests
on that interrupt line
› CM0+, CM4, and CM7 provide additional registers to control the activation of
exceptions/interrupts based on their priority
– PRIMASK: Prevent activation of exceptions having configurable priority
– FAULTMASK: Prevent activation of all exceptions other than NMI
– BASEPRI: Prevent activation of exceptions having the same or lower
priority than the BASEPRI
20Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.7 for additional details
Interrupt Set-Enable Register (ISER)
Interrupt Clear-Enable Register (ICER)
Hint Bar
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Exception States
› Each exception can be in one of the following states:
21Copyright © Infineon Technologies AG 2020. All rights reserved.
Review TRM section 12.8 for additional details.
Hint Bar
Inactive
Active
Return
PendingNot Active
Not Pending
Waiting
Exception is serviced by the processor, pending a request from the same source
during exception handler execution
IRQ3 (CAN) priority = 1 IRQ5 (Fault)
Priority= 0
IRQ3 (TCPWM) priority = 1
Active Pending
Return
(Active)
IRQ3 (TCPWM) priority = 1
Pending exception is serviced after the execution of exceptions with higher priority is complete
Active1
2
3
12
4
11
10
7
98
6
5
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Appendix
Number of Interrupts
23Copyright © Infineon Technologies AG 2020. All rights reserved.
› Maximum number of system interrupts and wakeup interrupts varies by device.
Series Maximum Number of
System Interrupts
Maximum Number of
Wakeup Interrupts
CYT2B6 228 38
CYT2B7 353 45
CYT2B9 383 45
CYT2BL 383 45
CYT3BB/CYT4BB 443 51
CYT4BF 567 51
CYT3DL 798 50
CYT4DN 798 50
Refer to each device datasheet for the list of system interrupts
Hint Bar
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24Copyright © Infineon Technologies AG 2020. All rights reserved.002-22198 *C, 2020-12-10
Revision HistoryRevision ECN Submission
Date
Description of Change
** 6154903 04/29/2018 Initial release
*A 6396762 11/29/2018 Added pages 2, 4, and 5 and note descriptions for all pages
Updated pages 3, 6, 7, 8, 10, 11, 14, 15, 16, 17, 18, and 20
Changed the contents of the Appendix section
*B 6612968 07/04/2019 Updated note descriptions for pages 3, 4, 5, 23, and 24
Updated pages 2, 5, 14, and 23
*C 7042917 12/11/2020 Updated page 2, 3, 9 and 23
Copyright © Infineon Technologies AG 2020. All rights reserved. 25002-22198 *C, 2020-12-10