Cuk Topology

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Published in IET Power Electronics

Received on 22nd November 2007

Revised on 21st February 2008

doi: 10.1049/iet-pel:20070023

ISSN 1755-4535

Voltage-lift-type Cuk converters: topologyand analysisM. Zhu F.L. LuoCenter of Advanced Power Electronics, School of Electrical and Electronic Engineering, Nanyang Technological University,

Singapore 639798, SingaporeE-mail: [email protected]

Abstract: The voltage-lift (VL) technique is an effective method that could be applied in electronic circuit design.

A series of negative output dcdc converters (Voltage-lift-type Cuk converters) applying series Cuk implementing

VL techniques is introduced. Compared with the Cuk converter prototype, these converters can perform positive

to negative dc dc voltage increasing conversion with higher voltage transfer gains. They are different from other

existing dcdc step-up converters and possess several advantages, mainly including fewer switches, clear

conversion processes and a high output voltage with the small ripple. Since the proposed converters avoid

using transformers and cascade connection, the relative simple structures are beneficial to potential practical

applications in future. A detailed theoretical analysis for continuous and discontinuous conduction modes is

given. Both simulation and experimental results are provided to verify the main characteristics.

1 Introduction

Dc dc step-up converters are widely used in computerhardware and industrial applications, such as computerperiphery power supplies, car auxiliary power supplies,servo-motor drives and medical equipment [1, 2]. Theclassical Cuk converter [3] shown in Fig. 1 has manyindustrial applications due to its good characteristics. Thistopology provides an output voltage with an opposite

polarity to its input voltage. Inductors L and L1 reduceEMI problems, and the output ripple is small. Under thedifferent conditions of duty ratio D, it can perform thestep-down and step-up dcdc conversion due to its voltagetransfer function as

MCuk D

1 D(1)

Because of the effects of parasitic elements, the practicalvalues of D in (1) have an upper limit and cannot be toohigh (usually should not be higher than 0.9). So, the

output voltage and power transfer efficiency of the Cukconverter have been seriously restricted. With the fastdevelopment of technologies, this disadvantage limits the

further applications of Cuk converters in some areas thatrequire higher voltage transfer gains such as communicationequipment, aerospace electronics, portable devices and ICchips.

Dc dc converters may be developed by n-cell cascadeconnection or by adding transformers to obtain higher

voltage transfer gains [411]. However, the resultingproblems, energy losses, multiple power switches and large

switching surges in transformers significantly increase thecontrol complexity and the cost of these converters. Inrecent years, advanced dc dc conversion enhancementtechniques such as switched-capacitor (SC) and voltage-lift(VL) techniques have been greatly explored [1222]. Themain objective is to reach a high efficiency, high powerdensity and simple structures. Since Cuk converters is aclassical topology, the combination with the Cuk prototypeand the above-mentioned enhancement techniques couldbe a good solution for promoting its further application. Itis well known that the main advantage of SC techniques isthe absence of inductors, thus making it very small in size

and high in power density. However, more power switchesare required in SC-type converters than in magnetic-basedconverters.

178 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191

& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023

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The VL technique is an effective method that is widelyapplied in electronic circuit design, especially in the radioengineering. It can also lead to performance andcharacteristics improvement of dcdc converters; however,it differs from current SC techniques. Both inductors andcapacitors play an important role in the VL technique, andall inner capacitors are fully charged by the power source.Moreover, fewer power switches (usually single switch ortwo synchronous switches) are included in VL-type

structures and avoid those complex multiple-switch controlschemes. So we apply the VL technique to the Cukprototype in this paper and develop a new series Cukimplementing the VL technique. Consequently, a series ofnovel negative output VL-type Cuk converters has beensuccessfully created.

The proposed VL-type Cuk converters are different fromany other existing dc dc step-up converters and possessabove-mentioned advantages as well as primary advantagesin the Cuk prototype. They are categorised into theelementary self-lift circuit, the developed self-lift circuit,the re-lift circuit and multiple circuits (e.g. triple-lift andquadruple-lift circuit). All circuits perform positive tonegative dc dc voltage increasing conversion with higher

voltage transfer gains, small ripple and high efficiency insimple structures. Therefore they will be used in computerperipheral equipment and industrial applications, especiallyfor high output voltage projects. The detailed analysis willbe performed in the following sections.

For any component X in this paper, its instantaneouscurrent and voltage are expressed as iX and vX. Its averagecurrent and voltage during a switching cycle in the steadystate are expressed as IX and VX. All reference directions

of currents and voltages can be referred to in the correspondingfigures. For general description, each component is ideal andthe output power is equal to the input power, VoIo VinIin.

Any parameter with the subscript B indicates the boundaryvalues between continuous conduction mode (CCM) anddiscontinuous conduction mode (DCM). The symbols 1, zand j are defined as output voltage variation ratio, inductorcurrent variation ratio and diode current variation ratios,respectively.

2 Elementary self-lift circuit

The circuit existing in the pump section is the core part for adcdc converter. Applying the VL technique to the pump

section can achieve its evolution. The elementary self-liftcircuit as shown in Fig. 2a is derived from the Cukconverter prototype by adding two components (diode D1and capacitor C1) into the pump section. The equivalentcircuits during switching-on, switching-off and DCM areshown in Fig. 2b2d, respectively. When switch S turns

on, D1 is on, and Df is off. When S turns off, D1 is off,and Df is on. C1 performs characteristics to lift the outputcapacitor voltage VCo by the capacitor voltage VCs.Furthermore, a P-type low-pass filter C12 L12 Co isconstructed and combined with the pump section.

2.1 Circuit analysis in CCM

Switching diagrams with main steady-state waveforms areshown in Fig. 3a to analyse the circuit operation, wherereference directions are referred to in Fig. 2a. In the steadystate, the average voltage across L1 over a period is zero. Thus

VC1 VCo Vo

During the switch-on period, VC1 is equal to the voltageacross Cs. Since Cs and C1 are sufficiently large, we have

VCs VC1 Vo

Figure 1 Prototype of the Cuk converter

Figure 2 Elementary self-lift Cuk circuit

a Topology

b Equivalent circuit during switching-onc Equivalent circuit during switching-offd Equivalent circuit during DCM

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doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009

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The inductor current iL increases during switching-on anddecreases during switching-off. The corresponding voltagesacross L are Vin and (VCs Vin) . Therefore applying theinductor voltsecond balance principle to L, we have

DTVin (1 D)T(VCs Vin) or

DTVin (1 D)T(Vo Vin)

Hence

Vo 1

1 DVin

The voltage transfer gain in the CCM is

MS VoVin

1

1 D(2)

Therefore the input current is

Iin 1

1 DIo IL IDfoff (3)

Co acts as a low-pass filter so that

IL1 Io (4)

Since the peak-to-peak current variation ofiL, DiL is equal toDTVin=L, the variation ratio of iL is

6L DiL=2

IL

D

2M2S

R

fL(5)

The peak-to-peak voltage variation ratio of VC1, DvC1 isapproximate to

DvC1 Io(1 D)TC1

Therefore the variation ratio ofVC1 is

1C1 DvC1=2

VC1

1

2MS fRC1(6)

Because vo varies very little, the peak-to-peak currentvariation of iL1 can be calculated by the area A of a trianglewith width T/2 and the height DvC1=2, which isapproximately

DiL1 (1=2)(DVC1=2)(T=2)

L1

(1 D)Io8f2L1C1

Therefore the variation ratio of iL1 is approximate to

6L1 DiL1=2

IL1

1

16MS f2L1C1

(7)

The variation of iDf is equal to DiL during switching-off, sothe variation ratio of iDf is

jDf 6L D

2M2S

R

fL (8)

To simplify the calculation, we treat the ripple of iL1 as atriangle waveform as shown in Fig. 3a because the ripple ofiL1 is very small. So the peak-to-peak voltage variation ofvo is calculated by the area B, which is approximately

Dvo (1=2)(DiL1=2)(T=2)

Co

(1 D)Io64f3L1C1Co

Therefore the variation ratio ofvo is approximate to

1S Dvo=2

Vo

1

128MS f3L1C1CoR

(9)

Figure 3 Performance of the elementary self-lift circuit

a Waveforms with enlarged variationsb Boundary between CCM and DCM and voltage transfer gainsagainst ZN



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2.2 Circuit analysis in DCM

The elementary self-lift circuit operates in the DCM, if thecurrent iDf reduces to zero during switching-off. Thecondition for the DCM is jDf ! 1, that is,

jDf D2M2SZN ! 1 (10)

where ZN is defined as the normalised load R/( fL).

As a special case, when iDf decrease to zero at t T, thecircuit operates at the boundary of CCM and DCM.

Therefore the boundary between CCM and DCM isobtained as below

ZNB 2M2S

D

2

D(1 D)2(11)

When ZN . ZN2B, the circuit operates in the DCM. Underthis condition, iDfdecreases to zero att t1 [D mS (12D)]T, where

DT, t1 , T and 0 , mS , 1

Here, mS is the current filling efficiency for the elementary self-lift circuit and defined as

mS t1 DT

(1 D)T(12)

In the DCM, iL increases during switching-on and decreasesduring the period from DT to mS(12D)T. Thecorresponding voltages across L are Vin and 2(VCs2Vin).

Thus, utilising the volt-second balance principle, we have

DTVin mS(1 D)T(VCs Vin) or

DTVin mS(1 D)T(Vo Vin) (13)

In addition, the transferred charges ofL during switching-offare equal to mS(1 D)TDiL=2, which compensate the totalconsumed charges of the load. So we have

IoT 12 mS(1 D)TDiL or

VoR

T 1

2mS(1 D)T

DTVinL

(14)

Combining (13) and (14), we can obtain the filling efficiency ofthe elementary self-lift circuit as:

mS 1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 2D2ZN

pD(1 D)ZN

(15)

From (13), we have

Vo 1 D

mS(1 D)

Vin (16)

Therefore substituting (15) into (16) yields the voltage transfergain in the DCM as follows:

MSDCM 1

21

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 2D2ZN

q (17)

Using (2), (11) and (17), we can obtain the boundarycurve between CCM and DCM as well as voltagetransfer gains against the normalised load, which isshown in Fig. 3b.

3 Developed self-lift circuit

The developed self-lift circuit is derived from the elementaryself-lift circuit by adding the components (DoS1) andredesigning the connection relations of L1. The circuitdiagram is shown in Fig. 4(a), and the subscript S0 is used

here to distinguish this topology from the elementary self-lift circuit. The equivalent circuits during switching-on,

Figure 4 Developed self-lift Cuk circuit

a Topology

b Equivalent circuit during switching-onc Equivalent circuit during switching-offd Equivalent circuit during DCM



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switching-off and DCM are shown in Fig. 4b4d,respectively. Static switches S and S1 are switchedsimultaneously. The lift circuit consists of C12 L1-S1-D1,and it is a basic VL cell. When S and S1 turn on, D1 is on,Df and Do are off. When S and S1 turn off, D1 is off, Dfand Do are on. Capacitor C1 performs its characteristics to

lift the output capacitor voltage VCo by the capacitorvoltage VCs.


Switching diagrams with main steady-state waveforms areshown in Fig. 5a to analyse the circuit operation, wherereference directions are referred to in Fig. 4a. The inductorcurrent iL increases during switching-on and decreasesduring switching-off. The corresponding voltages across Lare Vin and (VCs Vin), which are the same with the

condition of the foregoing elementary self-lift circuit.

Therefore we obtain

VCs 1

1 DVin

During switching-on, the voltage across C1 is equal to VCs.

Since Cs and C1 are sufficiently large, we have

VC1 VCs 1

1 DVin

The inductor current iL1 increases during switching-on anddecreases during switching-off. The corresponding voltagesacross L are VCs and (VCo VC1). Therefore with thesec-voltage balance principle, we have

DTVCs (1 D)T(VCo VC1) or

DTVCs (1 D)T(Vo VCs)

Hence,

Vo 1

(1 D)2Vin

The voltage transfer gain in CCM is

MS0 VoVin

1

(1 D)2(18)

and the input current is

Iin 1

(1 D)2Io IL ICsoff (19)

The charges ofCo increase during switching-off and decreaseduring switching-on. We obtain

QCo IoDT

QCo ICooff(1 D)T

In a switching cycle, QCo QCo2. Therefore

ICooff D

1 DIo

During switching-off, iDo iCo io. Therefore

IDooff ICooff Io 1

1 DIo (20)

During switching-off, L1 and C1 form a path and transfer thestored energy through Do. Therefore

IL1 IDooff 1

1 DIo

Since the peak-to-peak current variation of iL, DiL is equal

Figure 5 Performance of the developed self-lift circuit




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to DTVin=L, the variation ratio of the currentiL is

6L DiL=2

IL

D

2(M0S)2

R

fL(21)

Since the peak-to-peak current variation ofiL1, DiL1 is equalto DTVCs=L1, the variation ratio of the current iL1 is

6L1 DiL1=2

IL1

D

2M0S

R

fL1(22)

The variation of the currentiDo during switching-off is equalto DiL1, and iDo2off is equal to iL1. Therefore the variationratio of iDo is

jDo 6L1 D

2M0S

R

fL1(23)

The peak-to-peak voltage variation of vo, Dvo is equal toIoDT=Co. Therefore the variation ratio ofvo is

1S0 Dvo=2

Vo

D

2RCo f(24)


The developed self-lift circuit operates in DCM, if thecurrent iDo reduces to zero during switching-off. Thecondition for DCM is jDo ! 1, that is,

jDo D

2M0SZN ! 1 (25)

where ZN is defined as the normalised load R/( fL1).

As a special case, when iDo decrease to zero att T, thecircuit operates at the boundary of CCM and DCM.

Therefore the boundary between CCM and DCM isobtained as below:

ZNB 2MS0

D

2

D(1 D)2

(26)

When ZN . ZN2B, the circuit operates in DCM. Under thiscondition, iDo decreases to zero at t t1 [DmS0 (1 D)]T, where

DT, t1 , T and 0 , mS0 , 1

Here, mS0 is the current filling efficiency for the developedself-lift circuit, and its definition is the same to (12).

In DCM, current iL1 increases during switching-on and

decreases during the period from DT to mS(1 D)T. Thecorresponding voltages across L1 are VCs and(VCo VC1). Thus, using the voltsecond balance

principle, we have

DTVCs mS0 (1 D)T(VCo VC1) or

DT1

1 DVin mS0 (1 D)T Vo

1

1 DVin

(27)

Additionally, the transferred charges ofL1 during switching-off are equal to mS(1 D)TDiL1=2, which compensate thetotal consumed charges of the load. So we have

IoT 1

2mS0 (1 D)TDiL1 or

VoR

T 1

2mS0 (1 D)T

DT

L1

1

1 DVin (28)

Combining (28) and (29), we obtain

mS0 1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1 2D2

ZNp

D(1 D)ZN(29)

From (27), we have

Vo 1

1 D

D

mS0 (1 D)2

" #Vin (30)

Therefore substituting (29) into (30) yields the followingvoltage transfer gain in DCM

MS

0

DCM

1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 2D2ZNp2(1 D)

(31)

Using (18), (26) and(31), we obtain theboundarycurvebetweenCCM and DCM. The voltage transfer gains versus thenormalised load are thus shown in Fig. 5b, which is beneficialfor theoretical analysis and practical engineering design.

4 Re-lift circuit

The re-lift circuit shown in Fig. 6a is derived from thedeveloped re-lift circuit by adding the components(D22 C22D32 L2). The equivalent circuits duringswitching-on, switching-off and DCM are shown inFig. 6b6d respectively. The lift circuit consists ofC12 L12D22 C22D32 L22 S1 and it can be dividedinto two basic VL cells. When switches S and S1 turn on,D1, D2 and D3 are on, Df and Do are off. When S and S1turn off, D1, D2 and D3 are off, Df and Do are on.Capacitors C1 and C2 perform characteristics to lift theoutput capacitor voltage VCo by twice the capacitor voltageVCs. L1 performs the function of a ladder joint to link thetwo capacitors C1 and C2 and liftVCo.


Switching diagrams with main steady-state waveforms areshown in Fig. 7a to analyse the circuit operation, where



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reference directions are referred to in Fig. 6a. As is illustratedin the previous Section 3, we obtain the same formula

VCs 1

1 DVin

During switching-on, both the voltages across C1 and C2 are

equal to VCs. Since C, C1 and C2 are sufficiently large, wehave:

VC1 VC2 VCs 1

1 DVin

The voltage across L1 is equal to VCs during switching-on.With the volt second balance principle, we get

VL1off D

1 DVCs

D

(1 D)2Vin

The inductor current iL2 increases during switching-onand decreases during switching-off. The correspondingvoltages across L2 are VCs and (VCo VC1

VC2 VL1off). Therefore with the sec-voltage balanceprinciple, we have

DTVCs (1 D)T(VCo VC1 VC2 VL1off) or

DT1

1 DVin (1 D)T(Vo

2

1 DVin VL1off)

Hence

Vo 2

(1 D)2Vin

Figure 6 Re-lift Cuk circuit

a Topologyb Equivalent circuit during switching-onc Equivalent circuit during switching-offd Equivalent circuit during DCM

Figure 7 Performance of the re-lift circuit




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The voltage transfer gain in CCM is

MR VoVin

2

(1 D)2(32)

and the input current is

Iin 2

(1 D)2Io IL ICsoff (33)

The charges of both Co increase during switching-off anddecrease during switching-on. Thus, we obtain

QCo IoDT

QCo ICooff(1 D)T

In a switching cycle, QCo QCo2. Therefore

ICooff D1 DIo

During switching-off, iDo iCo io. Therefore

IDooff ICooff Io 1

1 DIo (34)

During switching-off, C1, L1, C2 and L2 form a path andtransfer the stored energy through Do. Therefore

IL1 IL2 IDooff 1

1 DIo (35)

In a switching cycle, DiL is equal to DTVin=L; therefore thevariation ratio of the current iL is

6L DiL=2

IL

D

2M2R

R

fL(36)

Analogously, DiL1 and DiL2 correspond to DTVCs=L1 andDTVCs=L2 respectively. Therefore the variation ratios of iL1and iL2 are

6L1 DiL1=2

IL1

D

2MR

R

fL1

(37)

6L2 DiL2=2

IL2

D

2MR

R

fL2(38)

The variation of the currentiDo during switching-off is equalto DiL2, so the variation ratio of iDo is

jDo 6L2 D

2MR

R

fL2(39)

The peak-to-peak voltage variation of vo, Dvo, is equal toIoDT=Co. Therefore the variation ratio ofvo is

1S Dvo=2

Vo

D

2RCo f(40)

Equations (37) and (38) indicate that the inductor currentvariations during a switching cycle may be different due to theinductance difference. Because L1 and L2 are in series duringswitching-off, the same inductance is thus recommended inpractical circuit design. In reality, although they will beslightly different, it will not affect the normal operation. This

is because the practical inductor current variations (ripple) willbe rather small under the high switching frequency and largeinductance conditions.


From the foregoing explanation, it is assumed that L1 and L2are the same, which can simplify the boundary analysis ofCCM and DCM. The re-lift circuit operates in DCM, ifthe current iDo reduces to zero during switching-off. Thecondition for DCM is jDo ! 1, that is,

jDo D2MRZN ! 1 (41)

As a special case, when iDo decrease to zero at t T, thecircuit operates at the boundary of CCM and DCM.

Therefore the boundary between CCM and DCM isobtained as below:

ZNB 2MR

D

4

D(1 D)2(42)

When ZN . ZN2B, the circuit operates in DCM. Under this

condition, iDo decreases to zero at t

t1

[D mR(12D)]T, where

DT, t1 , T and 0 , mR, 1

Here, mR is the current filling efficiency for the re-lift circuit,and its definition is the same to (12).

In DCM, because current iL2 increases during switching-on and decreases during the period from DTto (12D)mRT,

we thus have

VL2off

D

(1 D)mR VCs

Current iL1 increases during switching-on and decreasesduring the period from DT to mR(12D)T. Thecorresponding voltages across L1 are VCs and (VCoVC1 VC2 VL2off). Thus, using the volt2second balanceprinciple, we have

DTVCs (1 D)mRT(VCo VC1 VC2 VL2off) or

DTVCs (1 D)mRT Vo 2VCs D

(1 D)mRVCs

(43)

Additionally, the transferred charges ofL2 during switching-off are equal to mR(1 D)TDiL2=2, which compensate the



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total consumed charges of the load. So we have

IoT 1

2mR(1 D)TDiL2 or

Vo

R

T 1

2

mR(1 D)TDTVCs

L2

(44)

Combining (43) and (44), we obtain

mR 2 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 D2ZN

pD(1 D)ZN

(45)

From (43), we have

Vo 2 2D

mR(1 D)

VCs (46)

Therefore substituting (45) into (46) yields the followingvoltage transfer gain in DCM

MRDCM 1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 D2ZN

p1 D

(47)

Using (32), (42) and (47), we can obtain the boundary curvebetween CCM and DCM. The voltage transfer gains againstthe normalised load are thus shown in Fig. 7b, which isbeneficial for theoretical analysis and practical engineeringdesign.

5 Multiple-lift circuits

5.1 General analysis

Referring to Fig. 6a, it is possible to construct multiple-liftcircuits by repeatedly adding the components (D22 C22

L22

D3). Assuming that there are n VL cells, thegeneralised multiple-lift circuit is shown in Fig. 8a withreference directions. According to this principle, only twosynchronous switches S and S1 are required for eachcomplex multiple-lift circuit, which simplify the controlscheme and decrease the cost significantly. Hence, eachcircuit has two switches, (n 1) inductors, (n 2)capacitors and (2n 1) diodes.

When switches S and S1 turn on, D1, D2, . . . , D2n21 areon; Df and Do are off. When S and S1 turn off, D1, D2, . . . ,D2n21 are off; Df and Do are on. Capacitors C1, C2, . . . , Cn

lift VCo by n times of VCs. Inductors L1, L2,. . .

Ln performthe same function of a ladder joint to link the adjacentcapacitors. From the foregoing analysis and calculation, thegeneral formulas for all multiple-lift circuits can beobtained according to the similar steps.

The generalised voltage transfer gain is

M n

(1 D)h(n)n 1, 2, 3, 4, . . . (48)

Figure 8 Multiple-lift circuit possessing n voltage-lift cells

a Generalised representationb Boundaries between CCM and DCM against the normalised load ZN (1, elementary self-lift circuit; 2, developed self-lift circuit; 3, re-liftcircuit; 4, triple-lift circuit; 5, quadruple-lift circuit)



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Where

h(n) 1 elementary self-lift2 others

The generalised current of L is

IL n

(1 D)h(n)Io (49)

The generalised jth inductor current is

ILj 1

(1 D)h(n)1Io (50)

The following general analysis is for the developed self-liftcircuit and its corresponding multiple-lift circuits. Thegeneralised variation of the jth inductor current iLj is

6Lj DiLj=2

ILj

D

2M

R

fLj(51)

Analogously, the generalised variation ratio of the outputvoltage vo is

1 Dvo2=2

Vo

D

2RfCo(52)

The generalised variation of the diode current iDo is

jDo D

2M

R

fLN(53)

It is assumed that all inductors existing in the VL cells are thesame. Therefore the generalised boundaries between theCCM and the DCM for all circuits are

ZNB 2M

D

2n

D(1 D)2(54)

The generalised current efficiency is

m n ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffin2 2nD2ZNp

D(1 D)ZN (55)

The generalised voltage transfer gain in DCM is

MDCM n

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffin2 2nD2ZN

p2(1 D)

(56)

If the generalised circuit possesses three VL cells, it is termedthe triple-lift circuit. If the generalised circuit possesses fourVL cells, it is termed the quadruple-lift circuit. The maincharacteristics of these two multiple-lift circuits are given in

Table 1 for ready reference.

The boundaries between CCM and DCM of all proposedcircuits are shown in Fig. 8b. The curves of all MagainstZNindicate that the CCM area increases from the elementaryself-lift circuit via the developed self-lift circuit, the re-liftcircuit, the triple-lift circuit to the quadruple-lift circuit.

There are minimum values of ZN (13.5, 13.5, 27, 40.5 and54) at the boundaries, and all of them are under thecondition of D 1/3. It means that the condition ofD 1/3 is the most possible for these converters to enterDCM. The corresponding extreme points are also markedin Fig. 8b for ready reference.

5.2 Summary of proposed converters

From the foregoing analysis, we can obtain an overview andmain analytical results of proposed VL-type converters.Equation (52) indicates that the output voltage variationratios are determined by the interactions caused by D, R, fand Co. So increasing the capacitance of output capacitor

can effectively improve the output ripper.

In order to show the advantages of proposed circuits overthe conventional Cuk converter, voltage transfer gains Vo/Vin in duty ratio D 0.33, 0.5, 0.75 and 0.8 are listed in

Table 2.

The data in Table 2 indicate that all proposed converterscan obtain higher voltage transfer gains compared with theconventional Cuk prototype. Although both n-cell cascadeconnection converters and transformer-type converters canachieve high voltage transfer gains, their efficiency h

remains low. This is because hof n-cell cascade connectionconverters is given by the product of the efficiencies of each

Table 1 Main characteristics of proposed multiple-lift circuits

Triple-lift circuit Quadruple-lift circuit

M 3/(12 D)2 4/(12 D)2

MDCM (3 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

9 6D2ZN)p

=2(1 D) (2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

4 2D2ZN)p

=(1 D)

ZNB 6/D(12 D)2 8/D(12 D)2

m 3

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi9 6D2ZN

p=D(1 D)ZN 4 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi4 2D2ZN

p=D(1 D)ZN

IL [3/(12

D)

2

]Io [4/(12

D)

2

]Io

ILj, j 1, . . . ,4 [1/(12 D)]Io



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cell belonging to the cascade connection, that is h h1h2 . . .hn. And h of transformer-type converters would belimited by additional losses caused by transformer magneticcharacteristics. Since all proposed converters avoid theseproblems, compact structures with a good efficiency mightbe achieved in the practical manufacture.

5.3 Comparison with negative output

quadratic convertersQuadratic converters are a class of topologies which providethe voltage transfer gains with quadratic dependence on D.

Three negative output quadratic converters proposed in[12] are compared with the VL-type Cuk converters interms of the complexity, voltage transfer gains and voltagestresses, which is tabulated in Table 3. It is seen that the

proposed converters can provide higher voltage transfergains with additional complexity. Additionally, higher

voltage stresses exist in the proposed converters, whichmeans the high-performance semiconductors and controlalgorithm should be used to avoid the componentsdestruction in the practical applications.

6 Case analysis: simulation andexperimental results

To verify the foregoing theoretical analysis results, Psimsimulation package was applied to the proposed converters.

The corresponding hardware testing circuits were alsoconstructed to compare with the simulation results.

Table 3 Comparison between four proposed converters and quadratic converters (voltages are normalised to Vin)

Negative output quadratic

converters [12]

Proposed converters

Elementary self-liftcircuit

Developed self-lift circuit

no. of switch 1 1 2

no. of diode 3 2 3

no. of L 2 2 3

no. of C 2 3 3

M Vo/Vin 2D2/(12 D) 21/(12 D) 21/(12 D)2

stresses of diodes

(VD)

1 or D/(12 D) or 1/(12 D) 1/(12 D) VDf VD1 1/(12 D) andVDo 1/(12 D)

2

stresses of switch(VS)

1/(12 D) 1/(12 D) VS 1/(12 D) and VS1 1/(12 D)2

Table 2 Comparison between four proposed converters and the conventional Cuk converter

Topology Io Vo M Vo/Vin

D 0.33 D 0.5 D 0.75 D 0.8

conventional Cuk prototype Io [(12 D)/D]Iin Vo [D/

(12 D)]Vin

0.5 1 3 4

proposed

converters

elementary self-lift

circuit

Io (12 D)Iin Vo [1/(12 D)]Vin

1.5 2 4 5

developed self-lift

circuit

Io (12 D)2

Iin Vo [1/(12D)2]Vin

2.25 4 16 25

re-lift circuit Io [(12 D)2/

2]Iin

Vo [2/(12 D)

2]Vin

4.5 8 32 50

triple-lift circuit Io [(12 D2)/

3]Iin

Vo [3/(12 D)2]Vin

6.75 12 48 75

quadruple-lift circuit Io [(12 D)2/

4]Iin

Vo [4/

(12 D)2

]Vin

9 16 64 100



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6.1 Simulation and experimental resultsof two self-lift circuits (elementaryand developed)

Referring to Figs. 2aand 4a, both of thesetwocircuits areunderthe same simulation condition that Vin 10 V, R 100V,

L 1 mH, L1 500 mH, Cs 110 mF, C1 22 mF,Co 47 mF, D 0.5 and f 100 kHz. All the diodes andthe switch are ideal. Since simulation is to be performed inCCM, we use (11) and (26) to obtain the boundary values ofnormalised load, ZNBjD0:5. For these two cases, bothZNBjD0:5 are equal to 16. Both the normalised load ZN areequal to 2 and located at the left CCM region of theirboundary curve. Therefore it indicates that the aboveparameters are appropriate for the CCM operation.

According to (2) and (18), we obtain the theoretical outputvoltage values Vo which are equal to 20 V (elementary) and

40 V (developed) respectively. From (9) and (24), theoutput voltage variation ratios 1S and 1S0 are equal to7.5e2 8 and 5.3e2 4 respectively. Therefore the near-zeroripple is achieved. The simulation startup traces are shownin Fig. 9a, where curves 1 and 2 correspond to vo of theelementary self-lift circuit and the developed self-lift circuitrespectively. The simulated responses to the duty ratiodown-step change from 0.5 to 0.4 are shown in Fig. 9b.

The steady-state performance in all simulation cases isidentically matching to the theoretical analysis.

In the hardware testing circuit, we still choose the sameparameters. The n-channel MOSFET 2SK2267 is selectedas the power switches S. The drain-source on resistance is8 mV, which is near the ideal condition. All the diodes arerealised by using MBR6045WT, the forward voltage dropof 0.6 V. Thus, the practical output voltage is smaller thanthe theoretical values due to the effects caused by parasiticparameters. Under the condition of D 0.5, thecorresponding steady-state experimental curves are shownin Fig. 9c. After careful measurement, we obtained that thepractical output voltage value of the elementary self-liftcircuit, Vo1 19 V (shown in Channel 1 with 10 V/Div),and the practical output voltage value of the developed self-lift circuit, Vo2 37 V (shown in Channel 2 with 10 V/

Div). It is seen that the measured results are close to thetheoretical analysis and simulation results. Additionally, theexperimental results of the duty ratio down change from0.5 to 0.4 are shown in Fig. 9d. In Fig. 9d, the oscillationsin these two cases decay in a short time, and the open-looptransient processes are quick in only few milliseconds. Bothof these two cases reach their corresponding new steadystate, which have a good agreement with the simulationresults as shown in Fig. 9b.

6.2 Simulation and experimental resultsof the re-lift circuit

The circuit parameters for simulation are: Vin 10 V,R 100 V, L 1 mH, L1 L2 500 mH, Cs 110 mF,

Figure 9 Simulation and experimental results of the self-lift

circuits (curve/channel 1, elementary; curve/channel 2,developed)

a Simulated startup traces under zero initial conditionsb Simulated response to the duty ratio step change from 0.5 to0.4c Experimental output voltage results of steady-state

performanced Experimental output voltage results of the duty ratio stepchange from 0.5 to 0.4



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C1 C2 22 mF, Co 47 mF, D 0.5 and f 100 kHz.The other assumptions are the same with those forabove-mentioned self-lift circuits. Analogously, we use (42)and obtain the boundary values of normalised load,ZNBjD0:5 32. The normalised load ZN in this case isequal to 2 and located at the left CCM region of the

boundary curve as shown in Fig. 7b. Therefore it indicatesthat above parameters are appropriate for the CCMoperation.

According to (32), we obtain the theoretical value of Vo,which is equal to 80 V. Since the corresponding outputvoltage variation ratio 1 is equal to 5.3e-4 calculated by(40), the near-zero ripple is achieved. The simulatedstartup trace (vo) under zero initial conditions is shown inFig. 10a, and the steady-state performance in thesimulation is identically matching to the theoreticalanalysis. The simulated responses (vo, iL, iL1 and iL2) to

the duty ratio down-step change from 0.5 to 0.4 are shownin Fig. 10b.

The same parameters are chosen to construct a testinghardware circuit. Two n-channel MOSFETs are selected.

All diodes and MOSFETS are the same with thoseadopted in the self-lift circuits. Under the condition ofD 0.5, the corresponding steady-state experimental curveis shown in Fig. 10c. We obtained that the practical output

voltage value Vo 72 V (shown in Channel 1 with 20 V/Div). Considering the power losses, we see that themeasured results are very close to the theoretical analysisand simulation results. Additionally, the experimentalresults of the duty ratio down change from 0.5 to 0.4 areshown in Fig. 10d. The open-loop transient processes arequick in only few milliseconds. The converter reaches thenew steady state, which has a good agreement with thesimulation results as shown in Fig. 10b.

6.3 Transient process and stabilityanalysis

The open-loop transient processes are very quick in only fewmilliseconds as shown in Figs. 9 and 10, and they exhibit thecommon characteristics existing widely in dcdc converters.It is difficult to discuss it in this paper because of thelimitation of papers length. We would like to state thedetailed transient process and circuit stability analysis inother papers.

7 Conclusion

This paper introduced the application and development ofthe VL technique in the design of dcdc power conversioncircuits. A series of novel VL-type Cuk converters has beenproposed using the series Cuk implementing the VL

technique, which can greatly increase the output voltagetransfer gains. The proposed converters overcome theeffects of parasitic parameters and avoid taking too high a

Figure 10 Simulation and experimental results of the re-lift

circuit case

a Simulated startup traces under zero initial conditionsb Simulated response to the duty ratio step change from 0.5 to0.4c Experimental output voltage results of steady-state

performanced Experimental output voltage results of the duty ratio stepchange from 0.5 to 0.4



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value of the duty ratio D. They also have the characteristics ofhigh efficiency, small ripple in simple structures. Theoreticaltopology analysis achieved several important results which areuseful for potential applications. These converters could be

widely used in the areas of computer peripheral circuits,medical equipment, semiconductor industry, especially in

applications with high output voltages. The high-performance semiconductors and advanced controlalgorithm should be helpful to avoid the high stress inthese converters.

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