CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to CMOSIntroduction to CMOSComplementary Metal-Oxide Complementary Metal-Oxide

SemiconductorSemiconductor

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CMOS Logic StructuresCMOS Logic Structures

Static logic circuits hold their output values indefinitely

Dynamic logic circuits store the output in a capacitor, so it decays with time unless it is refreshed.

We will look at a few of these structures

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Pass TransistorsPass TransistorsTransistors can be used as switchesTransistors can be used as switches

g

s d

g = 0

s d

g = 1

s d

0 strong 0

Input Output

1 degraded 1

g

s d

g = 0

s d

g = 1

s d

0 degraded 0

Input Output

strong 1

g = 1

g = 1

g = 0

g = 0

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Pass TransistorPass Transistor

Pass-transistor circuits are formed by dropping the PMOS Pass-transistor circuits are formed by dropping the PMOS transistors and using only NMOS pass transistors transistors and using only NMOS pass transistors

In this case, CMOS inverters (or other means) must be used In this case, CMOS inverters (or other means) must be used periodically to recover the full Vperiodically to recover the full VDDDD level since the NMOS level since the NMOS

pass transistors will provide a Vpass transistors will provide a VOHOH of V of VDDDD – V – VTnTn in some in some

casescases

The pass transistor circuit requires complementary inputs The pass transistor circuit requires complementary inputs and generates complementary outputs to pass on to the next and generates complementary outputs to pass on to the next stagestage

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Pass TransistorPass Transistor

This figure shows a simple This figure shows a simple XNOR implementation XNOR implementation using pass transistors:using pass transistors:

If A is high, B is passed If A is high, B is passed through the gate to the through the gate to the outputoutput

If A is low, -B is passed If A is low, -B is passed through the gate to the through the gate to the outputoutput

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Pass TransistorPass Transistor

At right, At right, (a) is a 2-input NAND pass (a) is a 2-input NAND pass transistor circuittransistor circuit

(b) is a 2-input NOR pass (b) is a 2-input NOR pass transistor circuittransistor circuit

Each circuit requires 8 Each circuit requires 8 transistors, double that transistors, double that required using conventional required using conventional CMOS realizationsCMOS realizations

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Pass TransistorPass Transistor

Pass-transistor logic gate can implement Boolean functions Pass-transistor logic gate can implement Boolean functions NOR, XOR, NAND, AND, and OR depending upon the P1-NOR, XOR, NAND, AND, and OR depending upon the P1-P4 inputs, as shown below.P4 inputs, as shown below.

P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XORP1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XORP1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NANDP1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NANDP1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = ANDP1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = ANDP1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = ORP1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR

Circuit can be operated with clocked P pull-up device or inverter-based latch

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Transmission GatesN-Channel MOS Transistors pass a 0 better than a 1

P-Channel MOS Transistors pass a 1 better than a 0

This is the reason that N-Channel transistors are used in the pull-down network and P-Channel in the pull-up network of a CMOS gate. Otherwise the noise margin would be significantly reduced.

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Transmission GatesA transmission gate is a essentially a switch that connects two points. In order to pass 0’s and 1’s equally well, a pair of transistors (one N-Channel and one P-Channel) are used as shown below:

When s = 1 the two transistors conduct and connect x and yThe top transistor passes x when it is 1 and the bottom transistor passes x when it is 0

When s = 0 the two transistor are cut off disconnecting x and y

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Transmission GatesTransmission GatesPass transistors produce degraded outputsPass transistors produce degraded outputs

Transmission gatesTransmission gates pass both 0 and 1 well pass both 0 and 1 well

g = 0, gb = 1

a b

g = 1, gb = 0

a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a b

g

gb

a b

g

gb

a b

g

gb

g = 1, gb = 0

g = 1, gb = 0

symbols

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Transmission GatesImplementing XOR gates

With NAND gates and inverters:

With transmission gates:

Why would one of these circuits be preferable to the other?

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Transmission GatesImplementing a multiplexer with transmission gates:

When S = 0, input X1 is connected to the output Y

When S = 1, input X2 is connected to the output Y

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Dynamic Domino CMOS LogicDynamic Domino CMOS LogicOne technique to help decrease power in MOS logic One technique to help decrease power in MOS logic circuits is dynamic logiccircuits is dynamic logic

Dynamic logic uses different precharge and Dynamic logic uses different precharge and evaluation phases that are controlled by a system evaluation phases that are controlled by a system clock to eliminate the dc current path in single clock to eliminate the dc current path in single channel logic circuitschannel logic circuits

Early MOS logic required multiphase clocks to Early MOS logic required multiphase clocks to accomplish this, but CMOS logic can be operated accomplish this, but CMOS logic can be operated dynamically with a single clockdynamically with a single clock

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Static NMOSStatic NMOS

Totem-Pole OutputTotem-Pole Outputas we have seen previouslyas we have seen previously

Does not need to be refreshedDoes not need to be refreshedWhich is why it is called staticWhich is why it is called static

PMOS Acts as Constant PMOS Acts as Constant Current Source for Active Current Source for Active Pull-UpPull-Up

Faster rise-times as compared to Faster rise-times as compared to non-CMOS implementationsnon-CMOS implementations input

output

Vdd

ground

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Static CMOSStatic CMOS

Complementary MOSComplementary MOS

Example of a 2-input Example of a 2-input NAND gateNAND gate

Input 1

Input 2

ground

VDD

output

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Dynamic NMOSDynamic NMOS

Output is “1” unless Output is “1” unless dischargeddischarged

ff11 Charges Output Charges Output

ff22 Conditionally Conditionally

Discharges OutputDischarges Outputinput

ground

Vdd

outputf1

f2

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Dynamic Domino CMOS LogicDynamic Domino CMOS LogicThe figure demonstrates the basic concept of domino The figure demonstrates the basic concept of domino CMOS logic operationCMOS logic operation

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Simple Dynamic Domino Logic CircuitSimple Dynamic Domino Logic Circuit

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Dynamic Domino CMOS LogicDynamic Domino CMOS LogicDomino CMOS circuits only produce true logic outputsDomino CMOS circuits only produce true logic outputs

This can be overcome by using registers that have both true This can be overcome by using registers that have both true and complemented output to complete the function shown by and complemented output to complete the function shown by the following circuit:the following circuit: