CSE140L: Digital Systems Laboratory...
Transcript of CSE140L: Digital Systems Laboratory...
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CSE140L: Digital Systems Laboratory
Introduction
Instructor: Mohsen Imani
Slides from:Dr. Pietro Mercati & Prof. Tajana Simunic Rosing
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Welcome to CSE 140L!• Instructor: Mohsen Imani
• Email: [email protected];– please put “CSE140L” in the subject line
• Office Hours:– Mon 2-4pm CSE 2217
• Website: https://cseweb.ucsd.edu/classes/su17_2/cse140L-a/index.html– Homeworks and slides will be here
• TAs and Tutors– Office hours listed on the class website/Piazza
• Discussion sessions: TA will hold both lab and office hour• Grades: https://tritoned.ucsd.edu/• Announcements and online discussion: https://piazza.com SIGN UP SOON !!!
• Lab: TBD
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Course Description• Prerequisites:
– CSE 20 or Math 15A, and CSE 30.– CSE 140 must be taken concurrently
• Objective:– Introduce digital components and system design concepts through
hands-on experience in a lab• Grading:
– Class participation using iClicker: 5%– Homeworks (5): #1: 0%, #2,#3: 10% , #4, #5: 15%– Final: 45%
• Homeworks:– Can be solved individually or in teams of two.– Each homework solution should be checked-off with a
tutor or a TA before the end of the day on the due date– Detailed instructions will be provided on the homework
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Textbook and Recommended Readings• Recommended textbook:
– Contemporary Logic Design byR. Katz & G. Borriello
• Recommended textbook:– Digital Design by F. Vahid
• Lecture slides are derived from theslides designed for both books
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Demo Overview
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Outline• Transistors
– How they work– How to build basic gates out of transistors– How to evaluate delay
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Combinational circuit building blocks:Transistors, gates and timing
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The Scope of CSE140L• We start with Boolean algebra Y = A and B• End up with the design of a simple CPU
Nvidia Tegra 2 die photo
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Switches• Electronic switches are the basis of
binary digital circuits– Electrical terminology
• Voltage: Difference in electric potentialbetween two points
– Analogous to water pressure• Current: Flow of charged particles
– Analogous to water flow• Resistance: Tendency of wire to resist
current flow– Analogous to water pipe diameter
• V = I * R (Ohm’s Law)
4.5 A4.5 A
4.5 A
2 ohms
9V
0V 9V
+–
“Binary Digital” = all values are either 0 (low voltage) or 1 (high voltage)
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The CMOS Switches• CMOS circuit (Complementary – MOS)
– Consists of N and PMOS transistors– Both N and PMOS are similar to basic switches– Rp ~ 2 Rn => PMOS in series is much slower than NMOS
gate
source drainoxide
A positivevoltage here...
...attracts electrons here,turning the channel
between source and draininto aconductor.
(a)
IC package
IC
does notconduct
0
conducts
1gate
nMOS
does notconduct
1gate
pMOS
conducts
0
Silicon -- not quite a conductor or insulator:Semiconductor
1 = high voltage0 = low voltage
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VDD
A Y
GND
N1
P1
NOT
Y = A
A Y0 11 0
A Y
A P1 N1 Y
0
1
Logic gates: CMOS NOT Gate
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CMOS delay: resistance• Resistance:
– Function of:• resistivity r, thickness t : defined by technology• Width W, length L: defined by designer
– Approximate ON transistor with a resistor• R = r’ L/W• L is usually minimum; change only W
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Source: Prof. Subhashish Mitra
gate
source drainoxide
A positivevoltage here...
...attracts electrons here,turning the channel
between source and draininto aconductor.
(a)
IC package
IC
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CMOS delay: capacitance & timing estimates• Capacitor
– Stores charge = (capacitance C; voltage V)
– Current: =• Timing estimate– = = ( / ) =• Delay: time to go from 50% to 50% of waveform
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Source: Prof. Subhashish Mitra
gate
source drainoxide
A positivevoltage here...
...attracts electrons here,turning the channel
between source and draininto aconductor.
(a)
IC package
IC
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Charge/discharge in CMOS• Calculate on resistance• Calculate capacitance of the gates circuit is driving• Get RC delay & use it as an estimate of circuit delay
= ( 1 − − )• Rp ~ 2RN
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Source: Prof. Subhashish Mitra
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A
B
Y
N2N1
P2 P1NAND
Y = AB
A B Y0 0 10 1 11 0 11 1 0
AB Y
A B P1 P2 N1 N2 Y
0 0
0 1
1 0
1 1
CMOS Two Input NAND GateVDD
GND
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A B P1 P2 N1 N2 Y
0 0
0 1
1 0
1 1
CMOS Two Input NOR Gate
a
0
0
1
1
b
0
1
0
1
NOR1
0
0
0
(a+b)’
ab
NOR
P1
P2
N1
b
y
a
a
GND
N2b
GND
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Rules for making gates
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Another way of making CMOS gates
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CMOS Example
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A CMOS design example• Implement F using CMOS: F=A*(B+C’)
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What we’ve covered thus far
• Delay estimates• Transistor design• Building basic gates from CMOS
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