CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System...
-
Upload
shannon-higgins -
Category
Documents
-
view
223 -
download
3
Transcript of CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System...
![Page 1: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/1.jpg)
CSE 241
Computer Engineering (1) )1 (اتالحاسب هندسة
Lecture #3
Ch. 6Memory System Design
Dr. Tamer Samy GaafarDept. of Computer & Systems Engineering
![Page 3: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/3.jpg)
Characteristics of Memory Systems
1. Location2. Capacity3. Unit of transfer4. Access method5. Performance6. Physical type7. Physical characteristics8. Organization
![Page 4: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/4.jpg)
You want it fast?
• It is possible to build a computer which uses only static RAM
• This would be very fast• This would need no cache• This would cost a very large amount
![Page 5: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/5.jpg)
Design Constraints on Memory
• How much?• Capacity: bigger is better!
• How fast?• Time is money.• Best: keep up with CPU.
• How expensive?• Reasonable compared to other components.
• Trade-off among the three characteristics.• Solution: memory hierarchy.
![Page 6: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/6.jpg)
Memory Hierarchy - Diagram
• Less cost• Higher capacity• Greater access time• Less access frequency
• Registers• L1 Cache• L2 Cache• Main
memory• Disk• Optical• Tape
![Page 7: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/7.jpg)
Locality of Reference
CPU
Main memory
![Page 8: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/8.jpg)
Locality of Reference
• During the course of execution of a program, memory references tend to cluster (for both instructions and data).• e.g., loops, subroutines.• e.g., operations on tables and arrays.
• Over a short period of time, CPU is working with fixed clusters of memory references.
• Over a long period of time, the clusters in use change.
• This principle can be applied across all levels of the memory hierarchy.
![Page 9: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/9.jpg)
Cache Memory – Concept
• Small amount of fast memory.• Sits between normal main memory and CPU.• May be located on CPU chip.• Not usually visible to the programmer or CPU• Volatile, uses semiconductor technology.
![Page 10: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/10.jpg)
• CPU requests contents of memory location.• Check cache for this data.• If present cache hit, get from cache (fast).
• Because of locality of reference, this location, or a close one, is likely to be referenced soon.
• If not present cache miss, read required block from main memory to cache.
• Then deliver from cache to CPU.• Cache includes tags to identify which block of
main memory is in each cache slot.
Cache Memory – Operation
![Page 11: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/11.jpg)
Cache – Read Operation
Miss
Hit
![Page 12: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/12.jpg)
Typical Cache Organization
![Page 13: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/13.jpg)
Cache Memory – Design
1. Mapping function2. Replacement algorithm3. Write policy4. Number of caches5. Addresses6. Size7. Block/line size
![Page 14: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/14.jpg)
Cache Memory – Design
1. Mapping function2. Replacement algorithm3. Write policy4. Number of caches5. Addresses6. Size7. Block/line size
![Page 15: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/15.jpg)
Example (running)
• Main memory:—byte-addressable
Each location is 1-byte long.
—16 MBLength of address (s+w) = log2 16M = 24
—4-byte blocks# of blocks (M) = 16M / 4 = 4M
• Cache:—64 KB—4-bytes lines
– # of lines (m) = 64K / 4 = 16K
![Page 16: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/16.jpg)
Block 0
Block 1
Block 2
Block m-1
. . .
. . .
Block m
Block m+1
Block 2m-1
. . .
. . .
Block M-m
Block M-1
. . .
. . .
Block M-m+1
Block M-m+2
. . .
. . .
. . .
Line 0Line 1Line 2
Line m-1
Main memory
Cache memory
Block m+2
Direct Mapping
Each main memory block maps to only one cache line (B modulo m).i.e. if a block is in cache, it must be in one specific place.
![Page 17: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/17.jpg)
Direct Mapping Cache Line Table
Cache line assigned
Main memory blocks
0 0, m, 2m, 3m, …, 2s-m
1 1,m+1, 2m+1, …, 2s-m+1
m-1 m-1, 2m-1, 3m-1, …, 2s-1
…… ………………………….
2 2,m+2, 2m+2, …, 2s-m+2
• m cache lines.• 2s main memory blocks.
![Page 18: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/18.jpg)
MM Address-Block Number Relationship0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
012345678910111213141516
MM
ad
dre
ss
Block 0
Block 1
Block 2
Block 3
![Page 19: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/19.jpg)
MM Address-Line Number-tag Relationship0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:::::::::::::::::::::::::::::::::::::::::::::::::::::::::0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:::::::::::::::::::::::::::::::::::::::::::::::::::::::::0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:::::::::::::::::::::::::::::::::::::::::::::::::::::::::0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1:::::::::::::::::::::::::::::::::::::::::::::::::::::::::0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
01
::::::::::
655356553665537:::::::::
:13107
113107
213107
3:::::::::
:19660
719660
819660
9:::::::::
:26214
326214
4
MM
ad
dre
ss
16 k blocks
16 k blocks
16 k blocks
16 k blocks
Tag = 0
Tag = 1
Tag = 2
Tag = 3
![Page 20: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/20.jpg)
Direct Mapping
• Address is in two parts.
• Least significant w bits identify unique word.
• Most significant s bits specify one memory block.
• The MSBs are split into a cache line field r and a
tag of s-r (most significant).
![Page 21: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/21.jpg)
Direct MappingAddress Structure
Tag s-r Line or Slot r Word w
8 bits 14 bits 2 bits
• 24-bit address• 2-bit word identifier (4 byte block)• 22-bit block identifier
• 14-bit slot or line• 8-bit tag (=22-14)
• No two blocks that map to the same line have the same Tag field
• Check contents of cache by finding line and checking Tag
![Page 22: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/22.jpg)
Direct Mapping Cache Organization
![Page 23: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/23.jpg)
Direct Mapping Example
• Main memory size = 16 MB • Cache size = 64 kB• Block size = 4 bytes
(16339C)16 =
0001 0110 0011 0011 1001 1100
word
0CE7
LineTag
![Page 24: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/24.jpg)
Direct Mapping Summary
• Address length = (s + w) bits.• Number of addressable units = 2s+w words.• Block size = line size = 2w words.
— w = log2 (# of words in block).
• Number of blocks in MM = M = 2s+ w/2w = 2s.— s = log2 (# of words in MM / # of words in block).
• Number of lines in cache = m = 2r.— r = log2 (# of words in cache / # of words in line).
• Size of tag = (s – r) bits.— (s-r) = log2 (# of words in MM / # of words in cache).
![Page 25: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/25.jpg)
Direct Mapping pros & cons
• Simple.• Inexpensive.• Fixed location for given block.
• If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high.
![Page 26: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/26.jpg)
Associative Mapping
• A main memory block can load into any line of cache.
• Memory address is interpreted as tag and word.
• Tag uniquely identifies block of memory.• Every line’s tag is examined for a match.• Cache searching gets expensive.
![Page 27: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/27.jpg)
Associative MappingAddress Structure
• 22 bit tag stored with each 32 bit block of data.
• Compare tag field with tag entry in cache to check for hit.
• Least significant 2 bits of address identify which 1-byte word is required from 32 bit data block.
22 bits 2 bits
Tag s Word w
![Page 28: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/28.jpg)
Fully Associative Cache Organization
![Page 29: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/29.jpg)
Associative Mapping Example
• Main memory size = 16 MB • Cache size = 64 kB• Block size = 4 bytes
(16339C)16 =
0001 0110 0011 0011 1001 1100
word
058CE7
Tag
![Page 30: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/30.jpg)
Associative Mapping Summary
• Address length = (s + w) bits.• Number of addressable units = 2s+w words.• Block size = line size = 2w words.
— w = log2 (# of words in block).
• Number of blocks in MM = M = 2s+ w/2w = 2s.— s = log2 (# of words in MM / # of words in block).
• Number of lines in cache = m = undetermined.• Size of tag = s bits.
![Page 31: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/31.jpg)
Set-Associative Mapping
• Cache is divided into a number of sets (v) of equal size.
• Each set contains a number of lines (k).k-way set-associative mapping!
• A block b could map to any line in a set i if and only if i = b modulo v.
![Page 32: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/32.jpg)
Block 0
Block 1
Block 2
Block m-1
. . .
. . .
Block m
Block m+1
Block 2m-1
. . .
. . .
Block M-m
Block M-1
. . .
. . .
Block M-m+1
Block M-m+2
. . .
. . .
. . .
Main memory
Cache memory
Block m+2
Set-Associative Mapping
Set 0
Set 1
Set 2
Set v-1
………….......………….......………….......4-way set associative mapping
![Page 33: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/33.jpg)
Example (running)
• Main memory:—byte-addressable
Each location is 1-byte long.
—16 MBLength of address (s+w) = log2 16M = 24
—4-byte blocks# of blocks (M) = 16M / 4 = 4M
• Cache:—64 KB—4-byte lines
– # of lines (m) = 64K / 4 = 16K
—2-line sets k=2 2-way set-associative– # of sets (v) = 16K / 2 = 8K
![Page 34: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/34.jpg)
Set Associative MappingAddress Structure
• Use set field to determine cache set to look in.
• Compare tag field to see if we have a hit.
9 bits 13 bits 2 bits
Tag s-d Set d Word w
![Page 35: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/35.jpg)
k-Way Set Associative Cache
![Page 36: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/36.jpg)
Two-Way Set Associative Mapping - Example
• Main memory size = 16 MB • Cache size = 64 kB• Block size = 4 bytes• 2-way set associative mapping
![Page 37: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/37.jpg)
Set Associative Mapping Summary
• Address length = (s + w) bits.• Number of addressable units = 2s+w words.• Block size = line size = 2w words.
— w = log2 (# of words in block).
• Number of blocks in MM = M = 2s.— s = log2 (# of words in MM / # of words in block).
• Number of lines in set = k k-way set-associative• Number of sets = v = 2d.• Number of lines in cache = m = k * v = k * 2d.
— d = log2 (# of words in cache / # of words in set).
• Size of tag = (s – d) bits.— (s-d) = log2 (# of blocks in MM / # of sets in cache).
![Page 38: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/38.jpg)
Cache Memory – Design
1. Mapping function2. Replacement algorithm3. Write policy4. Number of caches5. Addresses6. Size7. Block/line size
![Page 39: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/39.jpg)
Replacement Algorithms (1)Direct mapping
• No choice.
• Each block only maps to one line.
• Replace that line.
![Page 40: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/40.jpg)
• Hardware implemented algorithm (speed)
• Least Recently Used (LRU)• e.g. in 2-way set associative: which of the 2 blocks is LRU?
• First In First Out (FIFO)• Replace block that has been in cache longest.
• Least Frequently Used• Replace block which has had fewest hits.
• Random
Replacement Algorithms (2)Associative and Set Associative
![Page 41: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/41.jpg)
Cache Memory – Design
1. Mapping function2. Replacement algorithm3. Write policy4. Number of caches5. Addresses6. Size7. Block/line size
![Page 42: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/42.jpg)
Write Policy – Multiple CPU Organization
• Several CPUs sharing the same MM, each has its own cache memory.
Main Memory
Cache 1
Cache 2
CPU 1
CPU 2
Cache nCPU n
::
![Page 43: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/43.jpg)
Write Policy – Constraints
• Multiple CPUs may have individual caches.
• I/O may access main memory directly.• Must not overwrite a cache block
unless main memory is up to date.
![Page 44: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/44.jpg)
Write through
• All writes go to main memory as well as cache.
• Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date.
• Lots of traffic.
• Slows down writes.
![Page 45: CSE 241 Computer Engineering (1) هندسة الحاسبات (1) Lecture #3 Ch. 6 Memory System Design Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.](https://reader036.fdocuments.net/reader036/viewer/2022062408/56649f295503460f94c430b7/html5/thumbnails/45.jpg)
Write back
• Updates initially made in cache only.• Update bit for cache line is set when
update occurs• If block is to be replaced, write to main
memory only if update bit is set.• Other caches get out of sync.• I/O must access main memory through
cache.• N.B. 15% of memory references are writes