CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are...

CSCI-365Computer Organization

Lecture

Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson & Hennessy, ©2005 Some slides and/or pictures in the following are adapted from: slides ©2008 UCB

Chapter 4

Truth Tables Uniquely Define CL Function

Truth Table

• A truth table defines the outputs of a logic block for each set of inputs– E.g., Consider a block with 3 inputs A, B, C and an output E that

is true only if exactly 2 inputs are true (DONE IN CLASS)

Logic Gates

2-input gates extend to n-inputs

• N-input XOR is the only one which isn’t so obvious

• It’s simple: XOR is a 1 iff the # of 1s at its input is odd

Boolean Algebra

• George Boole, 19th Century mathematician

• Developed a mathematical system (algebra)

involving logic– later known as “Boolean Algebra”

• Primitive functions: AND, OR and NOT

• The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA

+ means OR,• means AND, x means NOT

Canonical Forms

• Sum of products

Laws of Boolean Algebra

BA: Circuit & Algebraic Simplification

BA also great for circuit verificationCirc X = Circ Y?use BA to prove!

Canonical Forms

Truth Table Gates (e.g., majority circ.)

(DONE IN CLASS)

Common Logic Blocks - Multiplexor

• Multiplexor or selector: one of N inputs is reflected on the output depending on the value of the log2N selector bits. E.g., 2-input mux

Takes in N inputs and activates one of 2N outputs

I0 I1 O0 O1 O2 O3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

2-to-4Decoder

I0O0

Common Logic Blocks - Decoder

I1

O1

O2

O3

2-4 Decoder

(DONE IN CLASS)

Arithmetic and Logic Unit

• Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU)


• A common way to implement the ALU is to provide a CL block for each of the possible ALU functions– The inputs, A and B, get distributed to all the blocks

– The output of the proper block is selected with a mux

– Every function of the ALU is computed internally to the ALU on every cycle, but only one of the results is sent to the output


• The logical operations as defined by the MIPS ISA are bitwise operations– In the case of AND, the resultant bit ri is generated as

ai AND bi. The circuit to perform this operation is

simply a collection of 32 AND gates

– Similarly, the OR block is a collection of 32 OR gates

• The add/subtract block is significantly more complex

Adder/Subtracter Design -- how?

• Truth-table, then determine canonical form, then minimize and implement as we’ve seen before– This technique is only effective for very narrow

adders, truth table too large for wider adders

• Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer– We will design the smaller pieces individually, then

wire them together to create entire wide adder

1-Bit Adder

(DONE IN CLASS)

Multiplexor selects between ADD, OR, AND operations

1-Bit ALU with ADD, OR, AND

1-bit ALUs are connected “in series” with the carry-out of 1 box going into the carry-in of the next box

32-Bit Ripple Carry Adder

Must invert bits of B and add a 1• Include an inverter• CarryIn for the first bit is 1• The CarryIn signal (for the first bit) can be the same as the Binvert signal

Incorporating Subtraction

Incorporating NOR

• Perform a – b and check the sign

• New signal (Less) that is zero for ALU boxes 1-31

• The 31st box has a unit to detect overflow and sign – the sign bit serves as the Less signal for the 0th box

Incorporating SLT

• Perform a – b and confirm that the result is all zero’s

Incorporating BEQ

ALU

§4.4 A Sim

ple Implem

entation Scheme

ALU control Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set-on-less-than

1100 NOR

Processor

Computer

Control

Datapath

Memory(passive)

(where programs, data live whenrunning)

DevicesInput

Output

Keyboard, Mouse

Display, Printer

Disk (where programs, data live when not running)

Five Components of a Computer

• Processor (CPU): the active part of the computer, which does all the work (data manipulation and decision-making)– Datapath: portion of the processor which contains

hardware necessary to perform operations required by the processor (the brawn)

– Control: portion of the processor (also in hardware) which tells the datapath what needs to be done (the brain)

The CPU

The CPU

• Our implementation of the MIPS is simplified– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt– control flow instructions: beq, j

• Generic implementation– use the program counter (PC) to supply the

instruction address and fetch the instruction from memory (and update the PC)

– decode the instruction (and read registers)

– execute the instruction

• All instructions (except j) use the ALU after reading the registers

FetchPC = PC+4

DecodeExec

Fetching Instructions

• Fetching instructions involves– reading the instruction from

the Instruction Memory

– updating the PC to hold the address of the next instruction

– PC is updated every cycle, so it does not need an explicit write control signal

– Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Decoding Instructions

• Decoding instructions involves– sending the fetched instruction’s opcode and function

field bits to the control unit– reading two values from the Register File

• Register File addresses are contained in the instruction

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ControlUnit

Executing R Format Operations

• R format operations (add,sub,slt,and,or)

– perform the (op and funct) operation on values in rs and rt

– store the result back into the Register File (into location rd)

– The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File

R-type:31 25 20 15 5 0

op rs rt rd functshamt

10

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

overflowzero

ALU controlRegWrite

Executing Load and Store Operations

• Load and store operations involve– compute memory address by adding the base register (read from the Register

File during decode) to the 16-bit signed-extended offset field in the instruction– store value (read from the Register File during decode) written to the Data

Memory– load value, read from the Data Memory, written to the Register File

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

overflowzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

SignExtend

MemWrite

MemRead16 32

Executing Branch Operations

• Branch operations involves– compare the operands read from

the Register File during decode for equality (zero ALU output)

– compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

zero

ALU control

SignExtend16 32

Shiftleft 2

Add

4 Add

PC

Branchtargetaddress

(to branch control logic)

Executing Jump Operations

• Jump operation involves– replace the lower 28 bits of the PC with the lower 26 bits of the

fetched instruction shifted left by 2 bits

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Shiftleft 2

Jumpaddress

26

4

28

Creating a Single Datapath from the Parts

• Assemble the datapath segments and add control lines and multiplexors as needed

• Single cycle design – fetch, decode and execute each instructions in one clock cycle– no datapath resource can be used more than once per

instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders)

– multiplexors needed at the input of shared elements with control lines to do the selection

– write signals to control writing to the Register File and Data Memory

• Cycle time is determined by length of the longest path

ALU Control• ALU used for

– Load/Store: F = add

– Branch: F = subtract

– R-type: F depends on funct field

ALU control Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set-on-less-than

1100 NOR

ALU Control

• Assume 2-bit ALUOp derived from opcode– Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010

sw 00 store word XXXXXX add 0010

beq 01 branch equal XXXXXX subtract 0110

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110

AND 100100 AND 0000

OR 100101 OR 0001

set-on-less-than 101010 set-on-less-than 0111

The Main Control Unit Control signals derived from instruction

0 rs rt rd shamt funct31:26 5:025:21 20:16 15:11 10:6

35 or 43 rs rt address31:26 25:21 20:16 15:0

4 rs rt address31:26 25:21 20:16 15:0

R-type

Load/Store

Branch

opcode always read

read, except for load

write for R-type

and load

sign-extend and add

Single Cycle Datapath with Control Unit

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

10

00

0

1

ALUOp

Instr[5-0]

Instr[5-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]Branch

R-type Instruction Data/Control Flow

ReadAddress Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

10

0 0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]Branch

Load Word Instruction Data/Control Flow

Store Word

Instruction?

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]Branch

Branch Instruction Data/Control Flow

Jump Operation?

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26

PC+4[31-28]

28

Adding the Jump Operation

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

Can the Control Unit set all the control signals based solely on the opcode field of the instruction?

Single Cycle Disadvantages & Advantages

• Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction– especially problematic for more complex instructions like floating

point multiply

• May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle

but• Is simple and easy to understand

Clk

lw sw Waste

Cycle 1 Cycle 2

Where we are headed

• Single Cycle Problems:– what if we had a more complicated instruction like floating point?

– wasteful of area

• One Solution:– use a “smaller” cycle time

– have different instructions take different numbers of cycles

– a “multicycle” datapath

Multicycle Datapath

• Break up the instructions into steps, each step takes a cycle

• Assume the clock cycle can accommodate at most one of the following operations– a memory access– a register file access (two reads or one write)– an ALU operation

• At the end of a cycle– store values for use in later cycles (easiest thing to do)– introduce additional “internal” registers

• At the end of a cycle– Store values needed in a later cycle by the current instruction in an internal register

(not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed)

IR – Instruction Register MDR – Memory Data RegisterA, B – regfile read data registers ALUout – ALU output register

Multicycle Datapath

AddressRead Data

(Instr. or Data)

Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB A

LUou

t

– Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory)

Multicycle Datapath

• Several functional units are shared for different purposes– Need to add multiplexors

– Need to expand existing multiplexors

The Multicycle Datapath with Control Signals

Address

Read Data(Instr. or Data)

MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Five Execution Steps

• Five execution steps– Instruction Fetch

– Instruction Decode and Register Fetch

– Execution, Memory Address Computation, or Branch Completion

– Memory Access or R-type instruction completion

– Write-back step

• Instructions take from 3-5 cycles

Step 1: Instruction Fetch

• Use PC to get instruction and put it in IR

• Increment PC by 4 and put result back in PC

IR <= Memory[PC];PC <= PC + 4;

• What is the advantage of updating the PC now?

Step 1 Control Signals

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 2: Instruction Decode and Register Fetch• We don’t know yet what the instruction is

– Read registers rs and rt in case we need them

– Compute the branch address in case the instruction is a branch

A <= Reg[IR[25:21]];B <= Reg[IR[20:16]];ALUOut <= PC + (sign-extend(IR[15:0]) << 2);

• We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

Step 2 Control Signals

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 3 (instruction dependent)

• ALU is performing one of three functions, based on instruction type– Memory Reference

ALUOut <= A + sign-extend(IR[15:0]);

– R-typeALUOut <= A op B;

– Branchif (A==B) PC <= ALUOut;

– Jump

PC <= {PC[31:28], (IR[25:0],2’b00)};

Step 3 (Memory Reference)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 3 (R-type)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 3 (Branch)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 3 (Jump)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 4 (R-type or memory-access)

• Loads and stores access memoryMDR <= Memory[ALUOut];

or

Memory[ALUOut] <= B;

• R-type instructions finish

Reg[IR[15:11]] <= ALUOut;

Step 4 (Loads access memory)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 4 (Stores access memory)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Step 4 (R-type instructions finish)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

• Reg[IR[20:16]] <= MDR;

Which instruction needs this?

Step 5 (write-back)

Step 5 (write-back)

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

Multicycle Control Unit

Address


MemoryPC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

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Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28

CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are...

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Transcript of CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are...