CS2420_lec1

download CS2420_lec1

of 12

  • date post

    07-Sep-2014
  • Category

    Documents

  • view

    114
  • download

    0

Embed Size (px)

Transcript of CS2420_lec1

CS 2420: DIGITAL LOGICLecture 1: Course Description Instructor: Dr. Yijuan (Lucy) Lu

WELCOME

TO

CS2420: DIGITAL LOGIC

Instructor: Dr. Yijuan (Lucy) Lu Nueces building (office# 270) Tel: 512-245-6580 E-mail: yl12@txstate.edu WWW: http://www.cs.txstate.edu/Personnel/yl12 My research field: Multimedia Information Retrieval Machine Learning and Data Mining Statistical Learning Pattern Recognition Computer Vision Bioinformatics

MY GOALS FOR YOU

To understand logic and gates To understand combinational logic design

To understand sequential logic designTo understand basic computer components To understand basic computer architecture

HOW WILL THESE GOALS BE ACHIEVED?

Of course lectures and homeworkImplementation labs and projects Attendance is strongly recommended. Office hours: Tu, Th, 1:00 3:30 pm After the class or other time-by appointments Nueces building (office# 270)

COURSE TEXT

M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, 4th edition, Prentice Hall, 2008. Digital Design, 4th edition M. Morris Mano and Michael D. Ciletti, Pearson Prentice Hall, 2007

Class Notes

COURSE CONTENT

Digital circuit basics Number systems Boolean logic and logic gates Logic function optimization Arithmetic circuits Combinational logic circuits Sequential logic concepts and circuits Synchronous sequential logic design Finite state machine design Arithmetic state machine design Memory circuits Arithmetic logic unit (ALU) Basic computer architectures

LEARNING OBJECTIVES

Basic understanding of electricity [HS physics level] Rudimentary information. On semiconductors and CMOS technology. Relation to digital logic. Introduction to digital logic design: logic and gates, combinational logic design, sequential logic design, FSMs, registers (counters and shift registers), PLA-type devices, what clock does, basic computer components and basic computer architecture Communications concept: parallel & serial transmission, asynchronous and synchronous communication, rudiments of information theory

GRADING POLICY

Homework 25% Quiz 5%

MidtermFinal Lab

20% 20% 30%

HOMEWORK

One homework every two weeks: You may discuss these among yourselves but you must do your own homework

Clarity of exposition of the solutions is requiredLate homework will not be graded for credit.

LAB AND PROJECT

Nine labs and one project Must attend a designated lab (Counts 30% of your grade).

For details on the labs, go to the department web site www.cs.txstate.edu and follow the Lab links for more information, as the lab schedules begin. Lab instructor: Conrad Miller (Conrad@cs.txstate.edu) Sheetal Gampa (sheetal@cs.txstate.edu)

TESTS

Two exams (in-class) One midterm to be held during class hours One final during final week

Tests will be open-note close-bookTests will be based on reading assignments, homework, and project Without prior arrangements, missed exam results in a grade of zero.

OTHERS

All detailed information is put on the Tracs: https://tracs.txstate.edu/portal/login Check the announcement, assignment, resources, messages and calendar on the Trancs and also your email.