CS222: Concluding Class
Transcript of CS222: Concluding Class
CS222: Concluding ClassCS222: Concluding Class
Dr. A. Sahu
Dept of Comp. Sc. & Engg.Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
• Course Covered
• End Semester Exam
• Advanced TopicAdvanced Topic
• Job Prospects
C f db k• Course feedback
• Last Class – I/O Controller: PPC, PIT, PIC, DMA
Course CoveredCourse Covered• Instruction Set Architecture, MIPS ALP, RISC/CISC• ALU Design: Adder Algorithm, multiplier, divider,ALU Design: Adder Algorithm, multiplier, divider, Floating point operations
• CPU Design: Single Cycle Data Path & Control, l l h & l hMulti‐Cycle Data Path & Control Path
Ad d CPU D i Pi li H d D t• Advanced CPU Design: Pipeline, Hazards, Data forwarding, Branch Processing, Superscalar designg
• Memory Hierarchy: Cache, Cache Performance Optimizations, Disk, Memory, Virtual Memory IO O i i B i i f h d l• IO Organizations: Basic interface methodology: Interrupt, PIT, PPC,DMA
End Semester ExamEnd Semester Exam
• 6 Questions: 2 easy 2 Ok 2 difficult6 Questions: 2 easy, 2 Ok, 2 difficult
• Close book
b h h d i l• Expect both theory part and numerical problems in questions
• Syllabus: After Mid Semester Exam
Advanced TopicAdvanced Topic
• Advance Computer ArchitectureAdvance Computer Architecture• VLSI Algorithm and IC Design• Embedded System• Embedded System• Real Time SystemHi h P f S t• High Performance System
• Reconfigurable Computing and FPGA• Operating System • GPU Arciecture
Job ProspectsJob Prospects
• IntelIntel
• AMD
idi• Nvidia
• Freescale
• Mamga
• CadenceCadence
• Google HPC
Course FeedbackCourse Feedback
• Today Class at 10 40Today Class at 10.40..
• Fill in the form and Submit to Prabin Bhorali
• Designed to perform various I/O functionsDesigned to perform various I/O functions
• Device can be setup to perform specific functionsfunctions – By writing instruction to a internal register
• Can be changed during execution of the program
• Devices are flexible, versatile & economical
• Functions are determined by softwareFunctions are determined by software instructions
• Can be viewed asmultiple I/O deviceCan be viewed as multiple I/O device• Perform many functions
– Time delay counting interruptsTime delay, counting, interrupts
• Consists of many devices on a chip, interconnect through a common Businterconnect through a common Bus
• Software programmable approach of I/O reduce design timereduce design time
• The 8254 Programmable Interval‐timer is usedThe 8254 Programmable Interval timer is used by the PC system for – Generating timer‐tick interrupts (rate is 18.2 per g p ( psec),
– Performing dynamic memory‐refresh (reads ram 15 i d ) donce every 15 microseconds), and
– Generates ‘beeps’ of PC speaker
Wh th k f ti i ’t d d th• When the speaker‐function isn’t needed, the 8254 is available for other purposes
Brief 8255 PPCBrief 8255 PPC
• Increase I/O PortsIncrease I/O Ports
• Programmable port
3• 3 Port
• 3 Modes (0, 1, 2)
• One Bi drectional port
Block Diagram of 8255
Gr A I/O
Block Diagram of 8255CSb A1 A0 Sel
0 0 0 Port A
Group AControl
Gr APort A(8)
I/O PA7‐PA00 0 1 Port B
0 1 0 Port C
0 1 1 CRW
DataBus
Gr APort C(H 4)
I/O PC7‐PC4Bi directional
Data BusD7 D0
0 1 1 CRW
Buffer Gr BPort C(L 4)
I/O PC3‐PC0
8 bit Internal Data Bus
D7‐D0
b
Group BControl
ReadWriteControl Logic
Gr BPort B(8)
I/O PB7‐PB0
RDb
WRb
A1A0
Logic RESET
CSb
Ports & Modes in 8255 : Control registerPorts & Modes in 8255 : Control register
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0D7 D6 D5 D4 D3 D2 D1 D0
Port C(L) – 1 Input
Group B
Mode select: 0 mode 0; 1 mode 1
Port B – 1 Input 0 output
0 output
Port C(U) – 1 Input 0 output
Mode select: 0 mode 0; 1 mode 1
Port A – 1 Input 0 output
Mode select: 00 mode 0; 01 mode 1; 0x mode 2
1 – mode select 0 – bit set/reset
Group A
Operation modes: 0, 1, 2p , ,• Mode 0: Basic input‐output
bi d bi‐ two 8‐bit ports and two 4‐bit ports‐ any port can be input or output
Outputs are latched inputs are not latched‐ Outputs are latched, inputs are not latched
• Mode 1: strobed input‐outputth t di id d i t tthree ports are divided into two groups
‐each group contains one 8‐bit port and one 4‐bit control/data portp
‐ 8‐bit port can be either input or output and both latched
‐ 4‐bit port used for control and status of 8‐bit data port
• Mode 2: Bi directional mode
• Use Interrupt as generalized mechanism toUse Interrupt as generalized mechanism to connect
• Use priority resolver to connect them• Use priority resolver to connect them
• Arbitration done by peripherals– Built into peripheral or external logic addedp p g
• req input and ack output added to each peripheral
• Peripherals connected to each other in daisy‐chain manner– One peripheral connected to resource, all others connected “upstream”– Peripheral’s req flows “downstream” to resource, resource’s ack flows “upstream” to
requesting peripheral– Closest peripheral has highest priority
μPSystem bus
Int
IntaPeripheral1
Ack_in Ack_outReq_out Req_in
Peripheral2
Ack_in Ack_outReq_out Req_in 0
Daisy‐chain aware peripherals
Micro‐processor
System bus
Priority arbiter
Peripheral1
System bus
Int3
57
IntaPeripheral2
Ireq1 2 2Ireq1
Iack2
Iack1Ireq2
2 2
6
Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2.
Priority arbiter sees at least one Ireq input asserted so asserts IntPriority arbiter sees at least one Ireq input asserted, so asserts Int.Microprocessor stops executing its program and stores its state.Microprocessor asserts Inta. Priority arbiter asserts Iack1 to acknowledge
Peripheral1.Peripheral1.Peripheral1 puts its interrupt address vector on the system busMicroprocessor jumps to the address of ISR read from data bus, ISR executes and
returns
• Pros/consE dd/ i h l– Easy to add/remove peripheral ‐ no system redesign needed
D t t t ti i it– Does not support rotating priority
– One broken peripheral can cause loss of access to other peripheralsother peripherals
μPSystem bus
Micro‐processor
System bus
Int
IntaPeripheral1
Ack_in Ack_outReq_out
Req_in
Peripheral2
Ack_in Ack_outReq_ou
tReq_in 0
Priority arbiter
Peripheral1
System bus
Int
IntaPeripheral2
Ireq1
Iack1 t t
Daisy‐chain aware peripheralsIack2
Ireq2
• Interrupts alter a program’s flow of controlte upts a te a p og a s o o co t o– Behavior is similar to a procedure call
• Some significant differences between the two
• Interrupt causes transfer of control to an interrupt service routine (ISR)
ISR i l ll d h dl• ISR is also called a handler
• When the ISR is completed, the original program resumes executionresumes execution
• Interrupts are used to interface I/Os• Interrupts provide an efficient way to handle• Interrupts provide an efficient way to handle unanticipated events
• Tool/IC for managing the interrupt requests.
• 8259 is a very flexible peripheral controller chip:8 59 is a very flexible peripheral controller chip:– PIC can deal with up to 64 interrupt inputs
– interrupts can be masked
– various priority schemes can also programmed.
• originally (in PC XT) it is available as a separate IC
• Later the functionality of (two PICs) is in the motherboards chipset.
• In some of the modern processors, the functionality of the PIC is built in.
IRQ0IRQ0
IRQ1
IRQ2
INTR
CPU
8259 Programmable
Interrupt Controller
Q
IRQ3
IRQ4
INTA
Controller IRQ5
IRQ6
IRQ78 bitData Bus
INTAb INT
Control Logic
Interrupt S i
Priority Interrupt R t
IRQ0IRQ1IRQ2IRQ3Service
Register
yResolver
Request Register
IRQ3IRQ4IRQ5IRQ6IRQ7
Interrupt Mask Register
Internal Bus
• 8259 can service up to eight hardware devices8 59 ca se ce up to e g t a d a e de ces– Interrupts are received on IRQ0 through IRQ7
• 8259 can be programmed to assign priorities in p g g pseveral ways– Fixed priority scheme is used in the PC
• IRQ0 has the highest priority and IRQ7 lowest
• 8259 has two registersI t t C d R i t (ICR)– Interrupt Command Register (ICR)
• Used to program 8259
– Interrupt Mask Register (IMR)p g ( )
Priority ModesPriority Modes
• Fully Nested Modes– IR are arranged in IR0‐IR7 and Any IR can be assigned Highest or lowest priority IR4=0 (high), IR3=7 (low)
• Automatics Rotation ModeAutomatics Rotation Mode– A device after being served, receive the lowest priority with value 7 01234567 12345670 23456701
• Specific Rotation Mode• Specific Rotation Mode– User can select any IR for lowest priority
• EOI: End of interrupt– Specific EOI Command– Automatic EOI: no command necessary– Non‐Specific EOI: it reset the ISR bitNon Specific EOI: it reset the ISR bit
Direct Memory Access(DMA)(DMA)
DMACPU
DMA ControllerCPU
System Bus System Bus
M I/O
System Bus
Memory I/O
System Bus
Memory I/O Memory I/O
• HOLD: DMA to CPU– DMA Send HOLD High to CPU g– I (DMA) want BUS Cycles
• HOLDA– CPU send HOLDA– BUS is granted to DMA to do the transfer– DMA is from Slaves to Master modeDMA is from Slaves to Master mode
• HOLD Low to CPU – I (DMA) finished the transfer( )
• Cycle Stealing if One BUS • Other wise Separate process independent of
iprocessing
• Processor initiates the DMA controller – Gives device number, memory buffer pointer,Gives device number, memory buffer pointer, …
Called channel initialization– Once initialized, it is ready for data transfer
• When ready, I/O device informs the DMA controller – DMA controller starts the data transfer processDMA controller starts the data transfer process
» Obtains bus by going through bus arbitration» Places memory address and appropriate control signals» Completes transfer and releases the busp» Updates memory address and count value» If more to read, loops back to repeat the process
• Notify the processor when doneNotify the processor when done– Typically uses an interrupt
• Enable/Disable control of Individual DMA ReqEnable/Disable control of Individual DMA Req• Four Independent DMA Channel• Independent Auto initialization for all channel• Independent Auto initialization for all channel• Memory to Memory transferM Bl k i iti li ti• Memory Block initialization
• Address Increment and Decrement • Cascade (Directly expandable to any #CHN)• End of Process input for terminating transfers• Software DMA requests
DMA Request 0To data Bus
DREQ0DB0‐DB7
DMA Request 0DMA Request 1DMA Request 2DMA Request 3
Address Strobe
To Address Bus
DREQ0DREQ1DREQ2DREQ3
A0‐A3A4‐A7
ADSTB
Hold Ack
Address StrobeHold request
DMA ack0DMA k1
HLDA
ADSTBHOLD
DACK0DACK1
Clock
DMA ack1DMA ack2DMA ack3CLK
DACK1DACK2DACK3
ResetReady
Chip Select
IO Read I/O WriteMemory ReadMemory Write
RESETREADY
CSb
IORDb
IOWRb
MemRDb
MemWRbChip Select Memory Write
End of Process
CSb MemWRb
EOPb