CS152 Lec10.1 CS 152 Computer Architecture and Engineering Lecture 10 Designing a Multicycle...

CS152Lec10.1

CS 152Computer Architecture and Engineering

Lecture 10

Designing a Multicycle Processor

CS152Lec10.2

Recap: Processor Design is a Process

° Bottom-up• assemble components in target technology to establish critical

timing

° Top-down• specify component behavior from high-level requirements

° Iterative refinement• establish partial solution, expand and improve

datapath control

processorInstruction SetArchitecture

Reg. File Mux ALU Reg Mem Decoder Sequencer

Cells Gates

CS152Lec10.3

Recap: A Single Cycle Datapath

32

ALUctr

Clk

busW

RegWr

32

32

busA

32

busB

55 5

Rw Ra Rb

32 32-bitRegisters

Rs

Rt

Rt

RdRegDst

Exten

der

Mu

x

Mux

3216imm16

ALUSrc

ExtOp

Mu

x

MemtoReg

Clk

Data InWrEn

32

Adr

DataMemory

32

MemWr

AL

U

InstructionFetch Unit

Clk

Equal

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

CS152Lec10.4

Recap: The “Truth Table” for the Main Control

R-type ori lw sw beq jump

RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

Branch

Jump

ExtOp

ALUop (Symbolic)

1

0

0

1

0

0

0

x

“R-type”

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

0

1

x

xxx

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

ALUop <2> 1 0 0 0 0 x

ALUop <1> 0 1 0 0 0 x

ALUop <0> 0 0 0 0 1 x

MainControl

op

6

ALUControl(Local)

func

3

6

ALUop

ALUctr

3

RegDst

ALUSrc

:

CS152Lec10.5

Recap: PLA Implementation of the Main Control

op<0>

op<5>. .op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

op<5>. .<0>

R-type ori lw sw beq jumpRegWrite

ALUSrc

MemtoReg

MemWrite

Branch

Jump

RegDst

ExtOp

ALUop<2>

ALUop<1>

ALUop<0>

CS152Lec10.6

Recap: Systematic Generation of Control

° In our single-cycle processor, each instruction is realized by exactly one control command or “microinstruction”

• in general, the controller is a finite state machine

• microinstruction can also control sequencing (see later)

Control Logic / Store(PLA, ROM)

OPcode

Datapath

Inst

ruct

ion

Decode

Con

ditio

nsControlPoints

microinstruction

CS152Lec10.7

The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

° Today’s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath

Control

Datapath

Memory

Processor

Input

Output

CS152Lec10.8

Behavioral models of Datapath Componentsentity adder16 is

generic (ccOut_delay : TIME := 12 ns; adderOut_delay: TIME := 12 ns);port(A, B: in std_logic_vector (15 downto 0); DOUT: out std_logic_vector (15 downto 0); CIN: in std_logic; COUT: out std_logic);end adder16;

architecture behavior of adder32 isbegin

adder16_process: process(A, B, CIN)

variable tmp : std_logic_vector (18 downto 0);variable adder_out : std_logic_vector (31 downto 0);variable carry: std_logic;

begintmp := addum (addum (A, B), CIN);

adder_out := tmp(15 downto 0);carry :=tmp(16);

COUT <= carry after ccOut_delay; DOUT <= adder_out after adderOut_delay; end process;end behavior;

16

1616

A B

DOUT

CinCout

CS152Lec10.9

Behavioral Specification of Control Logic

° Decode / Control-store address modeled by Case statement

° Each arm of case drives control signals for that operation• just like the microinstruction

• either can be symbolic

entity maincontrol isport(opcode: in std_logic_vector (5 downto 0); ALUop out std_logic_vector (1 downto 0); equal_cond: in std_logic;

extop out std_logic;ALUsrc out std_logic;

MEMwr out std_logic;MemtoReg out std_logic;RegWr out std_logic;RegDst out std_logic;nPC out std_logic;

end maincontrol;

architecture behavior of maincontrol isbegin control: process(opcode,equal_cond) constant ORIop: std_logic_vector (5 downto 0) := “001101”; begin -- extop only 0 (no extend) for ORI inst case opcode is

when ORIop => extop <= 0; when others => extop <= 1;end case;

end process;end behavior;

CS152Lec10.10

Abstract View of our single cycle processor

° looks like a FSM with PC as state

PC

Nex

t P

C

Reg

iste

rF

etch ALU Reg

. W

rt

Mem

Acc

ess

Dat

aM

emInst

ruct

ion

Fet

ch

Res

ult

Sto

re

AL

Uct

r

Reg

Dst

AL

US

rc

Ext

Op

Mem

Wr

Eq

ual

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

MainControl

ALUcontrol

op

fun

Ext

CS152Lec10.11

What’s wrong with our CPI=1 processor?

° Long Cycle Time

° All instructions take as much time as the slowest

° Real memory is not as nice as our idealized memory• cannot always get the job done in one (short) cycle

PC Inst Memory mux ALU Data Mem mux

PC Reg FileInst Memory mux ALU mux

PC Inst Memory mux ALU Data Mem

PC Inst Memory cmp mux

Reg File

Reg File

Reg File

Arithmetic & Logical

Load

Store

Branch

Critical Path

setup

setup

CS152Lec10.12

Memory Access Time

° Physics => fast memories are small (large memories are slow)

• question: register file vs. memory

° => Use a hierarchy of memories

Storage Array

selected word line

addressstorage cell

bit line

sense ampsaddressdecoder

CacheProcessor

1 time-period

proc

. bu

s

L2Cache

mem

. bu

s

2-3 time-periods20 - 50 time-periods

memory

CS152Lec10.13

Reducing Cycle Time

° Cut combinational dependency graph and insert register / latch

° Do same work in two fast cycles, rather than one slow one

° May be able to short-circuit path and remove some components for some instructions!

storage element

Acyclic CombinationalLogic

storage element

storage element

Acyclic CombinationalLogic (A)

storage element

storage element

Acyclic CombinationalLogic (B)

CS152Lec10.14

Basic Limits on Cycle Time

° Next address logic• PC <= branch ? PC + offset : PC + 4

° Instruction Fetch• InstructionReg <= Mem[PC]

° Register Access• A <= R[rs]

° ALU operation• R <= A + B

PC

Nex

t P

C

Ope

rand

Fet

ch Exec Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

Inst

ruct

ion

Fet

ch

Res

ult

Sto

re

AL

Uct

r

Reg

Dst

AL

US

rc

Ext

Op

Mem

Wr

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

Control

CS152Lec10.15

Partitioning the CPI=1 Datapath

° Add registers between smallest steps

° Place enables on all registers

PC

Nex

t P

C

Ope

rand

Fet

ch Exec Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

Inst

ruct

ion

Fet

ch

Res

ult

Sto

re

AL

Uct

r

Reg

Dst

AL

US

rc

Ext

Op

Mem

Wr

nPC

_sel

Reg

Wr

Mem

Wr

Mem

Rd

Equ

al

CS152Lec10.16

Example Multicycle Datapath

° Critical Path ?

PC

Nex

t P

C

Ope

rand

Fet

ch

Inst

ruct

ion

Fet

ch

nPC

_sel

IRRegFile E

xtA

LU Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

Res

ult

Sto

reR

egD

stR

egW

r

Mem

Wr

Mem

Rd

S

M

Mem

ToR

eg

Equ

al

AL

Uct

rA

LU

Src

Ext

Op

A

B

E

CS152Lec10.17

Recall: Step-by-step Processor Design

Step 1: ISA => Logical Register Transfers

Step 2: Components of the Datapath

Step 3: RTL + Components => Datapath

Step 4: Datapath + Logical RTs => Physical RTs

Step 5: Physical RTs => Control

CS152Lec10.18

Step 4: R-rtype (add, sub, . . .)

° Logical Register Transfer

° Physical Register Transfers

inst Logical Register Transfers

ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4

inst Physical Register Transfers

IR <– MEM[pc]

ADDU A<– R[rs]; B <– R[rt]

S <– A + B

R[rd] <– S; PC <– PC + 4

Exe

c

Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

S

M

Reg

File

PC

Nex

t P

C

IR

Inst

. M

em

Tim

e

A

B

E

CS152Lec10.19

Step 4: Logical immed




ORI R[rt] <– R[rs] OR ZExt(Im16); PC <– PC + 4


IR <– MEM[pc]

ORI A<– R[rs]; B <– R[rt]

S <– A or ZExt(Im16)

R[rt] <– S; PC <– PC + 4

Exe

c

Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

S

M

Reg

File

PC

Nex

t P

C

IR

Inst

. M

em

Tim

e

A

B

E

CS152Lec10.20

Step 4 : Load




LW R[rt] <– MEM[R[rs] + SExt(Im16)];

PC <– PC + 4


IR <– MEM[pc]

LW A<– R[rs]; B <– R[rt]

S <– A + SExt(Im16)

M <– MEM[S]

R[rd] <– M; PC <– PC + 4

Exe

c

Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

S

M

Reg

File

PC

Nex

t P

C

IR

Inst

. M

em A

B

E

Tim

e

CS152Lec10.21

Step 4 : Store




SW MEM[R[rs] + SExt(Im16)] <– R[rt];

PC <– PC + 4


IR <– MEM[pc]

SW A<– R[rs]; B <– R[rt]

S <– A + SExt(Im16);

MEM[S] <– B PC <– PC + 4

Exe

c

Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

S

M

Reg

File

PC

Nex

t P

C

IR

Inst

. M

em A

B

E

Tim

e

CS152Lec10.22

Step 4 : Branch° Logical Register Transfer



BEQ if R[rs] == R[rt]

then PC <= PC + 4+SExt(Im16) || 00

else PC <= PC + 4

Exe

c

Reg

. F

ile

Mem

Acc

ess

Dat

aM

em

S

M

Reg

File

PC

Nex

t P

C

IR

Inst

. M

eminst Physical Register Transfers

IR <– MEM[pc]

BEQ E<– (R[rs] = R[rt])

if E then PC <– PC + 4 +SExt(Im16)||00

else PC <–PC+4

A

B

ET

ime

CS152Lec10.23

Our Control Model

° State specifies control points for Register Transfer

° Transfer occurs upon exiting state (same falling edge)

Control State

Next StateLogic

Output Logic

inputs (conditions)

outputs (control points)

State X

Register TransferControl Points

Depends on Input

CS152Lec10.24

Step 4 Control Specification for multicycle proc

IR <= MEM[PC]

R-type

A <= R[rs]B <= R[rt]

S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQPC <= Next(PC,Equal)

SW

“instruction fetch”

“decode / operand fetch”

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec10.25

Traditional FSM Controller

State

6

4

11nextState

op

Equal

control points

state op condnextstate control points

Truth Table

datapath State

CS152Lec10.26

Step 5 (datapath + state diagram control)

° Translate RTs into control points

° Assign states

° Then go build the controller

CS152Lec10.27

Mapping RTs to Control Points

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQ

PC <= Next(PC,Equal)

SW


“decode”

imem_rd, IRen

ALUfun, Sen

RegDst, RegWr,PCen

Aen, Ben,Een

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec10.28

Assigning States

IR <= MEM[PC]

R-type


S <= A fun B

R[rd] <= SPC <= PC + 4

S <= A or ZX

R[rt] <= SPC <= PC + 4

ORi

S <= A + SX

R[rt] <= MPC <= PC + 4

M <= MEM[S]

LW

S <= A + SX

MEM[S] <= BPC <= PC + 4

BEQ

PC <= Next(PC)

SW


“decode”

0000

0001

0100

0101

0110

0111

1000

1001

1010

00111011

1100

Exe

cute

Mem

ory

Writ

e-ba

ck

CS152Lec10.29

(Mostly) Detailed Control Specification (missing0)

0000 ?????? ? 0001 10001 BEQ x 0011 1 1 1 0001 R-type x 0100 1 1 1 0001 ORI x 0110 1 1 10001 LW x 1000 1 1 10001 SW x 1011 1 1 1

0011 xxxxxx 0 0000 1 0 x 0 x0011 xxxxxx 1 0000 1 1 x 0 x0100 xxxxxx x 0101 0 1 fun 10101 xxxxxx x 0000 1 0 0 1 10110 xxxxxx x 0111 0 0 or 10111 xxxxxx x 0000 1 0 0 1 01000 xxxxxx x 1001 1 0 add 11001 xxxxxx x 1010 1 0 11010 xxxxxx x 0000 1 0 1 1 01011 xxxxxx x 1100 1 0 add 11100 xxxxxx x 0000 1 0 0 1 0

State Op field Eq Next IR PC Ops Exec Mem Write-Backen sel A B E Ex Sr ALU S R W M M-R Wr Dst

R:

ORi:

LW:

SW:

-all same in Moore machine

BEQ:

CS152Lec10.30

Performance Evaluation

° What is the average CPI?• state diagram gives CPI for each instruction type

• workload gives frequency of each type

Type CPIi for type Frequency CPIi x freqIi

Arith/Logic 4 40% 1.6

Load 5 30% 1.5

Store 4 10% 0.4

branch 3 20% 0.6

Average CPI:4.1

CS152Lec10.31

How Effectively are we utilizing our hardware?

° Example: memory is used twice, at different times• Ave mem access per inst = 1 + Flw + Fsw ~ 1.3

• if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8

° We could reduce HW without hurting performance• extra control

IR <- Mem[PC]

A <- R[rs]; B<– R[rt]

S <– A + B

R[rd] <– S;PC <– PC+4;

S <– A + SX

M <– Mem[S]

R[rd] <– M;PC <– PC+4;

S <– A or ZX

R[rt] <– S;PC <– PC+4;

S <– A + SX

Mem[S] <- B

PC <– PC+4; PC < PC+4; PC < PC+SX;

CS152Lec10.32

“Princeton” Organization

° Single memory for instruction and data access • memory utilization -> 1.3/4.8

° Sometimes, muxes replaced with tri-state buses• Difference often depends on whether buses are internal to chip

(muxes) or external (tri-state)

° In this case our state diagram does not change• several additional control signals

• must ensure each bus is only driven by one source on each cycle

RegFile

A

B

A-BusB Bus

IR S

W-Bus

PC

nextPC ZX SX

Mem

CS152Lec10.33

Another Alternative MultiCycle DataPath

° In each clock cycle, each Bus can be used to transfer from one source

° µ-instruction can simply contain B-Bus and W-Dst fields

RegFile

A

B

A-Bus

B Bus

IR S mem

W-Bus

PC

instmem

nextPC ZX SX

CS152Lec10.34

What about a 2-Bus Microarchitecture (datapath)?

RegFile

A

B

A-BusB Bus

IR SPC

nextPC ZXSX

Mem

RegFile

A

BIR SP

CnextPC ZXSX

Mem

Instruction Fetch

Decode / Operand Fetch

M

M

CS152Lec10.35

Load

° What about 1 bus ? 1 adder? 1 Register port?

RegFile

A

BIR SP

CnextPC ZXSX

Mem

RegFile

A

BIR SP

CnextPC ZXSX

Mem

RegFile

A

BIR SP

CnextPC ZXSX

Mem

Execute

addr

M

M

M

Mem

Write-back

CS152Lec10.36

Summary

° Disadvantages of the Single Cycle Processor• Long cycle time

• Cycle time is too long for all instructions except the Load

° Multiple Cycle Processor:• Divide the instructions into smaller steps

• Execute each step (instead of the entire instruction) in one cycle

° Partition datapath into equal size chunks to minimize cycle time

• ~10 levels of logic between latches

° Follow same 5-step method for designing “real” processor

CS152 Lec10.1 CS 152 Computer Architecture and Engineering Lecture 10 Designing a Multicycle...

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