CS 6461: Computer Architecture Instruction Set Architecture

CS 6461: Computer ArchitectureInstruction Set Architecture

Instructor: Morris Lancaster

Appendix A+

Instruction Set Principles and Examples

August 13, 2012 CS 6461 Instruction Set Architecture 3

?Design a New High Performance System?

• ISA– What instructions should we include

• Internal Organization– How do the instructions implemented affect the

internal organization (and subsequently performance)

• How best approach this problem?– Understand what a computer and an instruction set

architecture does for us

– Look at current architectures for insight


Classifying ISA’s

• Type of Internal Storage– Stack

– Accumulator

– Set of Registers


Operand Locations for 4 ISA Classes


Design Decisions

• Instruction Set Architecture Class (Load-Store?)– How Many Registers (more is good)

• How Many Operands in the instruction?


Code Sequences for the 4 Classes

• Since 1980s almost all new designs are load store architectures.– Machines have large register files

– Registers are easier for the compiler to manage (addressed in only one way)

Stack Accumulator Register

(register-memory)

Register

(load store)

Push A Load A Load R1, A Load R1, A

Push B Add B Add R3, R1, B Load R2, B

Add Store C Store R3, C Add R3, R1, R2

Pop C Store R3,C


Number of Memory Addresses

Number of memory

addresses

Maximum number of operands

allowed

Type of Architecture Examples

0 3 Load-Store Alpha, ARM, MIPS, PowerPC, SPARC, SuperH, TM32

1 2 Register-Memory IBM 360/370, Intel 80x86, Motorola 68000, TI TMS320C54x

2 2 Memory – memory VAX (also has 3 operand formats)

3 3 Memory - memory VAX (also has 2 operand formats)


Tradeoffs for the ISA Classes

Type Advantages Disadvantages

Register-register

(0,3)

Simple, fixed length instruction encoding. Simple code generation model. Instructions take similar numbers of clocks to execute.

Higher instruction count than architectures with memory references in the instructions. More instructions and lower instruction density leads to larger programs

Register-memory

(1,2)

Data can be accessed without a separate load instruction first. Instruction format tends to be easy to encode and yields good density

Operands are not equivalent since a source operand is destroyed. Encoding a register number and a memory address in each instruction may restrict the number of registers. Clocks per instruction vary by operand location

Memory-memory

(2,2) or (3,3)

Most compact. Does not waste registers for temporaries.

Large variation in instruction size, especially for three-operand instructions. In addition, large variation in work per instruction. Memory accesses create memory bottleneck. (Not used today)


Memory Addressing(page B9)

• Register Add R4,R3 R4<- R4 + R3• Immediate Add R4,#3 R4<- R4 + 3• Displacement Add R4,100(R1) R4<- R4 + Mem[100+R1]• Register Indirect Add R4,(R1) R4<- R4 + Mem[R1]• Indexed Add R3,(R1+R2) R3<- R3 + Mem[R1+R2]• Direct Add R1, (1001) R1<- R1 + Mem[1001]• Memory Indirect Add R1, @(R3) R1<- R1 +

Mem[Mem[R3]]• AutoIncrement Add R1, (R2)+ R1<- R1 + Mem[R2]

R2<- R2 +d• AutoDecrement Add R1, -(R2) R2<- R2 - d

R1<- R1 + Mem[R2]• Scaled Add R1, 100(R2)[R3] R1<- (R1) +

Mem[100+(R2) + (R3)*d]


Summary of Use of Addressing Modes for DEC VAX Architecture


Displacement Values Are Widely Distributed


About ¼ of Data Transfers and ALU Operations Have an Immediate Operand


Distribution of Immediate Values


Type and Size of Operands

• 8, 16, 32, 64 bits• Alignment• Fetch capability• Encoding type


Distribution of Data Access By Size


Control Flow

• Addressing modes• Conditional branch operations• Frequency distributions


Breakdown of Control Flow Instructions


Branch Distance In Number of Instructions


Frequency of Different Types of Compares in Conditional Branches


Fig 2.38 Data Reference Sizes


Fig 2.23 Three Variations In Instruction Encoding


Instruction Encoding

• Balance– Desire to have as many registers and addressing modes

as possible

– The impact of the size of the register and addressing mode fields on the average instruction size and hence average program size

– A desire to have instructions encoded into lengths that will be easy to handle in a pipelined implementation


The Role of Compilers

• Structure• Optimizations• Register Allocation (tied with hardware)• Impact of Compiler Technology on Architects

Decisions


Fig 2.24 Compiler Structure


Fig 2.26 Change in Instruction Count From Compiler Optimization (SPEC2000)


MIPS Instruction Set

• MIPS 64 has 32 general purpose registers of 64 bits in length (R0…R31)– Value of R0 is always 0

• 32 floating point registers capable of holding 32 or 64 bit floating point numbers

• Instruction formats– I type immediate

– R type register-register

– J type jump


MIPS Instruction Set

• Instruction nomenclature– Opcode

– Registers rs, rd, rt


Fig 2.27 MIPS Instruction Layout


Fallacies and Pitfalls

• Pitfall – Designing a “high-level” instruction set feature specifically oriented to supporting a high-level language structure.

• Fallacy – There is such a thing as a typical program

• Pitfall – Innovating at the instruction set architecture to reduce code size without accounting for the compiler.

• Fallacy – An architecture with flaws cannot be successful

• Fallacy – You can design a flawless machine

CS 6461: Computer Architecture Instruction Set Architecture

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