CS 61C: Great Ideas in Computer Architecturecs61c/fa17/lec/07/L07... · 2017-09-15 · Big Idea:...
Transcript of CS 61C: Great Ideas in Computer Architecturecs61c/fa17/lec/07/L07... · 2017-09-15 · Big Idea:...
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CS61C:GreatIdeasinComputerArchitecture
RISC-VInstructionFormats
Instructors:KrsteAsanović andRandyH.Katz
http://inst.eecs.Berkeley.edu/~cs61c/fa17
9/14/17 Fall2017- Lecture#7 1
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LevelsofRepresentation/Interpretation
lw x10,0(x12)lw x11,4(x12)sw x11,0(x12)sw x10,4(x12)
HighLevelLanguageProgram(e.g.,C)
AssemblyLanguageProgram(e.g.,RISC-V)
MachineLanguageProgram(RISC-V)
HardwareArchitectureDescription(e.g.,blockdiagrams)
Compiler
Assembler
MachineInterpretation
temp=v[k];v[k]=v[k+1];v[k+1]=temp;
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
ArchitectureImplementation
Anythingcanberepresentedasanumber,
i.e.,dataorinstructions
LogicCircuitDescription(CircuitSchematicDiagrams)
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ENIAC(U.Penn.,1946)FirstElectronicGeneral-PurposeComputer
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• Blazinglyfast(multiplyin2.8ms!)– 10decimaldigitsx10decimaldigits
• Butneeded2-3daystosetupnewprogram,asprogrammedwithpatchcordsandswitches
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BigIdea:Stored-Program
Computer– Instructionsarerepresentedasbitpatterns- canthinkoftheseasnumbers– Therefore,entireprogramscanbestoredinmemorytobereadorwritten
justlikedata– Canreprogramquickly(seconds),don’thavetorewirecomputer(days)– Knownasthe“vonNeumann”computersafterwidelydistributedtech
reportonEDVACproject• Wrote-updiscussionsofEckertandMauchly• AnticipatedearlierbyTuringandZuse
FirstDraftofaReportontheEDVACby
JohnvonNeumannContractNo.W–670–ORD–4926
BetweentheUnitedStatesArmyOrdnanceDepartmentandthe
UniversityofPennsylvaniaMooreSchoolofElectricalEngineering
UniversityofPennsylvania
June 30,1945
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EDSAC(Cambridge,1949)FirstGeneralStored-ProgramComputer
• Programsheldasnumbersinmemory• 35-bitbinary2’scomplementwords
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Consequence#1:EverythingHasaMemoryAddress
• Sinceallinstructionsanddataarestoredinmemory,everythinghasamemoryaddress:instructions,datawords– Bothbranchesandjumpsusethese
• Cpointersarejustmemoryaddresses:theycanpointtoanythinginmemory– Unconstraineduseofaddressescanleadtonastybugs;avoidingerrors
uptoyouinC;limitedinJavabylanguagedesign• Oneregisterkeepsaddressofinstructionbeingexecuted:
“ProgramCounter”(PC)– Basicallyapointertomemory– IntelcallsitInstructionPointer(abettername)
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Consequence#2:BinaryCompatibility
• Programsaredistributedinbinaryform– Programsboundtospecificinstructionset– DifferentversionforphonesandPCs
• Newmachineswanttorunoldprograms(“binaries”)aswellasprogramscompiledtonewinstructions
• Leadsto“backward-compatible”instructionsetevolvingovertime
• SelectionofIntel8088in1981for1st IBMPCismajorreasonlatestPCsstilluse80x86instructionset;couldstillrunprogramfrom1981PCtoday
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InstructionsasNumbers(1/2)• Mostdataweworkwithisinwords(32-bitchunks):
– Eachregisterisaword– lw andsw bothaccessmemoryonewordatatime
• Sohowdowerepresentinstructions?– Remember:Computeronlyunderstands1sand0s,soassembler
string“add x10,x11,x0”ismeaninglesstohardware– RISC-Vseekssimplicity:sincedataisinwords,makeinstructions
befixed-size32-bitwordsalso• Same32-bitinstructionsusedforRV32,RV64,RV128
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InstructionsasNumbers(2/2)• Onewordis32bits,sodivideinstructionwordinto“fields”• Eachfieldtellsprocessorsomethingaboutinstruction• Wecoulddefinedifferentfieldsforeachinstruction,butRISC-
Vseekssimplicity,sodefinesixbasictypesofinstructionformats:– R-formatforregister-registerarithmeticoperations– I-formatforregister-immediatearithmeticoperationsandloads– S-formatforstores– B-formatforbranches(minorvariantofS-format,calledSBbefore)– U-formatfor20-bitupperimmediateinstructions– J-formatforjumps(minorvariantofU-format,calledUJbefore)
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SummaryofRISC-VInstructionFormats
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R-FormatInstructionLayout
• 32-bitinstructionworddividedintosixfieldsofvaryingnumbersofbitseach:7+5+5+3+5+7=32
• Examples– opcode isa7-bitfieldthatlivesinbits6-0oftheinstruction– rs2isa5-bitfieldthatlivesinbits24-20oftheinstruction
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Field’sbitpositions
NumberofbitsinfieldNameoffield
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R-FormatInstructionsopcode/funct fields
– opcode:partiallyspecifieswhatinstructionitis• Note:Thisfieldisequalto0110011two forallR-Formatregister-registerarithmeticinstructions
– funct7+funct3:combinedwithopcode,thesetwofieldsdescribewhatoperationtoperform
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• Question:Whyaren’topcode andfunct7 andfunct3 asingle17-bitfield?– We’llanswerthislater
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R-FormatInstructionsregisterspecifiers
– rs1 (SourceRegister#1):specifiesregistercontainingfirstoperand
– rs2 : specifiessecondregisteroperand– rd (DestinationRegister):specifiesregisterwhichwillreceiveresultofcomputation
– Eachregisterfieldholdsa5-bitunsignedinteger(0-31)correspondingtoaregisternumber(x0-x31)
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R-FormatExample• RISC-VAssemblyInstruction:
add x18,x19,x10
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0000000 01010 10011 000 10010 0110011
Reg-Reg OPrd=18ADDADD rs2=10 rs1=19
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AllRV32R-formatinstructions
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Differentencodinginfunct7+funct3selectsdifferentoperations
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I-FormatInstructions• Whataboutinstructionswithimmediates?
– 5-bitfieldonlyrepresentsnumbersuptothevalue31:immediates maybemuchlargerthanthis
– Ideally,RISC-Vwouldhaveonlyoneinstructionformat(forsimplicity):unfortunately,weneedtocompromise
• DefinenewinstructionformatthatismostlyconsistentwithR-format– Noticeifinstructionhasimmediate,thenusesatmost2registers(onesource,onedestination)
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I-FormatInstructionLayout
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• OnlyonefieldisdifferentfromR-format,rs2andfunct7replacedby12-bitsignedimmediate,imm[11:0]
• Remainingfields(rs1,funct3,rd,opcode)sameasbefore• imm[11:0]canholdvaluesinrange[-2048ten ,+2047ten]• Immediateisalwayssign-extendedto32-bitsbeforeuseinan
arithmeticoperation• We’lllaterseehowtohandleimmediates >12bits
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I-FormatExample• RISC-VAssemblyInstruction:
addi x15,x1,-50
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111111001110 00001 000 01111 0010011
OP-Immrd=15ADDimm=-50 rs1=1
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AllRV32I-formatArithmeticInstructions
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“Shift-by-immediate”instructionsonlyuselower5bitsoftheimmediatevalueforshiftamount(canonlyshiftby0-31bitpositions)
Oneofthehigher-orderimmediatebitsisusedtodistinguish“shiftrightlogical”(SRLI)from“shiftrightarithmetic”(SRAI)
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Administrivia
• HW0Gradeswerereleased– Ifyouhaveanissuewiththem,pleasefilloutthisformbytonight:
https://goo.gl/forms/QH44Iw746pcCxOyH2• HW1Part1DuenextMonday,Part2DueFridaySept22
– Homework-orientedofficehoursnextMonday(checkthewebsite)– HomeworkPartyonnextWednesday(6:30-10pmin293Cory)– Autograded resultstobereleasedeverynoonstartingthisFriday
• Midterm#1in1.5weeks:September26!– Twosided8.5”x11”cheatsheet+RISC-VGreenCardthatwegiveyou– DSPstudents:pleasemakesureweknowaboutyourspecial
accommodations(contactStevenHotheheadTAifyouhaven’tyet)
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Break!
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LoadInstructionsarealsoI-Type
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• The12-bitsignedimmediateisaddedtothebaseaddressinregisterrs1 toformthememoryaddress– Thisisverysimilartotheadd-immediateoperationbutusedtocreate
addressnottocreatefinalresult
• Thevalueloadedfrommemoryisstoredinregisterrd
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I-FormatLoadExample• RISC-VAssemblyInstruction:
lw x14, 8(x2)
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000000001000 00010 010 01110 0000011
LOADrd=14LWimm=+8 rs1=2
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AllRV32LoadInstructions
• LBUis“loadunsignedbyte”• LHis“loadhalfword”,whichloads16bits(2bytes)andsign-extendstofill
destination32-bitregister• LHUis“loadunsignedhalfword”,whichzero-extends16bitstofill
destination32-bitregister• ThereisnoLWUinRV32,becausethereisnosign/zeroextensionneeded
whencopying32bitsfromamemorylocationintoa32-bitregister24
funct3fieldencodessizeandsignedness ofloaddata
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S-FormatUsedforStores
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• Storeneedstoreadtworegisters,rs1forbasememoryaddress,andrs2fordatatobestored,aswellasneedimmediateoffset!
• Can’thavebothrs2andimmediateinsameplaceasotherinstructions!• Notethatstoresdon’twriteavaluetotheregisterfile,nord!• RISC-Vdesigndecisionismovelow5bitsofimmediatetowhererd
fieldwasinotherinstructions– keeprs1/rs2fieldsinsameplace• registernamesmorecriticalthanimmediatebitsinhardwaredesign
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S-FormatExample• RISC-VAssemblyInstruction:
sw x14, 8(x2)
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0000000 01110 00010 010 01000 0100011
STOREoffset[4:0]=8
SWoffset[11:5]=0
rs2=14 rs1=2
combined12-bitoffset=80000000 01000
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AllRV32StoreInstructions
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RISC-VConditionalBranches• E.g.,BEQ x1, x2, Label• Branchesreadtworegistersbutdon’twritearegister(similartostores)
• Howtoencodelabel,i.e.,wheretobranchto?
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BranchingInstructionUsage
• Branchestypicallyusedforloops(if-else,while,for)– Loopsaregenerallysmall(<50instructions)– Functioncallsandunconditionaljumpshandledwithjump
instructions(J-Format)• Recall: Instructionsstoredinalocalizedareaofmemory
(Code/Text)– Largestbranchdistancelimitedbysizeofcode– Addressofcurrentinstructionstoredintheprogramcounter
(PC)
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PC-RelativeAddressing• PC-RelativeAddressing: Usetheimmediate fieldasatwo’s-complementoffsettoPC– BranchesgenerallychangethePCbyasmallamount– Canspecify± 211 addressesfromthePC
• WhynotusebyteaddressoffsetfromPC?
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ScalingBranchOffset• Oneidea:Toimprovethereachofasinglebranchinstruction,multiplytheoffsetbyfourbytesbeforeaddingtoPC
• Thiswouldallowonebranchinstructiontoreach± 211× 32-bitinstructionseithersideofPC– Fourtimesgreaterreachthanusingbyteoffset
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BranchCalculation
• Ifwedon’t takethebranch:PC = PC + 4 (i.e.,nextinstruction)
• Ifwedo takethebranch:PC = PC + immediate*4
• Observations:– immediate isnumberofinstructionstojump(remember,specifieswords)eitherforward(+)orbackwards(–)
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RISC-VFeature,n×16-bitinstructions• ExtensionstoRISC-VbaseISAsupport16-bitcompressed
instructionsandalsovariable-lengthinstructionsthataremultiplesof16-bitsinlength
• Toenablethis,RISC-Vscalesthebranchoffsetby2bytesevenwhenthereareno16-bitinstructions
• Reducesbranchreachbyhalfandmeansthat½ofpossibletargetswillbeerrorsonRISC-Vprocessorsthatonlysupport32-bitinstructions(asusedinthisclass)
• RISC-Vconditionalbranchescanonlyreach± 210 × 32-bitinstructionseithersideofPC
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RISC-VB-FormatforBranches
• B-formatismostlysameasS-Format,withtworegistersources(rs1/rs2)anda12-bitimmediate
• Butnowimmediaterepresentsvalues-4096to+4094in2-byteincrements
• The12immediatebitsencodeeven 13-bitsignedbyteoffsets(lowestbitofoffsetisalwayszero,sononeedtostoreit)
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BranchExample,determineoffset• RISC-VCode:
Loop: beq x19,x10,Endadd x18,x18,x10addi x19,x19,-1j Loop
End: # target instruction
• Branchoffset=• (Branchwithoffsetof0,branchestoitself)
4×32-bitinstructions=16bytes
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1234
Countinstructionsfrombranch
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BranchExample,encodeoffset
• RISC-VCode:Loop: beq x19,x10,End
add x18,x18,x10addi x19,x19,-1j Loop
End: # target instruction
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??????? 01010 10011 000 ????? 1100011
BRANCHimmBEQimm rs2=10 rs1=19
offset=16bytes=8x2
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RISC-VImmediateEncoding
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InstructionEncodings,inst[31:0]
32-bitimmediates produced,imm[31:0]
Onlybit7ofinstructionchangesroleinimmediatebetweenSandBUpperbitssign-extendedfrominst[31]always
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BranchExample,completeencoding
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0 01010 10011 000 1000 11000110000000
BRANCHBEQrs2=10 rs1=19
beq x19,x10, offset = 16 bytes
13-bitimmediate,imm[12:0],withvalue16
0000000010000
imm[4:1]
imm[0]discarded,alwayszero
imm[10:5]
imm[11]imm[12]
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AllRISC-VBranchInstructions
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QuestionsonPC-addressing
• Doesthevalueinbranchimmediatefieldchangeifwemovethecode?– Ifmovingindividuallinesofcode,thenyes– Ifmovingallofcode,thenno
• Whatdowedoifdestinationis>210 instructionsawayfrombranch?– Otherinstructionssaveus
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QuestionsonPC-addressing
• Doesthevalueinbranchimmediatefieldchangeifwemovethecode?– Ifmovingindividuallinesofcode,thenyes– Ifmovingallofcode,thenno(becausePC-relativeoffsets)
• Whatdowedoifdestinationis>210 instructionsawayfrombranch?– Otherinstructionssaveus– beq x10,x0,far bne x10,x0,next# next instr à j far
next: # next instr419/14/17
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Break!
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U-Formatfor“UpperImmediate”instructions
• Has20-bitimmediateinupper20bitsof32-bitinstructionword
• Onedestinationregister,rd• Usedfortwoinstructions
– LUI– LoadUpperImmediate– AUIPC– AddUpperImmediatetoPC
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LUItocreatelongimmediates• LUIwritestheupper20bitsofthedestinationwiththe
immediatevalue,andclearsthelower12bits.• TogetherwithanADDItosetlow12bits,cancreateany32-bit
valueinaregisterusingtwoinstructions(LUI/ADDI).
LUI x10, 0x87654 # x10 = 0x87654000ADDI x10, x10, 0x321# x10 = 0x87654321
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OneCornerCaseHowtoset0xDEADBEEF?LUI x10, 0xDEADB # x10 = 0xDEADB000ADDI x10, x10, 0xEEF# x10 = 0xDEADAEEF
ADDI12-bitimmediateisalwayssign-extended,iftopbitisset,willsubtract-1fromupper20bits
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SolutionHowtoset0xDEADBEEF?LUI x10, 0xDEADC # x10 = 0xDEADC000ADDI x10, x10, 0xEEF # x10 = 0xDEADBEEF
Pre-incrementvalueplacedinupper20bits,ifsignbitwillbesetonimmediateinlower12bits.
Assemblerpseudo-ophandlesallofthis:li x10, 0xDEADBEEF # Creates two instructions
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AUIPC
• AddsupperimmediatevaluetoPCandplacesresultindestinationregister• UsedforPC-relativeaddressing
• Label: AUIPC x10, 0 # Puts address of label in x10
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J-FormatforJumpInstructions
• JALsavesPC+4inregisterrd (thereturnaddress)– Assembler“j”jumpispseudo-instruction,usesJALbutsetsrd=x0todiscardreturn
address• SetPC=PC+offset(PC-relativejump)• Targetsomewherewithin±219 locations,2bytesapart
– ±218 32-bitinstructions• Immediateencodingoptimizedsimilarlytobranchinstructiontoreduce
hardwarecost
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UsesofJAL# j pseudo-instructionj Label = jal x0, Label # Discard return address
# Call function within 218 instructions of PCjal ra, FuncName
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JALRInstruction(I-Format)
• JALRrd,rs,immediate– WritesPC+4tord (returnaddress)– SetsPC=rs +immediate– Usessameimmediates asarithmeticandloads
• nomultiplicationby2bytes
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UsesofJALR# ret and jr psuedo-instructionsret = jr ra = jalr x0, ra, 0# Call function at any 32-bit absolute addresslui x1, <hi20bits>jalr ra, x1, <lo12bits># Jump PC-relative with 32-bit offsetauipc x1, <hi20bits>jalr x0, x1, <lo12bits>
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SummaryofRISC-VInstructionFormats
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CompleteRV32IISA
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NotinCS61C