Criando Um Projeto No ISE

7/23/2019 Criando Um Projeto No ISE

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Criando um projetopara a placa Basys 2



Programar a seguinte tabela

A B S

P11 L3 M5

0 0 1

0 1 01 0 1

1 1 0

S= /A/B + A/B

S = /B



Fluxo de Dados – Data Flow

1. Passo 1 – Sintetizar. Passo – !m"lementar



#om"ortamental – Be$a%ioral

library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity funcao is !ort "A # in st$_lo%ic; & # in st$_lo%ic; S # out st$_lo%ic';en$ funcao;

((arc)itecture $ata_flo* of funcao is(( be%in(( S +, "not"A' an$ not"&'' or "A an$ not"&'';((en$ arc)itecture;

arc)itecture be)a-ioral of funcao is be%in

func # !rocess"ab' be%in if "a,// an$ b,//' t)en

S +, /1/;elsif "a,// an$ b,/1/' t)en S +, //;elsif "a,/1/ an$ b,//' t)en S +, /1/;else S +, //;en$ if;

en$ !rocess func;

en$ arc)itecture be)a-ioral;



Dia%ra0a e0 &locos



Si0ula2o

&ot2o $ireito no sinal #



&xem"los de #'digo

$tt"(//www.)ui*net.se/$d*/$dl/edu*aton/mux,-1/

-- =============================================================================

-- file name is: mux4_1.vhd (mux=multiplexer)

-- Author: Kim Petersen-- Created: .4.1 last modified: .4.1!-- ============================================================================= -- "t is a 4 input multiplexer #ith the fun$tion as:-- sel "nput =% output $omments-- &' '-- in =% output-- 1 in1 =% output-- 1 in* =% output-- 1 1 in! =% output------------ "+ and CA', $an onl e used inside a pro$ess.-- /0, and /"20 $an onl e used outside a pro$ess.---- "+ $orresponds to /0, -- CA', $orrepsonds to /"20

-- =============================================================================

LIBRARY ieee;USE ieee.st$_lo%ic_1164. ALL; -- $an e different dependent on tool used.USE ieee.st$_lo%ic_unsi%ne$. ALL; -- $an e different dependent on tool used.

ENTITY 0u34_1 IS

PORT "s # IN STD_LOGIC; s1 # IN STD_LOGIC; in # IN STD_LOGIC; in1 # IN STD_LOGIC; in # IN STD_LOGIC; in5 # IN STD_LOGIC; out!ut # OUT STD_LOGIC ';END 0u34_1;

-- =============================================================================

ARCHITECTURE if_e3a0!le OF 0u34_1 IS

BEGIN

0u3#PROCESS"s s1 in in1 in in5'BEGIN

IF "s,// AND s1,//' THEN

out!ut +, in; ELSIF "s,/1/ AND s1,//' THEN

out!ut +, in1; ELSIF "s,// AND s1,/1/' THEN

out!ut +, in; ELSIF "s,/1/ AND s1,/1/' THEN

out!ut +, in5; ELSE -- (s or s1 are not or 1) out!ut +, //; END IF;

END PROCESS 0u3;

END if_e3a0!le;

http://www.quicknet.se/hdc/hdl/educaton/mux4_1/

http://www.quicknet.se/hdc/hdl/educaton/mux4_1/



ARCHITECTURE case_e3a0!le OF 0u34_1 IS

BEGIN

0u3#PROCESS"s s1 in in1 in in5' VARIABLE sel # STD_LOGIC_7ECTO8"1 DOWNTO ';BEGIN

sel #, s1 9 s; -- $on$atenate s1 and s

CASE sel IS

WHEN :: , out!ut +, in; WHEN :1: , out!ut +, in1; WHEN :1: , out!ut +, in; WHEN :11: , out!ut +, in5; WHEN OTHERS , out!ut +, //; END CASE;

END PROCESS 0u3;

END case_e3a0!le;

-- =============================================================================

ARCHITECTURE *it)_e3a0!le OF 0u34_1 IS

SIGNAL sel # STD_LOGIC_7ECTO8"1 DOWNTO ';

BEGIN sel +, s1 9 s; -- $on$atenate s1 and s

WITH sel SELECT

out!ut +, in WHEN :: in1 WHEN :1: in WHEN :1: in5 WHEN :11: // WHEN OTHERS;

END *it)_e3a0!le;

-- =============================================================================

ARCHITECTURE *)en_e3a0!le OF 0u34_1 IS

BEGIN

out!ut +, in WHEN "s1 9 s',:: ELSE

in1 WHEN "s1 9 s',:1: ELSE

in WHEN "s1 9 s',:1: ELSE in5 WHEN "s1 9 s',:11: ELSE //;

END *)en_e3a0!le;

Criando Um Projeto No ISE

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