CprE 281: Digital Logic - Computer...
Transcript of CprE 281: Digital Logic - Computer...
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Instructor: Alexander Stoytchev
http://www.ece.iastate.edu/~alexs/classes/
CprE 281: Digital Logic
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Registers
CprE 281: Digital LogicIowa State University, Ames, IACopyright © Alexander Stoytchev
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Administrative Stuff
• Homework 8 is due next Monday.
• The second midterm exam is next Friday.
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Administrative Stuff• Midterm Exam #2
• When: Friday November 1 @ 4pm.
• Where: This classroom
• What: Chapters 1, 2, 3, 4 and 5.1-5.8
• The exam will be closed book but open notes (you can bring up to 3 pages of handwritten notes).
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Midterm 2: Format
• The exam will be out of 130 points
• You need 95 points to get an A for this exam
• It will be great if you can score more than 100 points.§ but you can’t roll over your extra points L
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Midterm 2: Topics
• Binary Numbers and Hexadecimal Numbers• 1’s complement and 2’s complement representation• Addition and subtraction of binary numbers• Circuits for adders and fast adders
• Single and Double precision IEEE floating point formats• Converting a real number to the IEEE format• Converting a floating point number to base 10
• Multiplexers (circuits and function)• Synthesis of logic functions using multiplexers• Shannon’s Expansion Theorem
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Midterm 2: Topics• Decoders (circuits and function)• Demultiplexers• Encoders (binary and priority)• Code Converters• K-maps for 2, 3, and 4 variables
• Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates
• Synthesis of logic circuits given constraints on the available building blocks that you can use
• Latches (circuits, behavior, timing diagrams)• Flip-Flops (circuits, behavior, timing diagrams)• Registers and Register Files
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Review of Flip-Flops
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A simple memory element with NOT Gates
x xx
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A simple memory element with NAND Gates
xx x
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A simple memory element with NOR Gates
xx x
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Basic Latch
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A simple memory element with NOR Gates
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A simple memory element with NOR Gates
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A simple memory element with NOR Gates
ResetSet
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Reset
Set Q
[ Figure 5.3 from the textbook ]
A memory element with NOR gates
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[ Figure 5.3 & 5.4 from the textbook ]
Two Different Ways to Draw the Same Circuit
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S R Q a Q b
0 00 11 01 1
0/1 1/00 11 00 0
(a) Circuit (b) Truth table
Q a
Q b
R
S
(no change)
SR Latch: Circuit and Truth Table
[ Figure 5.4a,b from the textbook ]
x1 x2 f0 0 10 1 01 0 01 1 0
NOR Gate NOR Gate Truth table
(Undesirable)
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Gated SR Latch
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[ Figure 5.5a from the textbook ]
Circuit Diagram for the Gated SR Latch
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Circuit Diagram for the Gated SR Latch
This is the “gate” of the gated latch
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Circuit Diagram for the Gated SR Latch
Notice that these are complements of each other
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[ Figure 5.5 from the textbook ]
Gated SR Latch: Circuit Diagram, Characteristic Table, and Graphical Symbol
(Undesirable)
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S
R
Clk
Q
Q
[ Figure 5.6 from the textbook ]
Gated SR latch with NAND gates
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S
R
Clk
Q
Q
Gated SR latch with NAND gates
In this case the “gate” is constructed using NAND gates! Not AND gates.
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S
R
Clk
Q
Q
Gated SR latch with NAND gates
Also, notice that the positions of S and R are now swapped.
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S
R
Clk = 1
Q
Q
Gated SR latch with NAND gates
S
R
Finally, notice that when Clk=1 this turns into the
basic latch with NAND gates, i.e., the SR Latch.
1
1
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S
R
Clk
Q
Q
Gated SR latch with NOR gates
Gated SR latch with NAND gates
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S
R
Clk
Q
Q
Gated SR latch with NOR gates
Gated SR latch with NAND gates
Graphical symbols are the same
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S
R
Clk
Q
Q
Gated SR latch with NOR gates
Gated SR latch with NAND gates
Characteristic tables are the same
(undesirable)
(undesirable)
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Gated D Latch
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[ Figure 5.7a from the textbook ]
Circuit Diagram for the Gated D Latch
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Gated D Latch: Alternative Design
[https://en.wikipedia.org/wiki/Flip-flop_(electronics)]
Clk
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[ Figure 5.7a,b from the textbook ]
Gated D Latch: Circuit Diagram, Characteristic Table, and Graphical Symbol
Note that it is now impossible to have S=R=1.When Clk=1 the output follows the D input.When Clk=0 the output cannot be changed.
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t sut h
Clk
D
Q
[ Figure 5.8 from the textbook ]
Setup and hold times for Gated D latch
Setup time (tsu) – the minimum time that the D signal must be stableprior to the the negative edge of the Clock signal
Hold time (th) – the minimum time that the D signal must remain stableafter the the negative edge of the Clock signal
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Master-Slave D Flip-Flop
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Constructing a Master-Slave D Flip-FlopFrom Two D Latches
Master Slave
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Constructing a Master-Slave D Flip-FlopFrom Two D Latches
Master Slave
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Constructing a Master-Slave D Flip-FlopFrom Two D Latches
Master Slave
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Constructing a Master-Slave D Flip-FlopFrom Two D Latches
[ Figure 5.9a from the textbook ]
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Constructing a Master-Slave D Flip-FlopFrom one D Latch and one Gated SR Latch
(This version uses one less NOT gate)
Master Slave
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Constructing a Master-Slave D Flip-FlopFrom one D Latch and one Gated SR Latch
(This version uses one less NOT gate)
Master Slave
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Edge-Triggered D Flip-Flops
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(a) Circuit
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
[ Figure 5.9a from the textbook ]
Master-Slave D Flip-Flop
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D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
Negative-Edge-Triggered Master-Slave D Flip-Flop
Positive-Edge-Triggered Master-Slave D Flip-Flop
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
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D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
Negative-Edge-Triggered Master-Slave D Flip-Flop
Positive-Edge-Triggered Master-Slave D Flip-Flop
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
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D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
Negative-Edge-Triggered Master-Slave D Flip-Flop
Positive-Edge-Triggered Master-Slave D Flip-Flop
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
D Q
Q
D Q
Q
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T Flip-Flop
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[ Figure 5.15a from the textbook ]
T Flip-Flop
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[ Figure 5.15a from the textbook ]
T Flip-Flop
Positive-edge-triggered D Flip-Flop
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[ Figure 5.15a from the textbook ]
T Flip-Flop
What is this?
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What is this?
Q
Q
TD
![Page 53: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/53.jpg)
Q
Q
T
D
What is this?
+ = ?
![Page 54: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/54.jpg)
T Flip-Flop
T
0
1 D Q
Q Clock
![Page 55: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/55.jpg)
T
0
1 D Q
Q Clock
T Flip-Flop
Q
Q
Note that the two inputs to the multiplexer are inverses of each other.
![Page 56: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/56.jpg)
T
0
1 D Q
Q Clock
Another Way to Draw This
Q
Q
![Page 57: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/57.jpg)
T
0
1 D Q
Q Clock
Another Way to Draw This
Q
Q
What is this?
![Page 58: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/58.jpg)
What is this?
Q
T
D
![Page 59: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/59.jpg)
What is this?
Q
T
D
D = QT + QT
![Page 60: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/60.jpg)
It is an XOR
Q
T
D
D = Q + T
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DQT
It is an XOR
D = Q + T
![Page 62: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/62.jpg)
What is this?
+ = ?
![Page 63: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/63.jpg)
T D Q
Q Clock
T Flip-Flop
![Page 64: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/64.jpg)
[ Figure 5.15a-c from the textbook ]
T Flip-Flop(circuit, truth table and graphical symbol)
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T Flip-Flop(How it Works)
If T=0 then it stays in its current state
If T=1 then it reverses its current state
In other words the circuit “toggles” its state when T=1. This is why it is called T flip-flop.
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JK Flip-Flop
![Page 67: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/67.jpg)
[ Figure 5.16a from the textbook ]
JK Flip-Flop
D = JQ + KQ
![Page 68: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/68.jpg)
[ Figure 5.16 from the textbook ]
JK Flip-Flop
J Q
Q
K01
Q t 1+( )Q t( )
0
(b) Truth table (c) Graphical symbol
J00
0 111 Q t( )1
K
D Q
Q
Q
Q
J
Clock
(a) Circuit
K
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JK Flip-Flop(How it Works)
A versatile circuit that can be used both as aSR flip-flop and as a T flip flop
If J=0 and S =0 it stays in the same state
Just like SR It can be set and reset J=S and K=R
If J=K=1 then it behaves as a T flip-flop
![Page 70: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/70.jpg)
Complete Wiring Diagrams
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Positive-Edge-Triggered D Flip-Flop
![Page 72: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/72.jpg)
Negative-Edge-Triggered D Flip-Flop
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The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop
D
Clock
Q
Q
![Page 74: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/74.jpg)
The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
Q
Q
D
Clock
![Page 75: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/75.jpg)
The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
Q
Q
D
Clock
![Page 76: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/76.jpg)
T D Q
Q Clock
Positive-Edge-Triggered T Flip-Flop
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Negative-Edge-Triggered T Flip-Flop
T D Q
Q Clock
![Page 78: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/78.jpg)
The Complete Wiring Diagram for a Positive-Edge-Triggered D Flip-Flop
T
Clock
Q
Q
![Page 79: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/79.jpg)
The Complete Wiring Diagram for a Negative-Edge-Triggered D Flip-Flop
T
Clock
Q
Q
![Page 80: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/80.jpg)
D Q
Q
Q
Q
J
Clock
K
Positive-Edge-Triggered JK Flip-Flop
![Page 81: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/81.jpg)
D Q
Q
Q
Q
J
Clock
K
Negative-Edge-Triggered JK Flip-Flop
![Page 82: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/82.jpg)
The Complete Wiring Diagram for a Positive-Edge-Triggered JK Flip-Flop
Q
Q
Clock
J
K
![Page 83: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/83.jpg)
The Complete Wiring Diagram for a Negative-Edge-Triggered JK Flip-Flop
Q
Q
Clock
J
K
![Page 84: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/84.jpg)
Registers
![Page 85: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/85.jpg)
Register (Definition)
An n-bit structure consisting of flip-flops.
![Page 86: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/86.jpg)
Parallel-Access Register
![Page 87: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/87.jpg)
1-Bit Parallel-Access Register
D Q
Q
Clock
InOut
Load
0
1
![Page 88: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/88.jpg)
1-Bit Parallel-Access Register
D Q
Q
Clock
InOut
Load
0
1
The 2-to-1 multiplexer is used to select whether to load a new value into the D flip-flop or to retain the old value.
The output of this circuit is the Q output of the flip-flop.
![Page 89: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/89.jpg)
1-Bit Parallel-Access Register
D Q
Q
Clock
InOut
Load
0
1
If Load = 0, then retain the old value.
0
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1-Bit Parallel-Access Register
D Q
Q
Clock
InOut
Load
0
1
If Load = 1, then load the new value from In.
1
![Page 91: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/91.jpg)
1-Bit Parallel-Access Register
D Q
Q
Clock
InOut
Load
0
1
If Load = 0, then retain the old value.
If Load = 1, then load the new value from In.
![Page 92: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/92.jpg)
2-Bit Parallel-Access Register
D Q
Q
Clock
Load
0
1D Q
Q
In_1
Out_0
0
1
Out_1
In_0
![Page 93: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/93.jpg)
2-Bit Parallel-Access Register
D Q
Q
Clock
Load
0
1D Q
Q
In_1
Out_0
0
1
Out_1
In_0
Parallel Input
Parallel Output
![Page 94: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/94.jpg)
3-Bit Parallel-Access Register
D Q
Q
Clock
Load
0
1D Q
Q
In_2
Out_1
0
1
Out_2
In_1
D Q
Q
Out_0
0
1
In_0
Notice that all flip-flops are on the same clock cycle.
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3-Bit Parallel-Access Register
Parallel Input
Parallel Output
D Q
Q
Clock
Load
0
1D Q
Q
In_2
Out_1
0
1
Out_2
In_1
D Q
Q
Out_0
0
1
In_0
![Page 96: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/96.jpg)
4-Bit Parallel-Access Register
Clock
Load
D Q
Q
0
1
In_3
Out_3
D Q
Q
0
1
In_2
Out_2
D Q
Q
0
1
In_1
Out_1
D Q
Q
0
1
In_0
Out_0
![Page 97: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/97.jpg)
4-Bit Parallel-Access Register
Parallel Input
Parallel Output
Clock
Load
D Q
Q
0
1
In_3
Out_3
D Q
Q
0
1
In_2
Out_2
D Q
Q
0
1
In_1
Out_1
D Q
Q
0
1
In_0
Out_0
![Page 98: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/98.jpg)
4-Bit Parallel-Access Register
Clock
Load
D Q
Q
0
1
In_3
Out_3
D Q
Q
0
1
In_2
Out_2
D Q
Q
0
1
In_1
Out_1
D Q
Q
0
1
In_0
Out_0
![Page 99: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/99.jpg)
4-Bit Parallel-Access Register
Clock
Load
D Q
Q
0
1
In_3
Out_3
D Q
Q
0
1
In_2
Out_2
D Q
Q
0
1
In_1
Out_1
D Q
Q
0
1
In_0
Out_0
0
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4-Bit Parallel-Access Register
Clock
Load
D Q
Q
0
1
In_3
Out_3
D Q
Q
0
1
In_2
Out_2
D Q
Q
0
1
In_1
Out_1
D Q
Q
0
1
In_0
Out_0
1
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Shift Register
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A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
[ Figure 5.17a from the textbook ]
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A simple shift register
Positive-edge-triggered D Flip-Flop
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
![Page 104: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/104.jpg)
A simple shift register
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
![Page 105: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/105.jpg)
A simple shift register
D Q
Q
Master Slave
D
Clock
Q
Q
D Q
Q
Q m Q s
Clk Clk
Gated D-Latch Gated D-Latch
D –Flip-Flop
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
![Page 106: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/106.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
![Page 107: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/107.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 108: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/108.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 109: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/109.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 110: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/110.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 111: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/111.jpg)
A simple shift register
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out Q 1 Q 2 Q 3 Q 4
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 112: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/112.jpg)
A simple shift register
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
![Page 113: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/113.jpg)
A simple shift register
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
Clock
![Page 114: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/114.jpg)
A simple shift register
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
Clock
![Page 115: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/115.jpg)
A simple shift register
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
Clock
![Page 116: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/116.jpg)
A simple shift register
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk
D Q
Q
Master Slave
Clk
D Q
QClk Clock
In
Clock
![Page 117: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/117.jpg)
A simple shift register
[ Figure 5.17 from the textbook ]
D Q
Q Clock
D Q
Q
D Q
Q
D Q
Q
In Out
t 0
t 1
t 2
t 3
t 4
t 5
t 6
t 7
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
0
1
1
Q 1 Q 2 Q 3 Q 4 Out = In
(b) A sample sequence
(a) Circuit
Q 1 Q 2 Q 3 Q 4
![Page 118: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/118.jpg)
Parallel-Access Shift Register
![Page 119: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/119.jpg)
Parallel-access shift register
[ Figure 5.18 from the textbook ]
![Page 120: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/120.jpg)
Parallel-access shift register
[ Figure 5.18 from the textbook ]
0
When Load=0, this behaves like a shift register.
![Page 121: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/121.jpg)
Parallel-access shift register
[ Figure 5.18 from the textbook ]
1
When Load=1, this behaves like a parallel-access register.
![Page 122: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/122.jpg)
Shift Register With Parallel Load and Enable
![Page 123: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/123.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
![Page 124: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/124.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
The directions of the input and output lines are switched relative to the previous slides.
![Page 125: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/125.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
Parallel Output
Parallel Input
![Page 126: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/126.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
0 0
![Page 127: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/127.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
0 1
![Page 128: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/128.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
1 0
![Page 129: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/129.jpg)
A shift register with parallel load and enable control inputs
[ Figure 5.59 from the textbook ]
1 1
![Page 130: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/130.jpg)
Parallel-access shift left / right register
![Page 131: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/131.jpg)
Complete the following circuit diagram to implement a 4-bit register that has both parallel load and shift left/right functionality. The register has two control inputs (C1 and C0), four parallel input lines (I3, I2, I1, and I0), and four output lines (Q3, Q2, Q1, and Q0). Depending on the values of C1 and C0, the register performs one of the following four operations:
Parallel-access shift left/right register
![Page 132: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/132.jpg)
Parallel-access shift left/right register
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 133: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/133.jpg)
Parallel-access shift left/right register
Clock
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 134: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/134.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
![Page 135: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/135.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
![Page 136: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/136.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0
![Page 137: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/137.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0In_3
![Page 138: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/138.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0In_3 In_2 In_1
![Page 139: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/139.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0In_3 In_2 In_1
![Page 140: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/140.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0In_3 In_2 In_1
C0C1
![Page 141: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/141.jpg)
Parallel-access shift left/right register
Clock
00011011
00011011
00011011
00011011
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Out_3 Out_2 Out_1 Out_0
In_0In_3 In_2 In_1
C0C1
![Page 142: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/142.jpg)
Multiplexer Tricks(select one of two 2-bit numbers)
![Page 143: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/143.jpg)
Select Either A=A1A0 or B=B1B0
0
1
s
0
1 F0
F1
A0
B0
A1
B1
![Page 144: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/144.jpg)
Select Either A=A1A0 or B=B1B0
0
1
s
0
1 F0
F1
A0
B0
A1
B1
0
= A0
= A1
![Page 145: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/145.jpg)
Select Either A=A1A0 or B=B1B0
0
1
s
0
1 F0
F1
A0
B0
A1
B1
1
= B0
= B1
![Page 146: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/146.jpg)
Multiplexer Tricks(select one of four 2-bit numbers)
![Page 147: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/147.jpg)
Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0
s 0
00011011
A0B0C0D0
F0
00011011
A1B1C1D1
F1
s 1
![Page 148: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/148.jpg)
Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0
= A0
= A1
0 0s
0
00011011
A0B0C0D0
F0
00011011
A1B1C1D1
F1
s 1
![Page 149: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/149.jpg)
Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0
= B0
= B1
0 1s
0
00011011
A0B0C0D0
F0
00011011
A1B1C1D1
F1
s 1
![Page 150: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/150.jpg)
Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0
= C0
= C1
1 0s
0
00011011
A0B0C0D0
F0
00011011
A1B1C1D1
F1
s 1
![Page 151: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/151.jpg)
Select A=A1A0 or B=B1B0 or C=C1C0 or D=D1D0
= D0
= D1
1 1s
0
00011011
A0B0C0D0
F0
00011011
A1B1C1D1
F1
s 1
![Page 152: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/152.jpg)
Register File
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Complete the following circuit diagram to implement a register file with four 2-bit registers, one write port,
one read port, and one write enable line.
![Page 154: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/154.jpg)
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Register 0
Register 1
Register 2
Register 3
![Page 156: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/156.jpg)
Register A
Register B
Register C
Register D
![Page 157: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/157.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
![Page 158: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/158.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
![Page 159: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/159.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
Write_enable
Write_address_0Write_address_1
![Page 160: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/160.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
Write_enable
Write_address_0Write_address_1
![Page 161: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/161.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
Out1 Out0Write_enable
Write_address_0Write_address_1 Read_address_1
Read_address_0
![Page 162: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/162.jpg)
Register A
Register B
Register C
Register D
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
Out1 Out0Write_enable
Write_address_0Write_address_1 Read_address_1
Read_address_0
Clock
![Page 163: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/163.jpg)
A1 A0
B1 B0
C1 C0
D1 D0
In1 In0
Out1 Out0Write_enable
Write_address_0Write_address_1 Read_address_1
Read_address_0
Clock
![Page 164: CprE 281: Digital Logic - Computer Engineeringalexs/classes/2019_Fall_281/slides_PDF/27_Registers.pdfMidterm 2: Topics •Decoders (circuits and function) •Demultiplexers •Encoders](https://reader034.fdocuments.net/reader034/viewer/2022042911/5f43eb37d0f4bf5d5b2dd4ab/html5/thumbnails/164.jpg)
Questions?
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THE END