CPCI 1228 S 16 A NALOG INPUTS /32 D I/O IMULTANEOUS … · Chocs 25 g - 6 ms EUROPEAN STANDARDS CE...

CONTACT: Email: [email protected]

Tel.: 33.1.41.87.30.00 www.adas.fr

APPLICATIONS

♦ 16 analog differential isochronous inputs

♦ 32 TTL I/O (2 x 16 bits)

♦ 16-bit ADCs 250 Ks/s per channel

♦ Software-programmable gains on each analog input

♦ 15 decimation ratios with anti-aliasing protection

♦ 1 programmable digital filter per channel

♦ High accuracy and low drift

♦ IRIG B or TRIGGER input for time-stamping (Master/Slave)

♦ Time resolution of 1 µs with PLL

♦ Multi-board multi-rack sync.(PXI)

♦ FLIP-FLOP memory on the board ( 2 x 256 KSamples)

The CPCI 1228 board provides simultaneous and isochronous acquisition of 16 analog differential inputs, and 32 TTL I/O (2 x 16 bits).

Each analog input possesses:

− One instrumentation amplifier with software-programmable gain (1 ; 2 ; 5 ; 10) (protection ± 40 V),

− One 16-bit ADC, max speed: 250 kSamples/s,

− One 128-sample programmable digital filter.

CPCI 1228 takes advantage of the PXI concept for board-to-channel and rack-to-rack synchronization. Time-sampling is performed through an IRIG B input followed by a synchronized oscillator which ensures a 1-μs resolution.

CPCI 1228 features:

− 2K-word measurement-descriptor table,

− Dual-access RAM in FLIP-FLOP mode, 2 x 256 kwords,

− 8 programmable interrupt sources with a debouncer.

The board can be used as Master or Slave on the CPCI / PXI to ensure high transmission rates in real time environments.

16 ANALOG INPUTS/32 DIGITAL I/O SIMULTANEOUS SAMPLING CPCI 1228

SPECIFICATIONS*

ANALOG INPUTS

Number of channels 16 differential

INSTRUMENTATION AMPLIFIER

Software programmable gain per channel

1 ; 2 ; 5 ; 10

Input impedance 1 MΩ diff / 500 kΩ SE

Signal range ± 10 V FS

Over voltage protection ± 40 V (with or without supplies)

Input current ± 30 nA

Input offset voltage ≤ ± 200+ 600/GμV

Offset drift ≤ ± 1,7 μV/°C (G = 10)

Gain error ≤ ± 0,04 %

Gain drift ≤ 10 ppm/°C

Non linearity ≤ ± 0,003 % FS

CMRR ≥ 70 dB (DC to 100 kHz)

Slew rate 20 V / μs

Attenuation at 100 kHz (10 Vpp)

< 100 ndB

Noise 2,5 μVpp (0,1 Hz to 10 Hz)

Crosstalk ≤ -96 dB (DC 100kHz)

THD (input signal at 10 kHz) ≤ - 94dB

SP

EC

IF

IC

AT

IO

NS

*

WWW. ADAS.FR

ADCS

Type 16-bit SAR with SH

Speed 250 K Samples/S (5 μs)

INL ± 2 LSB max

DNL ± 1 LSB max 16-bit no missing codes

SFDR 90 dB min

SNR (20 kHz) 88 dB typical

Interchannel skew 5 ns

NUMERICAL FILTERING

Type FIR (Finite Impulse Response)

Order 127

Selection With or without filter by software

Cut off frequency Programmable from Fd/50 to Fd/2,5

Attenuation at twice cut frequency

≥ 60 dB

Transition slope ≥ 160 dB/octave

Bandwidth ripple ≤ 0,02 dB of DC at 0,7 Fc

DIGITAL I/O

Number of channels 32 TTL / CMOS Compatibility 2 x 16-bit I/O selection

Number of interrupt inputs 8 with Anti-bounce software switchable adjustable frequencies of 30 kHz, 300 kHz, 3 MHz

Timing Synchro inputs with analog sampling or asynchronous R /W

TIME STAMPING

Type Type Analog IRIG B composite input or TTL external start trigger

Analog IRIG B input

Zin = 10 kΩ modulation : 1/3 Vin min : 500 mVpp / 170 mVpp (1/3) Vin max : 6 Vpp / 2 Vpp (1/3) Nominal : 2.5 Vpp / 840 mVpp

AFNOR NORM NORM NFS 87- 500

Coupling Master / Slave boards with synchro via trigger

High time resolution PLL with IRIG synchro for 1 μs resolution time stamping

Acquisition frequency 200 kHz max

Number of internal timers 2

Timers Resolution 16 bits

RTSI 3 TRIGGER lines

MEMORIES AND TRIGGER

Trigger modes Continuous Pre/post trigger

Trigger source External event Software Analog threshold

Scanning table

⋅ Pattern 1008 channels

⋅ Depth max 64 K patterns

Memories measurement

⋅ Type FLIP-FLOP or ONE SHOT

⋅ Deph 2 x 256 kSamples

CPCI 1268 - 16 ANALOG INPUTS/32 DIGITAL I/O SIMULTANEOUS SAMPLING

Specifications are subject to change. Please, verify the latest specifications prior order. Version : 2.0— Edion : June 2016

CPCI INTERFACE

PCI Master/Slave 32 bits/33 MHz

PXI Trigger & Trigstar

Coupler AMCC 5335

Data transmission 66 Mo/s (max.)

POWER SUPPLY

Voltage + 5 V/1,5 A ; + 3,3 V/0,5 A

CONNECTORS

Front panel connectors

1 μD 68 pts Female

Analog Inputs + Digital I/O

1 x LEMO 1 point for IRIG B or TRIGGER (Input / Output)

PHYSICAL CHARACTERISTICS

Format 3U/4Te CPCI FORM FACTOR

LEDS

1 x Acquisition

1 x Active Master

1 x Access board

ENVIRONMENT

Range Industrial

Operating temperature - 20°C / + 70°C

Storage temperature - 25°C / + 85°C

Relative humidity 90 % non condensing

Vibrations 20 Hz - 2000 Hz - 4g

Chocs 25 g - 6 ms

EUROPEAN STANDARDS

CE Compliance (EMC - EN 61326 - EN 55011 Class A) ROHS - 2002/95/EC

SP

EC

IF

IC

AT

IO

NS

*

CPCI 1268 - 16 ANALOG INPUTS/32 DIGITALI/O SIMULTANEOUS SAMPLING

*Specifications given for 25°C

ORDERING INFORMATION

PCI 1268 C 16 Analog inputs/32 digitalI/O simultaneous sampling

STB Terminal blocks STB 534 + (STB 554 + STB 552) STB 534 + (STB 658 + STB 532 or STB 520)

BCI Terminal blocks STB 514 + (2 x BCI 184 + 2 x BCI 140 or BCI 160)

Cables WR 368

ACCESSORIES

CPCI 1228 - Rev. B - Edition 2 – 28/07

1

TRACEABILITY FORM

DOCUMENT FOLLOW-UP

Title: Titre : CPCI 1228

English documentation Rev. B - Edition 2 – 28/07

Revised

Approved

Written

by

by

by A. MARQUES

D. PIMONT

Ph. DUTIN

on

on

on

28/07

28/07

28/07

Visa

Visa

Visa

Warning: Unless otherwise stated, this revision overwrites the previous one which must be destroyed, along with any copies given to your collaborators.

Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.

Table of the modifications Table des évolutions (mots clés)

Page n°

Chapter E IRIG B / TRIGGER Inputs 18

F.2.1 Control register 1 25/26

F.5. Clock and time-stamping 54/56

DSQ - 4.5.a - Indice G – 28/02 T.S.V.P.


2

NOTES :

!

WARNING

5V AND 3.3V PCI POWER SUPPLIES ARE USED IN THIS BOARD


3

CPCI 1228

SUMMARY

Chapter A Presentation .........................................5

A.1. Wiring and interconnection....................................................5

Chapter B PCI Interface.........................................6

B.1. Warnings ..................................................................................6

B.2. Literature ..................................................................................6

B.3. PCI configuration registers ....................................................7

B.4. PCI Operational Registers ....................................................10

Chapter C Analog inputs .....................................14

C.1. Instrumentation Amplifier.....................................................14

C.2. Analog digital conversion.....................................................16

Chapter D Digital inputs/outputs ........................17

D.1. “TTL” Inputs...........................................................................17

D.2. “TTL” Outputs........................................................................17

Chapter E IRIG B / TRIGGER Inputs...................18

E.1. IRIG Mode...............................................................................19

E.2. TRIGGER inputs ....................................................................20

E.3. Standalone Timer ..................................................................21

Chapter F Configuration registers .....................23

F.1. Introduction............................................................................23

F.2. Registers Definition...............................................................25

F.2.1. Control register 1 ........................................................25

F.2.2. Control Register 2.......................................................27

F.2.3. Register Timers ..........................................................34

F.2.4. I/O port register...........................................................36

F.2.5. Conversion start..........................................................36


4

F.2.6. Conversion stop..........................................................36

F.2.7. Gain register ...............................................................37

F.2.8. Interrupt registers........................................................38

F.3. Pattern Table..........................................................................41

F.4. Digital Filtering ......................................................................45

F.4.1. Introduction .................................................................45

F.4.2. Principle of decimation................................................46

F.4.3. Register Sample Frequency .......................................48

F.4.4. Filters register .............................................................49

F.4.5. Delay time...................................................................52

F.5. Clock and Time-stamping.....................................................56

Chapter G CPCI 1228 Board Initialization.........59

Chapter H Implementation .................................61

H.1. LEDs .......................................................................................61

H.2. Connection.............................................................................61

Chapitre I Interface Terminal Blocks ................64

Appendix .............................................................65

CONFIGURATION LAYOUT ....................................................................65

EQUIPMENT LAYOUT ...........................................................................65

PCI CONFIGURATION REGISTERS .........................................................65


5

Chapter A Presentation

The CPCI 1228 is a multifunction acquisition board designed to be plugged in a machine with PCI slots. It features 16 analog inputs configured in bipolar (± 10V FS), for isochronous 16-bit encoding up to 200kHz. It is also provided with 32 digital channels, i.e., 2 x 16-bit groups with programmable inputs or outputs. 8 out of the 32 digital channels may be interrupt sources. Several operating modes are available, together with timers for a number of boards. The acquisitions can also be time-stamped using an internal clock (±1µs). Each of the 16 analog channels has up to 11 digital programmable filters for each sampling frequency. Decimation (i.e., decreasing the sampling rate) prevents any aliasing due to the use of digital filters. The CPCI 1228 can access the PCI bus directly, for direct exchanges from one memory to the other (MASTER mode). One external clock (composite IRIG B) and various triggers (on PXI and external connectors) are also available. In addition, interface terminal blocks and conditioners are provided in order to adapt the board’s inputs and outputs to the process.

A.1. Wiring and interconnection

If the reader wishes it, application examples of interconnections are given on our Web site www.adas.fr Click on the icon: chapter “Wiring & Config”.


6

Chapter B PCI Interface

B.1. Warnings

The CPCI 1228 board plugs into a PC with CPCI 32-bit connectors (3U). Therefore, it features all the characteristics related to this environment (PCI 2.1.). The PCI interface is provided by a custom device: AMCC S5335

B.2. Literature We strongly advise the reader to obtain the following literature:

PCI HARDWARE and SOFTWARE

Architecture et Design Written by Edward SOLARI et George WILLSE

Edit. : ANNA BOOKS

AND

AMCC PCI CONTROLLERS

S5335 DATA BOOK


7

B.3. PCI configuration registers


8

For the CPCI 1228 board, registers are configured as follows at power-up:

03 02 01 00

8858 10E8

0 0

0 0A

FFFFFFC0H (mémoire)

FFFFE000H (mémoire)

FFF00000H (mémoire)

FFFF0001H (I/O)

00 00 01 0A

00

00

00

00

00

00

00

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

08H

04H

00H

D31 D0

0CH00

FF 0

STATE AT THE POWER-UP

CPCI 1228 - Rev. B - Edition 2 – 28/07 9

8858 10E8

0 0

FF 0 00 0A

FFFFFFC0H

FFFFE000H

FFF00000H

00

00

00

00

00

FFFF0001H

00

00

00 00 01 0A

D31 D0

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

0CH

08H

04H

00H

64K octets

BOOT

EPROM

AMCC atPower up

32 words

PCI OPERATION REGISTER

CONFIGURATION CPCI 1228

1M octets

Measure

Memory

228 Configuration – 8K octets D31 D7 D0 D16

BFM BHG NU

D4 D6 D5

Chan. N° 0H

+0FBC

+0FC0

+0FC4

+0FC8

+0FCC

+0FD0

+0FD4

+0FD8

+0FDC

+0FE0

+0FE4

+0FE8

+0FEC

+0FF0

+0FF4

+0FF8

+0FFC

Pattern table Not Used

Control 1

Control 2

Timer

32 I/O

START

STOP

Gain Amplifier Register

Decount Time Register

Day Hours

Minutes Seconds

Milliseconds Microseconds

Clear IRIG Registers

Day of start conversion

Minutes of start conversion

Milliseconds of start conversion

Hours of start conversion

Seconds of start conversion

Microseconds of start conversion

Clear IRIG Registers of start conversion

R/W

R/W

R/W

R/W

R/W

Wo

Wo

R/W

Wo

Wo

Ro

Ro

Ro

Ro

+1000

+1020 R/W Filter Registers

00H

+1024 Interrupts Register R/W

R/W

R/W

R/W


10

B.4. PCI Operational Registers

16 x 32-bit registers accessible via address 10H in configuration space (see chapter B.3. PCI CONFIGURATION REGISTERS).

10H FF FF FF C0

The CPCI 1228 board does not use all of the registers but only the following: These registers pertain to be board in two operating modes:

! “Slave” ! “Master”

Only the registers used by the CPCI 1228 board are explained below for each operating mode. For further information on all the 16 PCI operational registers, see Appendix at the end of this documentation.

OFFSET ADDRESSES ABBREVIATIONS REGISTER NAME

10H 14H 24H 28H 34H 38H 3CH

IMB1 IMB2

MWAR MWTC MBEF

INTCSR MCSR

Input MailBox Register 1 (p.89)

Input MailBox Register 2 (p.89)

Master Write Address Register (p.90)

Master Write Transfer Count Register (p.91)

MailBox Empty / Full status (p.94)

INTerrupt Control / Status Register (p.96)

Bus Master Control / Status Register (p.100)


11

>>> CPCI 1228 IN “SLAVE” MODE

This is the board’s basic mode. The registers concerned are:

OFFSET ADDRESSES ABBREVIATIONS VALUES TO BE WRITTEN

10H 34H 38H 3CH

IMB1 MBEF

INTCSR MCSR

FF (H) One bit read (bits 16 – 19)

Typical Word Bus Master Control / Status Register

The MCSR (3CH) register Initializes the CPCI 1228 board. Bit D24 set to “1” resets the CPCI 1228 board. The stored values remain unchanged.

The IMB1 (10H) register Written by the CPCI 1228 board when the RAM is full. (FFFFFFFFH written in Mailbox 1).

The MBEF (34H) register This is the Mailbox status register. When the RAM is full, the CPCI 1228 board writes into Mailbox 1. The MBEF register takes value 000F0000H. Reading the IMB1 (10H) register resets MBEF status register to value 0.

The INTCSR (38H) register Used to handle interrupts (optional). The interrupt source may be incoming Mailbox 1 or incoming Mailbox 2 (see section F.2.8.). Set bit D12 to “1” in order to enable the interrupt from Mailbox 1. This will notify the user that a buffer is full.


12

>>> CPCI 1228 IN "MASTER” MODE

In this case, the CPCI 1228 board takes over the control of the PCI bus in order to exchange data from one memory to another. The registers concerned are:

OFFSET ADDRESSES ABBREVIATIONS VALUE TO BE WRITTEN

24H 28H 38H 3CH

MWAR MWTC INTCR MCSR

Target base address Length of exchange Typical Word Bus Master Control

When used in Master mode, the CPCI 1228 board must be initialized as follows: The MWAR (24H) register contains the address at which the CPCI 1228 board will start transferring the data. This register is incremented automatically during the exchanges. The MWTC (28H) register contains the number of bytes to be transferred by the CPCI 1228 board (a multiple de 4). This number of bytes can be different than the RAM width of the CPCI 1228 board. The MCSR (3CH) register must have bit D10 set, in order to start the exchange. In MASTER mode, the maximal data rate may be up to 66 MB/s.

Interrupts: One interrupt can be generated when the byte transfer counter (MWTC) has a value of zero. This interrupt must be first activated by setting bit D14 in INTCSR register. Another Mailbox 1 interrupt can be activated to notify the user that one data block has been transferred. The activation procedure is the same as in Slave mode (see previous page).


13

Operating mode The CPCI 1228 board is set as Master (“master”), bit D16 = 1 in control register 1 (Base + 0FC0H) in configuration space. The CPCI 1228 board must be in “Flip/Flop” mode, bit D17 = 0 in control register 1. The pattern table is initialized along with control registers and PCI registers (MWAR, MWTC, MCSR and INTCSR). Acquisitions are started using the START command. Note that, when in acquisition mode, the CPCI 1228 board's registers cannot be accessed and its pattern table cannot be changed. Acquisitions can only be stopped by an EXTERNAL STOP or a reset through MSCR (3CH) register of bit D24. When RAM 1 is full, the CPCI 1228 board requests the PCI bus and starts transferring data at MWAR register’s address. The number of bytes transferred corresponds to the number of channels in a pattern multiplied by the number of patterns, then the transfer stops (even with a higher number of bytes in MWTC register). Several consecutive “Flip/Flops” can be transferred to central memory. In this case, the MWTC register will contain the number of bytes (that is a multiple of the number of channels) multiplied by the number of patterns multiplied by the number of Flip/Flops.

Example : Base address MWAR = 400000H

# of bytes in MWTC = 100000H (1M bytes) Bit D10 of MCSR register set to “1”. Pattern table = 16 # of patterns = 2000H i.e., 8192 patterns by “Flip/Flop” (256 Kbytes) The CPCI 1228 board will perform 4 RAM changeovers before MWTC counter is reset to zero. Then, it will no more transfer data but will keep acquiring data. To restart the transfer, simply reset MWAR and MWTC registers. Nevertheless, you should first erase the FIFOs (bit D26 in MCSR register), if the CPU is not able to reset the registers before the next "Flip/Flop". At maximum sampling frequency, we advise using at least 8 patterns per RAM in order to receive all acquisitions properly.

!

!


14

Chapter C Analog inputs C.1. Instrumentation Amplifier

An instrumentation amplifier with software-programmable gains is provided at each of the 16 analog inputs in the CPCI 1228. The gains are 1, 2, 5 and 10. The diagram below shows the structure of each input: VIN max = VIN (+) – VIN (-) = ± 10V FS

IN (+)

IN (-)

GND

499KΩ

499KΩ

Analog ground

SPGA Amplifier

gains 1, 2, 5 & 10

GAIN FS

1 +/- 10,00V

2 +/- 5,00V

5 +/- 2,00V

10 +/- 1,00V


15

The protection system limits the input dynamic range of the instrumentation amplifier. The allowed voltages are ± 40V. Moreover, input impedance remains high, even after switching off the board. Please note: Differential wiring involves 3 wires: IN(+) ; IN(-) and GND An example of differential acquisition is:

IN (+)

IN (-)

GND

+

V1

Measure = 1V

Differential amplifier

-

2V

1V

2V

V2

+V

Vdifferential = V2 –V1 = 3V – 2V = 1V When using the board in “single-wire” mode:

! Enter the signal between IN(+) and GND and

! Connect IN(-) to GND


16

C.2. Analog digital conversion

Each channel has its own ADS (an A/D converter with a built-in sample-and-hold device). The conversion uses a series of approximations in a C/2C network. This type of technology is based on a built-in header sample-and-hold device. Actual encoding takes place exactly at the same time as the conversion command. Moreover, the converter acts independently of the sampling rate, hence its performances are much higher than those of Σ Δ type converters over wide frequency ranges.

CODING INPUT F F F F + PE - 1 LSB 8 0 0 0 0 0 0 0 0 - PE


17

Chapter D Digital inputs/outputs

In addition to 16 isochronous analog inputs, the CPCI 1228 board can handle 32 “TTL” inputs/outputs split into two 16-bit word groups, i.e.,:

! 32 “TTL” inputs ! 32 “TTL” outputs ! 16 “TTL” inputs + 16 “TTL” outputs

The selection is done from Control register 2 (bits 24 to 27).

D.1. “TTL” Inputs In this case, TTL inputs may be:

! acquired as analog inputs into two 16-bit logical channels ! read independently as a standard TORS I/O board at address

+ 0FCC(H) ! interrupt sources (first 8 channels) if activated (base address

+ 1024(H))

D.2. “TTL” Outputs When using output logical channels, they are driven by writing 32-bit words at base address + 0FCC(H).


18

Chapter E IRIG B / TRIGGER Inputs

The board features a front panel ‘IRIG B’ or ‘TRIGGER’ LEMO 1 point plug. This chapter indicates how to use the plug.


19

E.1. IRIG Mode

Composite IRIG B is an analog signal the frame of which is repeated every second and carries time-related information (date, countdown time + 1KHz clock). Please refer to the applicable standard. To increase the resolution to 1µs, the board has its own phase-locked oscillator (32MHz PLL) which is divided so as to provide a 1MHz frequency synchronous to IRIG time. A 32-bit timer receives (32:4) 8MHz to provide acquisition sync. for all boards with a resolution of 125ns.

DESERIALIZATION

IRIG B

32-bit TIMER

DATE REGISTERS

1µS RESOLUTION

A/D

PLL

÷ 4

÷ 32000

MASTER BOARD

Sync. 32MHz

8MHz

1KHz

Analog IRIG B input

TRIGGER input

INTERNAL + TRIGGER acquisition pulses

OR

The board in “SLAVE” TRIGGER mode receives trigger pulses from the front panel LEMO plug. It can also synchronize output racks or acquisition boards. The CPCI 1228 board decodes IRIG time, if present. Data are written into registers provided for that purpose. They can be read independently or considered as channels. In this case, acquisition blocks (FLIP-FLOP) contain exact TRIGGERS time.


20

E.2. TRIGGER inputs

In non-IRIG mode, the board’s acquisitions are clocked by an external trigger. In “MASTER” TRIGGER mode, the board outputs trigger pulses via the backplane in order to synchronize the other boards.

CPCI 1228 BOARD

MASTER

CPCI 1228 BOARD

SLAVE

CPCI 1228 BOARD

MASTER

CPCI 1264 BOARD

64 I/O TORS

CPCI 1228 BOARD

SLAVE

FdP n° 1

FdP n° 2

TRIG1

Generator

« TTL » external Trigger input

ExternalTTL input

LEMO

TRIG0

TRIG0

TRIG1

TRIG0

TRIG0

All boards are synchronized in this way.


21

E.3. Standalone Timer

Acquisitions need not necessarily be correlated using an external time-stamping. Built-in resources, within the board, can also be used to recover the necessary time signals. The timer is reset to “zero” upon starting the “Master” board and is incremented as in IRIG B mode (using an internal oscillator). This increments the time counters using a 1-µs resolution. The slave boards are clocked by an external TRIGGER.


22

Synoptic of the LEMO CPCI 1228

SYNCIN (Input Trigger)

IRIG Frame decoded + Clock

at 1kHz

LEMO OUT

SYNCOUT (Input Trigger) Selection of the Trigger source

upon control register 2

PLL 32 MHz

LEMOIRIG B or Trigger

1kHz if IRIG prsence

1 point


23

Chapter F Configuration registers F.1. Introduction

We have described in chapter B, "PCI Interface", the management of the physical interface between the CPCI 1228 board and the PCI bus. The CPCI 1228 board comprises 4 “memory spaces”: Operational configuration PCI space 10 (H) Boot PROM space 30 (H) The board’s memory space (RAM) 18 (H) The board’s configuration space 14 (H) These memory spaces will be detailed in this chapter. They include all necessary resources to use the CPCI 1228 board in each of the four operating modes. The “board configuration” space comprises two areas: “Pattern table” area (Base + 0(H) à 0FBF(H)) “Registers” area (Base + 0FC0(H) à 1024(H)) These areas are shown in the following mapping.

>>>Note: After starting acquisition, it will be impossible to read or change these registers.


24

Base +0H

R/W Pattern Table

Base + 0FBCHR/W Control Register 1 Base + 0FC0H R/W Control Register 2 Base + 0FC4H R/W LF Timer HF Timer Base + 0FC8H R/W I/O Register Base + 0FCCHWo START Base + 0FD0H Wo STOP Base + 0FD4H R/W Gain Amplifier Register Base + 0FD8H R/W Decount Time Register Base + 0FDCHR/W Day Hour Base + 0FE0H R/W Minutes Seconds Base + 0FE4H Ro Milliseconds Microseconds Base + 0FE8H Wo Clear IRIG Base + 0FECHRo Day of Start Conversion Hour of Start Conversion Base + 0FF0H Ro Minutes of Start Conversion Seconds of Start Conversion Base + 0FF4H Ro Ms of Start Conversion µs of Start Conversion Base + 0FF8H Wo Clear Time of Start Conversion Base + 0FFCH R/W Filter Register for channels 0 & 1 Base + 1000H R/W Filter Register for channels 2 & 3 Base + 1004H R/W Filter Register for channels 4 & 5 Base + 1008H R/W Filter Register for channels 6 & 7 Base + 100CH R/W Filter Register for channels 8 & 9 Base + 1010H R/W Filter Register for channels 10 & 11 Base + 1014H R/W Filter Register for channels 12 & 13 Base + 1018H R/W Filter Register for channels 14 & 15 Base + 101CH R/W Sample Frequency Register Base + 1020H R/W Interrupts Register Base + 1024H

MAPPING CONFIGURATION – 8k octets


25

F.2. Registers Definition

F.2.1. Control register 1 Base address + 0FC0 (H) Read and write access. Power-up state 00000000H.

>>> Bits D0 to D15: Number of patterns The number of patterns multiplied by the number of channels/pattern must not exceed the maximum size of the measurement memory (256k words).

Example: Let us consider a pattern table with 64 channels, and up to 4096 patterns (1000H).

>>> Bit D16: MASTER / SLAVE

Bit D16 set to “0” switches the CPCI 1228 to SLAVE mode Bit D16 set to “1” switches the CPCI 1228 to MASTER mode

D31 D20 D19 D18 D17 D16 D15 D0

Not Used Nbre de motifs

« Flip/Flop » /

« One Shot »

Slave / Master

STAT ACQ

STAT RAM

D21 D22

Not Used

D30

TD &


26

>>> Bit D17 : “Flip/Flop” / “One Shot”

D17 = 0 FLIP/FLOP mode D17 = 1 ONE SHOT mode “ONE SHOT” mode is used only when the CPCI 1228 board is in SLAVE mode. Acquisition stops upon the number of patterns reaching the original value loaded.

>>>Bits D18 & D19: unused bits. >>>Bit D20: Acquisition status. Read access only.

D20 = 0 No acquisition in progress. D20 = 1 Acquisition in progress.

>>>Bit D21: RAM 1 or RAM 2 status. Read access only.

This bit is valid only when an acquisition is in progress. D21 = 0 Acquisition in progress in RAM 1. RAM 2 can be read. D21 = 1 Acquisition in progress in RAM 2. RAM 1 can be read.

>>> Bits D22 to D30: These bits are always read as "0". >>> Bits D31: TD & IRIG D31 = 0 Countdown is updated by IRIG external clock D31 = 1 Countdown is independent of IRIG external clock This bit allows to control countdown depending composite IRIG B clock is present or not. If D31 is at “1”, countdown is managed in internal. It’s possible to stop it or to modify it even in IRIG presence. In the opposite case, it’s always updated each new composite IRIG B frame. As it has no external clock, countdown keep the last value of the decoded frame.


27

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

Signals direction

Selects LEMOUpdates the clock

Selects TRIG 2 edge

Digital port direction Activates digital port

IRIG lost IRIG present

Valid time

Updates IRIG if clock loss

F.2.2. Control Register 2 Base address + 0FC4 (H) Read and write access, (excluding bits 28, 29, and 30). Power-up state 00000000H.


START

SYNC.

TRIG0

TRIG1

SYNCOUT

TRIG2

Selects triggers edges

Acquisition sync. on IRIG B clock


28

>>>Bits D0 & D1 : Select the START command

D1 D0 START controlled by 0 0 SOFT (Base + 0FD0H) 0 1 External sync. (SYNCIN) 1 0 TRIGSTAR 1 1 TRIG0

START command synoptic 00

01

10

11

START SYNCIN

TRIG0

SOFT

TRIGSTAR

>>>Bits D3 & D2 : Select sampling frequency source

D3 D2 Sampled by 0 0 TIMER HF 0 1 TIMER LF 1 0 External sync. (SYNCIN) 1 1 TRIG2

Sampling frequency source synoptic 00

01

10

11

Sample Frequency

TIMER LF

TRIG2

TIMER HF

SYNCIN


29

>>>Bits D5 & D4 : Select TRIG0

D5 D4 TRIG0 generated by 0 0 TIMER HF 0 1 TIMER LF 1 0 START SOFT 1 1 External sync. (SYNCIN)

Notes: TRIG0 must be set in order to output a signal (bit 16 of control register 2 set to "1").

TRIG0 synoptic 00

01

10

11

TRIG0 TIMER LF

SYNCIN

TIMER HF

START SOFT


D7 D6 TRIG1 generated by 0 0 TIMER HF 0 1 TIMER LF 1 0 START SOFT 1 1 External sync. (SYNCIN)


TRIG1 synoptic 00

01

10

11

TRIG1 TIMER LF

SYNCIN

TIMER HF

START SOFT


30

>>>Bits D9 & D8 : Select external sync. (SYNCOUT)

D7 D6 SYNCOUT generated by 0 0 TIMER HF 0 1 TIMER LF 1 0 TRIG0 1 1 TRIG1

Notes: SYNCOUT must be set in order to output a signal (bit 18 of control register 2 set to "1").

SYNCOUT synoptic 00

01

10

11

SYNCOUTTIMER LF

TRIG1

TIMER HF

TRIG0


D11 D10 TRIG2 generated by

0 0 TIMER HF 0 1 TIMER LF 1 0 START SOFT 1 1 External sync. (SYNCIN)


TRIG2 synoptic 00

01

10

11

TRIG2 TIMER LF

SYNCIN

TIMER HF

START SOFT


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>>>Bit D12 : Select TRIG0 active edge

D12 = 0 TRIG0 active on leading edge D12 = 1 TRIG0 active on falling edge

>>>Bit D13 : Select TRIG1 active edge D13 = 0 TRIG1 active on leading edge D13 = 1 TRIG1 active on falling edge

>>>Bit D14 : Select TRIGSTAR active edge D14 = 0 TRIGSTAR active on leading edge D14 = 1 TRIGSTAR active on falling edge

>>>Bit D15 : Selects SYNCIN active edge D15 = 0 SYNCIN active on leading edge D15 = 1 SYNCIN active on falling edge

>>>Bit D16 : Activates TRIG0 output D16 = 0 TRIG0 output OFF D16 = 1 TRIG0 output ON


>>>Bit D18 : Activates SYNCOUT output (external sync.) D18 = 0 SYNCOUT output OFF D18 = 1 SYNCOUT output ON


>>>Bit D20 : Selects the use of LEMO D20 = 0 SYNCOUT ON, IRIG OFF (output) D20 = 1 IRIG ON SYNCOUT OFF (input)


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>>>Bit D21 : Updates IRIG registers D21 = 0 Updated by sampling frequency source. D21 = 1 Updated by reading one of the 3 IRIG registers (See Mapping configuration).

>>>Bits D22 Selects TRIG2 active edge D22 = 0 TRIG2 active on leading edge D22 = 1 TRIG2 active on falling edge

>>>Bit D23 : Updated IRIG in case of loss D 23 = 0 The hour is updated at every new catching of the IRIG clock D 23 = 1 In case of IRIG loss, the hour stays on internal clock even if the

IRIG comes back. It is necessary to oblige this bit at 0 for recover the new IRIG hour.

>>>Bit D24 : Direction of digital port group 1 (31 to 16) D24 = 0 Group 1 as input D24 = 1 Group 1 as output

>>>Bit D25 : Direction of digital port group 0 (15 to 0) D25 = 0 Group 0 as input D25 = 1 Group 0 as output

>>>Bit D26 : Activates digital port group 1 (31 to 16) at the output D26 = 0 Group 1 ON D27 = 1 Group 1 OFF

>>>Bit D27 : Activates digital port group 0 (15 to 0) at the output D27 = 0 Group 0 ON D27 = 1 Group 0 OFF

>>>Bit D28 : IRIG present/absent. Read access only. D28 = 0 IRIG time absent D28 = 1 IRIG time present

>>>Bit D29 : IRIG time valid. Read access only. D29 = 0 IRIG time ≠ internal clock D29 = 1 IRIG time = internal clock (valid)


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!

>>>Bit D30 : IRIG signal lost. Read access only.

D30 = 0 No loss D30 = 1 IRIG signal lost

>>>Bit D31 : SYNC signal synchronized to IRIG time D31 = 0 No sync. D31 = 1 SYNC signal synchronized

This bit begins the acquisition sequence only at the next TOP of the second, stricly if the IRIG hour is present. Note: In order for CPCI 1228 board to capture IRIG B time, make sure to set bit D20 to “1”.

The reading of this register resets bits D30 and D28 at value “0” if they are

read at “1”.


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F.2.3. Register Timers Base address + 0FC8 (h) Read and write access. Power-up state 0000 0000H.

D31 D16 D15 D0

TIMER LF TIMER HF

These timers are used to trigger conversions at regular intervals, according to bits D2 & D3 of Control 2 register. They can also be used to synchronize several boards or several racks.

>>>High frequency timer Base frequency is Fclk = 8 MHz. n min = 39 (27H) n max = 65535 (FFFF H) Output frequency:

1+

=nFclkFs

n = 39 Fs = 200 kHz (max sample frequency) n = 65535 Fs = 122 Hz (min sample frequency)


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>>>Low frequency timer

Base frequency is Fclk = 10 kHz. n mini = 0 (0H) n max = 65535 (FFFF H) Output frequency is n = 0 Fs = 10 kHz (max sample frequency) n = 65535 Fs = 0,15 Hz (min sample frequency) Both timers are only operational when acquisitions are in progress (this is essential for multi-board synchronization).

!


36

F.2.4. I/O port register Base address + 0FCC (H) Read and write access. Power-up state FFFFFFFFH (Read mode). The CPCI 1228 board features 32 x TTL I/Os on one ANA µD68-pt connector referred below as I/O PORT. The following chapter shows how to read and write the digital data. Note that the first 8 bits can generate interrupts when programmed as input (see chapter F.2.8.). Each bit of this register corresponds to a logical channel. The 32 channels of the port are broken down into 2 groups. (see Chapter D. Digital Inputs / Outputs). Note that the value of the digital port can be loaded at any time into this register (or vice versa) with a read (or a write) according to the group’s direction, or upon starting an acquisition. F.2.5. Conversion start Base address + 0FD0 (H) Write access only. A software conversion start is enabled by a dummy writing at base address + 0FD0H. F.2.6. Conversion stop Base address + 0FD4 (H) Write access only. A software conversion stop is enabled by a dummy writing at base address + 0FD4H.


37

F.2.7. Gain register Base address+ 0FD8 (H) Read and write access. Power-up state 0000 0000H All 32 bits are used to set the gains of the 16 analog inputs.


G7 G6 G5 G4 G3 G2 G1 G0


G7 G6 G5 G4 G3 G2 G1 G0

The gain bits of each Gn analog input are D2n+1 and D2n. They correspond to:

D2n+1 D2n Gain of relevant input 0 0 1 0 1 2 1 0 5 1 1 10


38

F.2.8. Interrupt registers Base address+ 1024 (H) Read and write access. Power-up state 00000000H

>> Bits D0 to D7 : Select the interrupts DX = 0 Interrupt from VDX digital channel ‘OFF’ DX = 1 Interrupt from VDX digital channel ‘ON’

D31 D15 D11 D10 D9 D8 D7 D0

Select interrupts

Not used

D16 D23D24

Not used

Select debouncing frequency

Not used

Select interrupt active edge


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>> Bits D10 & D9 : Select the debouncing frequency

D10 D9 Sampling frequency 0 0 Debouncing disabled 0 1 3 MHz 1 0 300 kHz 1 1 30 kHz

A debouncer is used to suppress spurious frequencies.

The maximum allowed frequency, when using the debouncer, is the sampling frequency divided by 3.

Sampling freq. Filtered pulses Max. frequency 3 MHz < 1μs 1 MHz

300 kHz < 10μs 100 kHz 30 kHz < 100μs 10 kHz

>> Bits D23 to D16 : Select the Interrupt active edge D16 = 0 (or 1) VD0 active on leading (or falling) edge D17 = 0 (or 1) VD1 active on leading (or falling) edge D18 = 0 (or 1) VD2 active on leading (or falling) edge D19 = 0 (or 1) VD3 active on leading (or falling) edge D20 = 0 (or 1) VD4 active on leading (or falling) edge D21 = 0 (or 1) VD5 active on leading (or falling) edge D22 = 0 (or 1) VD6 active on leading (or falling) edge D23 = 0 (or 1) VD7 active on leading (or falling) edge

In order for an interrupt to be active, the group to which it belongs must be set as the input (bits D24 and D25 of Control register 2)


40

When an interrupt occurs, only the value of digital channels is written in register Incoming Mailbox 2 (14H) excluding the channels for which the interrupt was activated. When an interrupt is activated, a logical “1” is also sent to IMB2 for the channel(s) which caused the writing, or a logical “0” for other channels where no interrupt took place. After sending the value, register MBEF (34H) is switched to value 00F00000H (Incoming Mailbox 2 full). Reading register IMB2 allows status register MBEF to be set to 0, but also resets digital channels interrupts. Until register IMB2 is read, all active interrupts are saved. If another interrupt occurs, the value of the digital channels is again sent to register Incoming MailBox 2, and the new interrupt(s) are saved together with the former ones. You can generate an interrupt on PCI bus when an interrupt occurs in one of the digital channels. This is made possible by first setting bits D12 and D10 of register INTCSR (38H) to “1” . It is impossible to receive both a MailBox 1 interrupt and a MailBox 2 interrupt on PCI bus! First choose among the two types of interrupts.

!


41

F.3. Pattern Table

The CPCI 1228 board has a pattern table of 4K (8 working bits), i.e., 1008 bytes, between base address + 0 (H) and base address + 0FBF (H). This is a 32-bit read / write table OFF acquisitions. Bits D31 to D8 are not used. This table contains the base pattern for organizing the storage in the measurement RAM. The first channel scanned will be the channel written at low address, then the channel written at low address + 4, and so on. This pattern is repeated NM (# of patterns) times in measurement RAM. You set NM value in Control register 1 (see D.2.1. Control register 1). The 16-bit NM register repeats the pattern table up to 64K times in the measurement RAM. You need not use the whole table. Simply define its length using the End-of-pattern bit (BFM) located in the last channel to be saved. The pattern table is subdivided into sub-patterns. Note: The pattern table must have at least 2 sub-patterns of one channel each, or a pattern or sub-pattern of 2 channels. The product (number of channels x number of patterns) must be an even number.

>>>WORD FORMAT IN THE PATTERN TABLE

D (4 : 0) : Channel number D5 : Not used. D6 : Sub-pattern end bit D7 : Pattern end bit

D7 D6 D5 D4 D0

BFM BHG NU CHANNEL No.


42

>>>ACQUISITION CHANNEL NUMBER

D(4:0) in hex. Corresponding channel

00h Channel 0 01h Channel 1 02h Channel 2 03h Channel 3 04h Channel 4 05h Channel 5 06h Channel 6 07h Channel 7 08h Channel 8 09h Channel 9 0Ah Channel 10 0Bh Channel 11 0Ch Channel 12 0Dh Channel 13 0Eh Channel 14 0Fh Channel 15 10h Pattern number (MSB) 11h Pattern number (LSB) 12h Group 1 of I/Os 13h Group 0 of I/Os 14h Current-time day 15h Current-time hour 16h Current-time minutes 17h Current-time seconds 18h Current-time ms 19h Current-time µs 1Ah Function bits & counter-time hour 1Bh Counter-time minutes & seconds


43

>>>SUB-PATTERN END BIT (BHG)

The sub-pattern end bit denotes the last channel among the sub-patterns. A single sub-pattern may include the data for all 26 channels. Sub-patterns are useful for saving signal samples at different sampling frequencies. >>>Example: A pattern comprising 2 sub-patterns, as follows: 1 sub-pattern comprising channels 0 and 1; 1 sub-pattern comprising channel 0. With a sampling frequency of 200 kHz, channel 1 will have a sampling frequency the half (100 kHz) of channel 0, that is one sample out of two. When a pattern comprises several sub-patterns, it is not necessary to add a sub-pattern end flag to the last channel in the pattern. Simply set the pattern end bit to "1".


44

>>>PATTERN END BIT (BFM)

The pattern end bit denotes the pattern length. D7 = 0 Switch to next channel D7 = 1 Last channel scanned in the pattern, the next channel will be the first in the pattern. The number of measurements stored in the measurement RAMs depends of the number of patterns (NM) and on the number of channels in each pattern. Make sure that the product (number of patterns (NM) x number of channels in each sub-pattern) is consistent with the size of the measurements RAMs (256k measurements per block). >>>Example 1: If NM = 65535 (FFFFH), the max pattern will be 4 channels, e.g. one pattern comprising channels 0-3. >>>Example 2: With a pattern comprising 4 sub-patterns, that is: 1 sub-pattern comprising the channels day, hour, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 = 14 channels; 1 sub-pattern comprising the channels 0, 1, 2, 3, 9, 10 = 6 channels; 1 sub-pattern comprising the channels 0, 1, 2, 3, 9, 10 = 6 channels; 1 sub-pattern comprising the channels 0, 1, 2, 3, 9, 10 = 6 channels. The total number of channels in the pattern is 32 channels. The number of patterns (NM) cannot exceed 8192 (2000H).


45

F.4. Digital Filtering

F.4.1. Introduction The CPCI 1228 board has 8 registers for defining the cutoff frequency of the programmable digital filter for each of the 16 analog inputs. These are read/write 32-bit registers OFF acquisitions. Bits D31 to D20 and D15 to D4 are not used and are read as “0”. Register “SF” (Sample Frequency) selects the decimation ratio from base sampling frequency (Fs). This is a read/write 32-bit register OFF acquisitions. Bits D31 to D4 are not used and are read as “0”.

D31 D20 D19 D16 D15 D4 D3 D0

Not Used FILTER 1 Not Used FILTER 0 Base + 1000 Not Used FILTER 3 Not Used FILTER 2 Base + 1004 Not Used FILTER 5 Not Used FILTER 4 Base + 1008 Not Used FILTER 7 Not Used FILTER 6 Base + 100C Not Used FILTER 9 Not Used FILTER 8 Base + 1010 Not Used FILTER 11 Not Used FILTER 10 Base + 1014 Not Used FILTER 13 Not Used FILTER 12 Base + 1018 Not Used FILTER 15 Not Used FILTER 14 Base + 101C

Not Used SF Base + 1020

Note:

When writing into one of the 8 filter registers, it is necessary to wait at least 4 µs for each register, in order for the board to initialize those digital filters. Minimum wait time for register SF will be 32 μs.


46

F.4.2. Principle of decimation The main characteristic of the CPCI 1228 board is that it is able to decimate the sampling frequency of ADCs. This filtering technique aims at decreasing the sampling frequency of analog-digital conversions by an integer ratio, while moving away the first overlap (Shannon’s theorem). The main strength of this technology used in ΣΔ converters is to use aliasing filter of low order compared to those generally included with digital filters. There is still some aliasing whichever the type of digital filter used. But it can be moved away by oversampling the signal. Let us assume an application requiring a 40kHz filter on samples occurring every 10 µs. In the event of a FIR digital filter, the first overlap (the most critical) appears between 40 and 60kHz. It can be minimized using a Butterworth analog filter with a cutoff frequency of 50kHz in order to avoid reducing the bandwidth.

Figure 1: Limitation of digital filters


47

Since the transition band is very small (20kHz), we find that an analog filter is unable to cut down the first overlap by more than 50dB, even with a 32th-order aliasing filter. By oversampling the signal at 200kHz, then by decimating it by 2, the overlapping of the FIR filter having a cutoff frequency Fc = 40kHz moves away at 160kHz. Indeed, a decimation filter always comes with a digital filter, which limits the signal bandwidth to half its output sampling frequency. In the present case, the digital filter of the decimation filter has a cutoff frequency of 50kHz which avoids any aliasing due to decimation. Therefore it becomes much easier to filter out the first aliasing with an analog filter of average order. Presently, a 8th-order filter perfectly cuts down the first aliasing at 160kHz (figure below).

Figure 2: Decimation filtering

In brief, thanks to the sampling frequency decimation technique, the CPCI 1228 provides all the main advantages of digital filters (very little band-pass reduction, narrow transition band, high attenuation in the rejected band) while limiting the overlapping effects.


48

F.4.3. Register Sample Frequency Prior to setting up the digital filters for each channel, it is necessary to set the base sampling frequency. This Fs frequency is the sampling frequency of analog-digital converters. This is the source used by bits D3 and D2 of Control register 2 (base address + 0FC4H). This frequency can be decimated by an integer number through the Sample Frequency register (base address + 1020H).

SAMPLE FREQUENCY (Fd) HEXA VALUE [D3 : D0] FS 0h

FS/2 1h FS/4 2h FS/5 3h FS/8 4h

FS/10 5h FS/20 6h FS/40 7h FS/50 8h FS/80 9h

FS/100 Ah FS/200 Bh FS/400 Ch FS/500 Dh FS/800 Eh

FS/1000 Fh

Example Let us assume an application requiring acquisitions at 2ksamples/s using the HF timer (base address + 0FC8H) HF timer = 27H FS = 200kHz SF = AH We obtain a sampling frequency (Fs) for analog-digital converters of 200kHz decimated by a ratio of 100, that is Fd = Fs/100 = 2kHz This frequency will be the base sampling frequency of analog filters (Fd).


49

F.4.4. Filters register The cutoff frequency of digital filters is defined as a function of the output decimated sampling frequency (Fd). The CPCI 1228 has no less than 11 programmable digital filters per sampling frequency. A total of 48 cutoff frequencies are available from a single ADC sampling frequency (Fs).

CUT FREQUENCY (Fc)

HEXA VALUE [D3 : D0] et [D19 : D16]

Without FIR 0h Fd/2,5 1h Fd/4 2h Fd/5 3h Fd/8 4h

Fd/10 5h Fd/16 6h Fd/20 7h Fd/25 8h Fd/32 9h Fd/40 Ah Fd/50 Bh

Reserved Ch Reserved Dh Reserved Eh Reserved Fh

Note: When no digital filter is used, the signal bandwidth is [Fd/2 – 0] except where Fd = Fs with a bandwidth of [Fs -0] Example: Fd = 10kHz The signal bandwidth without a FIR filter is [5kHz – 0] The table below exemplifies various cutoff frequencies available from an ADC sampling frequency of 200kHz.


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Fc Fd 200kHz 100kHz 50kHz 40kHz 25kHz 20kHz 10kHz 5kHz 4kHz 2,5kHz 2kHz 1kHz 500Hz 400Hz 250Hz 200Hz

80kHz 50kHz 40kHz 25kHz 20kHz 16kHz

12,5kHz 10kHz 8kHz

6,25kHz 5kHz 4kHz

3,125kHz 2,5kHz 2kHz

1,6kHz 1,563kHz 1,25kHz

1kHz 800Hz

781,25Hz 625Hz 500Hz 400Hz

312,5Hz 250Hz 200Hz 160Hz

156,25Hz 125Hz 100Hz 80Hz


51

Fc Fd 200kHz 100kHz 50kHz 40kHz 25kHz 20kHz 10kHz 5kHz 4kHz 2,5kHz 2kHz 1kHz 500Hz 400Hz 250Hz 200Hz

78,13Hz 62,5Hz 50Hz 40Hz

31,3Hz 25Hz 20Hz 16Hz

15,6Hz 12,5Hz 10Hz 8Hz

7,8Hz 6,3Hz 5Hz 4Hz


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F.4.5. Delay time For a time-stamped pattern, the recording time does not correspond to the acquisition time of the various samples but to a post-recording time (decimation and/or FIR). The delay (processing) time is essential in order to determine with accuracy the acquisition instant of a sample from a time-stamped pattern. The delay time (Td) is determined by the ADC sampling frequency, the various decimation ratios (R, F0, F1) and the use (or not) of a FIR filter. With no decimation: w/o a FIR with a FIR 63 Td = 0 Td = Fs With a decimation: w/o a FIR with a FIR 63 63 Td = Td = (1 + R) Fs Fs With two decimation: w/o a FIR with a FIR 63 63 Td = (1 + F0) Td = (1 + F0 + R) Fs Fs The table below shows the various decimation ratios required for computing the delay time (Td).


53

DECIMATION RATIO « R » R = F0 x F1

FIRST DECIMATION

RATIO F0

SECOND DECIMATION

RATIO F1 1 - - 2 2 - 4 2 2 5 5 - 8 4 2

10 5 2 20 5 4 40 10 4 50 10 5 80 16 5

100 10 10 200 25 8 400 50 8 500 50 10 800 50 16

1000 50 20


54

This table, given by way of example, lists all delay times from an ADC sampling frequency of 200kHz. Since the decimation frequency is the same for all analog channels, it is essential to select, if necessary, for each channel used, a digital filter with a cutoff frequency in line with the sampling frequency. You may also use no digital filter at the output of the decimation filter.

DELAY TIME (Td) DECIMATION FREQUENCY Fd

DECIMATION RATION R WITH FIR WITHOUT FIR

200kHz - 315µs 0 100kHz 2 945µs 315µs 50kHz 4 2,205ms 945µs 40kHz 5 1,89ms 315µs 25kHz 8 4,095ms 1,575ms 20kHz 10 5,04ms 1,89ms 10kHz 20 8,19ms 1,89ms 5kHz 40 16,065ms 3,465ms 4kHz 50 19,215ms 3,465ms 2,5kHz 80 30,555ms 5,355ms 2kHz 100 34,965ms 3,365ms 1kHz 200 71,190ms 8,19ms 500Hz 400 142,065ms 16,065ms 400Hz 500 173,565ms 16,065ms 250Hz 800 268,065ms 16,065ms 200Hz 1000 337,065ms 16,065ms


55

Example: FS = 200kHz with a decimation ratio of 20, i.e., a decimation frequency of 10kHz. The cutoff frequencies of the filters available for this frequency are: 4kHz; 2,5kHz; 2kHz; 1,25kHz; 1kHz; 685Hz; 500Hz; 400Hz; 312,5Hz; 250Hz and 200Hz. On the other hand, let us assume a filtered channel and an unfiltered channel; the recording time of the first sample will be: t0 + tdF.

t0 td tdF

« START ACQUISITION »

DELAY TIME WITHOUT FIR

DELAY TIME WITH FIR

START OF RECORD

The CPCI 1228 does not have an aliasing filter. ADAS provides STB 6x2 (8 channels) or STB 658 (16 channels) conditioners along with the accompanying ACM/IN modules named “Butterworth 8th-order analog filters“ for various frequencies (see chapter I).

!


56

F.5. Clock and Time-stamping

The CPCI 1228 board makes it possible to capture IRIG B time. This 1-KHz external clock is translated into a 32-MHz frequency, with a PLL allowing to “lock” the internal clock to the external clock. This allows very accurate time-stamping within one µs and with no time drift at all. This traceability lets you time-stamp any data captured at any given time. The synchronization tick (and therefore the analog/digital conversion) is also “locked” to the external clock. If the external clock is lost, the CPCI 1228 board switches to the internal clock and remains synchronized to its own 32-MHZ clock. Moreover, bit D30 of Control register 2 is set to “1” to inform the user that the external clock has been lost. Bit D28 of the same register is also set to “0” to indicate that the external clock is missing. At each IRIG B frame received, the external clock’s time is compared to the internal clock. If they are found to be identical, bit D29 of Control register 2 is set to "1". To receive IRIG B external clock, set bit D20 to “1”. After capturing IRIG B frame, and according to the state of bit D21, time data will be stored in registers at addresses Base+ 0FDCH Base + 0FE0H, Base + 0FE4H and Base + 0FE8H. If D21 is “0", the clock’s time will be updated at each acquisition tick. Otherwise, it will be updated when reading any of the 4 registers. To reset the clock, simply perform a dummy writing at Base address + 0FECH. At power-up, the CPCI 1228 board is automatically set to the external clock, if present. Otherwise, the internal clock will start from “0” hour, and the countdown will be incremented. Registers at addresses Base + 0FE0H and Base 0FE4H can be updated by software, in BCD format, if the bit D28 of control register 2 is at “1”. (internal clock). A writing in one of the two registers resets milliseconds and microseconds. When an analog channel uses a programmable digital filter and the time-stamp must be saved, the first recorded time will correspond to the time-stamping for the 65th conversion (see chapter “Digital filters”).


57

All current-time registers are read-only registers. Data are in BCD form (Binary Coded Decimal).

The time-stamp for the first acquisition is also recorded in three different registers, at addresses Base + 0FF0H, Base + 0FF4H and Base + 0FF8H, respectively. Launching a new sequence will restart the recording of the time-stamp for the first acquisition, etc. It is also possible, as for current-time registers, to reset the first-acquisition time-stamp registers, by performing a dummy writing at address Base + 0FFCH.

DAY HOUR

MINUTES SECONDS

Millisecondes Microseconds

Base + 0FF0H

Base + 0FF4H

Base + 0FF8H

D31

D31

D31

D16

D16

D16

D15

D15

D15

D0

D0

D0

DAY HOUR

MINUTES SECONDS

Microseconds

Base + 0FE0H Max value



D31

D31

D31

D16

D16

D16

D15

D15

D15

D0

D0

D0

0 3 6 5 0 0 2 3

0 0 5 9 0 0 5 9

0 9 9 9 0 9 9 9

Milliseconds


58

!

The countdown register is a read-and-write register. Indeed, it can be used to initialize a countdown. In external clock mode, the value of countdown register is deserialized from IRIG B composite frame, then saved at base address +0FDC (H), if the bit D31 of control register 1 is at “0”. If this bit is at “1”, countdown is independent of composite IRIG B external clock. In this case, countdown register can be initialized even in external clock.

D31 D24 D23 D16 D15 D8 D7 D0

H0URS MINUTES SECONDS Base +0FDCH

2 3 5 9 5 9 Max value

Sign bit

Not used

Stop bit

At power-up, countdown is initialized at time 0 with stop bit at “1”. Bit D24: Sign bit D24 = 0 Incrementation (counter mode) D24 = 1 Decrementation (countdown mode) Bit D31: Stop bit D31 = 1 Stop D31 = 0 Counting / countdown in progress It is possible to load the time (either the counter time or the countdown time) but only if the composite IRIG B external clock is missing or if the bit D31 of control register 1 is at “1”. It exists a time offset of one second between the composite IRIG B external clock and the countdown register when external clock is used.


59

Chapter G CPCI 1228 Board Initialization At power-up , the board is configured as follows:

1. no acquisition, 2. board configured in slave mode “Flip / Flop”, 3. first measurements into RAM1, 4. internal clock and “0” hour

To initialize the CPCI 1228 board, you must:

1. select the operating mode (SLAVE or MASTER mode) 2. program PCI registers according to the mode selected 3. enter sampling frequency value 4. fill-up the pattern table 5. initialize the programmable digital filters and the gains for each

desired channel 6. program the number of patterns (NM) according to the

measurement memory 7. start acquisition

Any change of operating mode requires that you reset the CPCI 1228 board (bit 24 of MCSR register).

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60

>>> Example 1 (“Flip/Flop” slave mode):

8-channel pattern and one time-stamp using milliseconds and microseconds, frequency of 200 kHz, 450 patterns, software start, external clock (IRIG B). The pattern RAM will also contain the base address: 0 00h 1 01h 2 02h 3 03h 4 04h 5 05h 6 06h 7 07h ms 18h µs 99h Last channel in the pattern The registers are configured as follows: 1- Timer = 27h 200-kHz clock 2- Control 1 = 1C2h 450 patterns 3- Control 2 = 10000h IRIG B connected, SOFT start 4- Pattern table loaded 5- START = 0h Acquisition start The acquisition STATUS bit (bit D20 in Control register 1) remains set to “1” as long you do not stop the acquisition. The RAM STATUS bit (bit D21 in Control register 1) is set from “0” to “1, and vice versa, each time the pattern counter reaches 450. The measurement RAMs are read upon each change of the D21 bit.

>>> Example 2 (“One Shot” slave mode): Same procedure as above, you change the value of Control register 1 by 201C2h. Setting back the acquisition STATUS bit to “0” terminates the acquisition sequence. If, during the acquisition, bit D21 is set to “0”, you should read data from RAM 1 at base address + 0h. Otherwise, the data will be found in RAM 2 at base address + 20000h.


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Chapter H Implementation

The user will beforehand read the on-line available for consultation document on our Internet site www.adas.fr

Click on the icon:

GENERAL INSTRUCTIONS FOR IMPLEMENTING ADAS PRODUCTS

INSTRUCTIONS GENERALES DE MISE EN OEUVRE DES PRODUITS ADAS

The CPCI 1228 can be plugged into a rack with PCI slots. Make sure to switch off the rack before plugging the board or removing the board into/from the rack. The CPCI 1228 comprises CMOS parts. All precautions must be used against electrostatic discharges.

H.1. LEDs The CPCI 1228 board has 3 LEDs: LED A “MASTER” mode in progress LED B Access via PCI bus LED C Acquisition in progress

H.2. Connection The board has 1 connector µD 68 points female.


62

PIN ASSIGNMENT Connector µD 68S

PIN SIGNAL PIN SIGNAL 1 35 0V_MES 2 VOIE 0- 36 VOIE 0+ 3 VOIE 1- 37 VOIE 1+ 4 VOIE 2- 38 VOIE 2+ 5 VOIE 3- 39 VOIE 3+ 6 VOIE 4- 40 VOIE 4+ 7 VOIE 5- 41 VOIE 5+ 8 VOIE 6- 42 VOIE 6+ 9 VOIE 7- 43 VOIE 7+ 10 VOIE 8- 44 VOIE 8+ 11 VOIE 9- 45 VOIE 9+ 12 VOIE 10- 46 VOIE 10+ 13 VOIE 11- 47 VOIE 11+ 14 VOIE 12- 48 VOIE 12+ 15 VOIE 13- 49 VOIE 13+ 16 VOIE 14- 50 VOIE 14+ 17 VOIE 15- 51 VOIE 15+ 18 VD0 52 VD16 19 VD1 53 VD17 20 VD2 54 VD18 21 VD3 55 VD19 22 VD4 56 VD20 23 VD5 57 VD21 24 VD6 58 VD22 25 VD7 59 VD23 26 VD8 60 VD24 27 VD9 61 VD25 28 VD10 62 VD26 29 VD11 63 VD27 30 VD12 64 VD28 31 VD13 65 VD29 32 VD14 66 VD30 33 VD15 67 VD31 34 0V_MES 68 5V protégé par fusible


63

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F 22 NC PXI_RSVA22 PXI_RSVB22 PXI_RSVC22 PXI_RSVD22 PXI_RSVE22 GND 21 NC PXI_LBR0 GND PXI_LBR1 PXI_LBR2 PXI_LBR3 GND 20 NC PXI_LBR4 PXI_LBR5 PXI_LBL0 GND PXI_LBL1 GND 19 NC PXI_LBL2 GND PXI_LBL3 PXI_LBL4 PXI_LBL5 GND 18 NC PXI_TRIG3 PXI_TRIG4 PXI_TRIG5 GND PXI_TRIG6 GND 17 NC PXI_TRIG2 GND PRST# PXI_STAR PXI_CLK10 GND 16 NC PXI_TRIG1 PXI_TRIG0 DEG# GND PXI_TRIG7 GND 15 NC PXI_BRSVA15 GND FAL# PXI_LBL6 PXI_LBR6 GND 14 NC AD[35] AD[34] AD[33] GND AD[32] GND 13 NC AD[38] GND AD[37] AD[36] GND 12 NC AD[42] AD[41] AD[40] GND AD[39] GND 11 NC AD[45] GND AD[44] AD[43] GND 10 NC AD[49] AD[48] AD[47] GND AD[46] GND 9 NC AD[52] GND AD[51] AD[50] GND 8 NC AD[56] AD[55] AD[54] GND AD[53] GND 7 NC AD[59] GND AD[58] AD[57] GND 6 NC AD[63] AD[62] AD[61] GND AD[60] GND 5 NC C/BE[5]#] GND C/BE[4]# PAR64] GND 4 NC PXI_BBRSVB

4 C/BE[7]# GND C/BE[6]# GND

3 NC PXI_LBR7 GND PXI_LBR8 PXI_LBR9 PXI_LBR10 GND 2 NC PXI_LBR11 PXI_LBR12 SYSEN# PXI_LBL7 PXI_LBL8 GND 1 NC PXI_LBL9 GND PXI_LBL10 PXI_LBL11 PXI_LBL12 GND

CPCI J2 PIN ASSIGNMENT Female connector

Used pins in bold


64

Chapitre I Interface Terminal Blocks

The CPCI 1228 board can be interfaced with various terminal blocks according to the chosen outputs/inputs. Hereinafter, you can see differents layouts possibilities.


65

Appendix

CONFIGURATION LAYOUT

EQUIPMENT LAYOUT PCI CONFIGURATION REGISTERS

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66

Configuration Abbreviation Register NameAddress Offset

00h–01h VID Vendor Identification02h–03h DID Device Identification04h–05h PCICMD PCI Command Register06h–07h PCISTS PCI Status Register08h RID Revision Identification Register09h–0Bh CLCD Class Code Register0Ch CALN Cache Line Size Register0Dh LAT Master Latency Timer0Eh HDR Header Type0Fh BIST Built-in Self-test10h–27h BADR0-BADR5 Base Address Registers (0-5)28h–2Fh — Reserved30h EXROM Expansion ROM Base Address34h–3Bh — Reserved3Ch INTLN Interrupt Line3Dh INTPIN Interrupt Pin3Eh MINGNT Minimum Grant3Fh MAXLAT Maximum Latency40h–FFh — Not used

PCI CONFIGURATION REGISTERSEach PCI bus device contains a unique 256-byte region called its configuration header space. Portions of thisconfiguration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.This section describes each of the configuration space fields—its address, default values, initialization options,and bit definitions—and also provides an explanation of its intended usage.

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VENDOR IDENTIFICATION REGISTER (VID)Register Name: Vendor IdentificationAddress Offset: 00h-01hPower-up value: 10E8h (AMCC, Applied Micro

Circuits Corp.)Boot-load: External nvRAM offset

040h-41hAttribute: Read Only (RO)Size: 16 bits

The VID register contains the vendor identificationnumber. This number is assigned by the PCI SpecialInterest Group and is intended to uniquely identifyany PCI device. Write operations from the PCI inter-face have no effect on this register. After reset isremoved, this field can be boot-loaded from the ex-ternal non-volatile device (if present and valid) so thatother legitimate PCI SIG members can substitute theirvendor identification number for this field.

Bit Description

15 010E8h

Vendor Identification Register (RO)

15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.

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68

PCI CONFIGURATION REGISTERS

DEVICE IDENTIFICATION REGISTER (DID) Register Name: Device Identification Address Offset: 02h-03h Power-up value: 4750h (ASCII hex for ‘GP’,

General Purpose) Boot-load: External nvRAM offset

042h-43hAttribute: Read OnlySize: 16 bits

15 0

Device Identification Register (RO)

82F9

Bit Description

15:0 Device Identification Number: This is a 16-bit value initially assigned by AMCC to ADAS applications for PCI 102 card.

The DID register contains the vendor-assigned deviseidentification number. This number is generated by AMCCin compliance with the conditions of the PCI specification.Write operations from the PCI interface have no effect onthis register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present andvalid) so that other legitimate PCI SIG members cansubstitute their own device identification number for thisfield.

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PCI COMMAND REGISTERRegister Name: PCI CommandAddress Offset: 04h-05hPower-up value: 0000hBoot-load: not usedAttribute: Read/Write (R/W on 6 bits,

Only for all others)Size: 16 bits

This 16-bit register contains the PCI Command. Thefunction of this register is defined by the PCI specifi-cation and its implementation is required of all PCIdevices. Only six of the ten fields are used by thisdevice; those which are not used are hardwired to 0.The definitions for all fields are provided here forcompleteness.

15 0

Reserved = 00's

Fast Back-to-BackSERREWait Cycle EnableParity Error EnablePalette SnoopMemory Write and InvalidateSpecial Cycle EnableBus Master EnableMemory AccessI/O Access Enable

X 00 X 0 0 0 XXX

123456789

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15:10 Reserved. Equals all 0’s.

9 Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.This bit is cleared to a 0 upon RESET#.

8 System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drainoutput pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normallysignifies a parity error on the address/control bus.

7 Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5933controller never uses stepping, it is hardwired to 0.

6 Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. Whena parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testingdisabled) upon the assertion of RESET#.

5 Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. Thisfeature is used solely for PCI-based VGA devices.

4 Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the MemoryWrite and Invalidate PCI bus command when set to 1. When set to 0, masters must use the MemoryWrite command instead. The S5933 controller does not support this command when operated as amaster and therefore it is hardwired to 0.

3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when thisbit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit ishardwired to 0.

2 Bus Master Enable. This bit, when set to a one, allows the S5933 controller to function as a bus master.This bit is initialized to 0 upon the assertion of signal pin RESET#.

1 Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target formemory regions that may be defined in one of the five base address registers. This bit is initializedto 0 upon the assertion of signal pin RESET#.

0 I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycleswhich are to regions defined by any one of the five base address registers. This bit is initialized to 0upon the assertion of signal pin RESET#.

Bit Description

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PCI STATUS REGISTER (PCISTS)

Register Name: PCI Status

Address Offset: 06h-07h

Power-up value: 0080hBoot-load: not usedAttribute: Read Only (RO), Read/Write

Clear (R/WC)Size: 16 bits

7 0

X00XXX

6

XX

Reserved (RO)

Signaled Target Abort (R/WC)Received Target Abort (R/WC)Received Master Abort (R/WC)Signaled System Error (R/WC)Detected Parity Error (R/WC)

0

15 14 13 12 11 10 9 8

Reserved (RO) = 00's

Fast Back-to-Back (RO)Data Parity Reported (R/WC)

DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved

This 16-bit register contains the PCI status informa-tion. The function of this register is defined by thePCI specification and its implementation is requiredof all PCI devices. Only some of the bits are used bythis device; those which are not used are hardwiredto 0. Most status bits within this register are desig-nated as “write clear,” meaning that in order to cleara given bit, the bit must be written as a 1. All bitswritten with a 0 are left unchanged. These bits areidentified in Figure 4 as (R/WC). Those which areRead Only are shown as (RO) in Figure 4.

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Bit Description

15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independentlyfrom the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.

14 Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can bereset by writing a 1 to this location.

13 Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset bywriting a 1 to this location.

12 Received Target Abort. This bit is set whenever this device has one of its own initiated cyclesterminated by the currently addressed target. This bit can be reset by writing a 1 to this location.

11 Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.This bit can be reset by writing a 1 to this location.

10:9 Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from thisdevice when accessed as a target.

8 Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involvingthe S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must beset in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this locationor by the assertion of the signal RESET#.

7 Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target.

6:0 Reserved. Equal all 0’s.

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REVISION IDENTIFICATION REGISTER (RID)Register Name: Revision IdentificationAddress Offset: 08hPower-up value: 00hBoot-load: External nvRAM/EPROM offset

048hAttribute: Read OnlySize: 8 bits

The RID register contains the revision identificationnumber. This field is initially cleared. Write operationsfrom the PCI interface have no effect on this register.After reset is removed, this field can be boot-loadedfrom the external non-volatile device (if present andvalid) so that another value may be used.

Bit Description

7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.

7 000h

Revision Identification Number (RO)

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CLASS CODE REGISTER (CLCD)Register Name: Class CodeAddress Offset: 09h-0BhPower-up value: FF0000hBoot-load: External nvRAM offset

049h-4BhAttribute: Read OnlySize: 24 bits

This 24-bit, read-only register is divided into threeone-byte fields: the base class resides at location0Bh, the sub-class at 0Ah, and the programming in-terface at 09h. The default setting for the base classis all ones (FFh), which indicates that the devicedoes not fit into the thirteen base classes defined inthe PCI Local Bus Specification. It is possible, how-ever, through use of the external non-volatilememory, to implement one of the defined class codesdescribed in Table 7 below.

For devices that fall within the seven defined classcodes, sub-classes are also assigned. Tables 8through 20 describe each of the sub-class codes forbase codes 00h through 0Ch, respectively.

7 0Sub-Class

7070Base Class Prog I/F

(Bit)(Offset)@09h@0Ah@0Bh

Base-Class Description

00h Early, pre-2.0 PCI specification devices

01h Mass storage controller

02h Network controller

03h Display controller

04h Multimedia device

05h Memory controller

06h Bridge device

07h Simple communication controller

08h Base system peripherals

09h Input devices

0Ah Docking stations

0Bh Processors

0Ch Serial bus controllers

0D-FEh Reserved

FFh Device does not fit defined class codes (default)

Sub-Class Prog I/F Description

00h 00h All devices other than VGA

01h 00h VGA-compatible device

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75


00h 00h RAM memory controller

01h 00h Flash memory controller

80h 00h Other memory controller


00h 00h SCSI controller

01h xxh IDE controller

02h 00h Floppy disk controller

03h 00h IPI controller

04h 00h RAID controller

80h 00h Other mass storage controller


00h 00h Ethernet controller

01h 00h Token ring controller

02h 00h FDDI controller

03h 00h ATM controller

80h 00h Other network controller


00h 00h VGA-compatible controller

00h 01h 8514 compatible controller

01h 00h XGA controller

80h 00h Other display controller


00h 00h Video device

01h 00h Audio device

80h 00h Other multimedia device

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76


00h 00h Host/PCI bridge

01h 00h PCI/ISA bridge

02h 00h PCI/EISA bridge

03h 00h PCI/Micro Channel bridge

04h 00h PCI/PCI bridge

05h 00h PCI/PCMCIA bridge

06h 00h NuBus bridge

07h 00h CardBus bridge

80h 00h Other bridge type


00h 00h Generic XT compatible serial controller

01h 16450 compatible serial controller

02h 16550 compatible serial controller

01h 00h Parallel port

01h Bidirectional parallel port

02h ECP 1.X compliant parallel port

80h 00h Other communications device


00h 00h Generic 8259 PIC

01h ISA PIC

02h EISA PIC

01h 00h Generic 8237 DMA controller

01h ISA DMA controller

02h EISA DMA controller

02h 00h Generic 8254 system timer

01h ISA system timer

02h EISA system timers (2 timers)

03h 00h Generic RTC controller

01h ISA RTC controller

80h 00h Other system peripheral

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00h 00h Keyboard controller

01h 00h Digitizer (Pen)

02h 00h Mouse controller

80h 00h Other input controller


00h 00h Generic docking station

80h 00h Other type of docking station


00h 00h Intel386™

01h 00h Intel486™

02h 00h Pentium™

10h 00h Alpha™

40h 00h Co-processor


00 00h FireWire™ (IEEE 1394)

01h 00h ACCESS.bus

02h 00h SSA

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CACHE LINE SIZE REGISTER (CALN)Register Name: Cache Line SizeAddress Offset: 0ChPower-up value: 00h, hardwiredBoot-load: not usedAttribute: Read OnlySize: 8 bits

This register is hardwired to 0. The cache line con-figuration register is used by the system to define thecache line size in doubleword (64-bit) increments.This controller does not use the “Memory Write andInvalidate” PCI bus cycle commands when operatingin the bus master mode, and therefore does not inter-nally require this register. When operating in the tar-get mode, this controller does not have theconnections necessary to “snoop” the PCI bus andaccordingly cannot employ this register in the detec-tion of burst transfers that cross a line boundary.

7 000h

Cache Line Size (RO)

LATENCY TIMER REGISTER (LAT)Register Name: Latency TimerAddress Offset: 0DhPower-up value: 00hBoot-load: External nvRAM offset

04DhAttribute: Read/Write, bits 7:3;

Read Only bits 2:0Size: 8 bits

The latency timer register has meaning only whenthis controller is used as a bus master and pertains tothe number of PCI bus clocks that this master will beguaranteed. The nonzero value for this register isinternally decremented after this device has beengranted the bus and has begun to assert FRAME#.Prior to this latency timer count reaching zero, thisdevice can ignore the removal of the bus grant andmay continue the use of the bus for data transfers.

7 0

Latency Timer value (R/W)# of clocks x 8

0

1

0

2

0

3

X

4

X

5

X

6

XX

Bit

Value

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HEADER TYPE REGISTER (HDR)Register Name: Header TypeAddress Offset: 0EhPower-up value: 00hBoot-load: External nvRAM offset

04EhAttribute: Read OnlySize: 8 bits

This register consists of two fields: Bits 6:0 define theformat for bytes 10h through 3Fh of the device con-figuration header, and bit 7 establishes whether thisdevice represents a single function (bit 7 = 0) or amultifunction (bit 7 = 1) PCI bus agent. The S5933 isa single function PCI device.

7 0

Single/Multi-function device (Read Only)0 = single function1 = multi-function

123456

X

Bit

Value00h

Format field (Read Only)

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BUILT-IN SELF-TEST REGISTER (BIST)Register Name: Built-in Self-TestAddress Offset: 0FhPower-up value: 00hBoot-load: External nvRAM/EPROM

offset 04FhAttribute: D7, D5-0 Read Only, D6 as

PCI bus write onlySize: 8 bits

The Built-In Self-Test (BIST) register permits theimplementation of custom, user-specific diagnostics.This register has four fields as depicted in Figure 10.Bit 7, when set signifies that this device supports abuilt-in self test. When bit 7 is set, writing a 1 to bit 6will commence the self test. In actuality, writing a 1 tobit 6 produces an interrupt to the Add-On interface.Bit 6 will remain set until cleared by a write operationto this register from the Add-On bus interface. Whenbit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value forthe completion code (bits 3:0).

Bit Description

7 BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one isreturned. A zero should be returned if this self test feature is not desired. This field is read onlyfrom the PCI interface.

6 Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only bewritten when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Otherthan through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On businterface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within2 seconds after being set, or the device will be failed.

5:4 Reserved. These bits are reserved. This field will always return zeros.

3:0 Completion Code. This field provides a method for detailing a device-specific error. It is consideredvalid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion codeindicates successful completion.

7 0

X

1

X

2

X

3

X

4

0

5

0

6

0X

Bit

Value

User definedCompletion Code (RO)

Reserved (RO)

Start BIST (WO)

BIST Capable (RO)

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BASE ADDRESS REGISTERS (BADR)Register Name: Base AddressAddress Offset: 10h, 14h, 18h, 1Ch, 20h, 24hPower-up value: FFFFFFC1h for offset 10h;

00000000h for all othersBoot-load: External nvRAM offset

050h, 54h, 58h, 5Ch, 60h(BADR0-4)

Attribute: high bits Read/Write; low bitsRead Only

Size: 32 bits

The base address registers provide a mechanism forassigning memory or I/O space for the Add-On func-tion. The actual location(s) the Add-On function is torespond to is determined by first interrogating theseregisters to ascertain the size or space desired, andthen writing the high-order field of each register toplace it physically in the system’s address space. Bitzero of each field is used to select whether the spacerequired is to be decoded as memory (bit 0 = 0) or I/O(bit 0 = 1). Since this PCI controller has 16 DWORDsof internal operating registers, the Base AddressRegister at offset 10h is assigned to them. The re-maining five base address registers can only be usedby boot-loading them from the external nvRAM inter-face. BADR5 register is not implemented and will re-turn all 0’s.

Determining Base Address SizeThe address space defined by a given base addressregister is determined by writing all 1s to a givenbase address register from the PCI bus and thenreading that register back. The number of 0s returnedstarting from D4 for memory space and D2 for I/Ospace toward the high-order bits reveals the amountof address space desired. Tables 23 and 24 list thepossible returned values and their corresponding sizefor both memory and I/O, respectively. Included inthe table are the nvRAM/EPROM boot values whichcorrespond to a given assigned size. A register re-turning all zeros is disabled.

Assigning the Base Address

After a base address has been sized as described inthe preceding paragraph, the region associated withthat base address register (the high order one bits)can physically locate it in memory (or I/O) space. Forexample, the first base address register returnsFFFFFFC1h indicating an I/O space (D0=1) and isthen written with the value 00000300h. This meansthat the controller’s internal registers can be selectedfor I/O addresses between 00000300h through0000033Fh, in this example. The base address valuemust be on a natural binary boundary for the requiredsize (example 300h, 340h, 380h etc.; 338h would notbe allowable).

31 0

X

1

0

2 Bit

Value

I/O Space Indicator (RO)Reserved (RO)

Programmable (R/W)

31 0

X

1

X

2

X

3

X

4 Bit

Value

Memory Space Indicator (RO)Type (RO) 00-locate anywhere (32) 01-below 1 MB 10-locate anywhere (64) 11-reserved

Programmable (R/W)

Prefetchable (RO)

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31:4 Base Address Location. These bits are used to position the decoded region in memory space. Onlybits which return a 1 after being written as 1 are usable for this purpose. Except for Base AddressRegister 0, these bits are individually enabled by the contents sourced from the external boot memory.

3 Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachableregions can only be located within the region altered through PCI bus memory writes. This bit, whenset, also implies that all read operations will return the data associated for all bytes regardless of theByte Enables. Memory space which cannot support this behavior should leave this bit in the zerostate. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by theexternal boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is readonly from the PCI interface.

2:1 Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the spacelocation is restricted to be within the first megabyte of memory space. The table below describes theencoding:

Bits Description2 10 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space.

0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space.

1 0 Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.(Not supported by this controller.)

1 1 Reserved. (Not supported by this controller.)

1 The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The onlymeaningful option is whether it is desired to position memory space anywhere within 32-bit memoryspace or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the resetpin and later initialized by the external boot memory (if present).

0 Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space andthe remaining bits in the base address register are defined as shown in Table 22a.

Bit Description

Bit Description

31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bitswhich return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,these bits are individually enabled by the contents sourced from the external boot memory (EPROMor nvRAM).

1 Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for theentire register location, bits 31 through 0).

0 Space Indicator = 1. When one this bit identifies a base address region as an I/O space and theremaining bits in the base address register have the definition as shown in Table 11b.

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Response Size in bytes [EPROM boot value] 1

00000000h none - disabled 00000000h orBIOS missing 2,3

FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFF0h

FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFE0h

FFFFFFC0h 64 bytes (16 DWORDs) FFFFFFC0h

FFFFFF80h 128 bytes (32 DWORDs) FFFFFF80h


FFFFFE00h 512 bytes (128 DWORDs) FFFFFE00h

FFFFFC00h 1K bytes (256 DWORDs) FFFFFC00h

FFFFF800h 2K bytes (512 DWORDs) FFFFF800h

FFFFF000h 4K bytes (1K DWORDs) FFFFF000h

FFFFE000h 8K bytes (2K DWORDs) FFFFE000h

FFFFC000h 16K bytes (4K DWORDs) FFFFC000h

FFFF8000h 32K bytes (8K DWORDs) FFFF8000h


FFFE0000h 128K bytes (32K DWORDs) FFFE0000h

FFFC0000h 256K bytes (64K DWORDs) FFFC0000h

FFF80000h 512K bytes (128K DWORDs) FFF80000h

FFF00000h 1M bytes (256K DWORDs) FFF00000h

FFE00000h 2M bytes (512K DWORDs) FFE00000h

FFC00000h 4M bytes (1M DWORDs) FFC00000h

FF800000h 8M bytes (2M DWORDs) FF800000h

FF000000h 16M bytes (4M DWORDs) FF000000h

FE000000h 32M bytes (8M DWORDs) FE000000h

FC000000h 64M bytes (16M DWORDs) FC000000h

F8000000h 128M bytes (32M DWORDs) F8000000h

F0000000h 256M bytes (64M DWORDs) F0000000h

E0000000h 512M bytes (128M DWORDs) E0000000h

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.3. BADR5 register is not implemented and will return all 0’s.

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Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing 3

FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFFDh



FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFE1h

FFFFFFC1h 64 bytes (16 DWORDs) FFFFFFC1h 4



4. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external bootmemory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h orFFFFFFC2h).

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EXPANSION ROM BASE ADDRESSREGISTER (XROM)

Register Name: Expansion ROM Base AddressAddress Offset: 30hPower-up value: 00000000hBoot-load: External nvRAM offset

70hAttribute: bits 31:11, bit 0 Read/Write; bits

10:1 Read OnlySize: 32 bits

31 0

00

110 Bit

Value

Address Decode Enable (RW) 0=Disabled 1=EnabledReserved (RO)Programmable (R/W)

11

The expansion base address ROM register providesa mechanism for assigning a space within physicalmemory for an expansion ROM. Access from the PCIbus to the memory space defined by this register willcause one or more accesses to the S5933 control-lers’ external BIOS ROM (or nvRAM) interface. SincePCI bus accesses to the ROM may be 32 bits wide,repeated operations to the ROM are generated bythe S5933 and the wider data is assembled internalto the S5933 controller and then transferred to thePCI bus by the S5933.

Bit Description

31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region inmemory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Thesebits are individually enabled by the contents sourced from the external boot memory (EPROM ornvRAM). The desired size for the ROM memory is determined by writing all ones to this register andthen reading back the contents. The number of bits returned as zeros, in order from least significantto most significant bit, indicates the size of the expansion ROM. This controller limits the expansionROM area to 64K bytes. The allowable returned values after all ones are written to this register areshown in Table 26.

10:1 Reserved. All zeros.

0 Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit.When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is requiredthat the PCI command register also have the memory decode enabled for this bit to have an effect.

Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing

FFFFF801h 2K bytes (512 DWORDs) FFFFF801h

FFFFF001h 4K bytes (1K DWORDs) FFFFF001h

FFFFE001h 8K bytes (2K DWORDs) FFFFE001h

FFFFC001h 16K bytes (4K DWORDs) FFFFC001h



CPCI 1228

86

INTERRUPT LINE REGISTER (INTLN)Register Name: Interrupt LineAddress Offset: 3ChPower-up value: FFhBoot-load: External nvRAM offset

7ChAttribute: Read/WriteSize: 8 bit

This register indicates the interrupt routing for theS5933 controller. The ultimate value for this registeris system-architecture specific. For x86 based PCs,the values in this register correspond with the estab-lished interrupt numbers associated with the dual8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspondwith the IRQ numbers 0 through 15, and the valuesfrom 16 to 254 are reserved. The value of 255 (thecontroller’s default power-up value) signifies either“unknown” or “no connection” for the system inter-rupt. This register is boot-loaded from the externalboot memory, if present, and may be written by thePCI interface.

7 01

FFh

5 Bit

Value

6 4 23

INTERRUPT PIN REGISTER (INTPIN)Register Name: Interrupt PinAddress Offset: 3DhPower-up value: 01hBoot-load: External nvRAM offset

7DhAttribute: Read OnlySize: 8 bits

7 015 Bit

Value

6 4 23

0 0000 XXX

Reserved (all zeroes-RO)

Pin Number 0 0 0 None0 0 1 INTA#0 1 0 INTB#0 1 1 INTC#1 0 0 INTD# 1 0 1 Reserved1 1 X Reserved

This register identifies which PCI interrupt, if any, isconnected to the controller’s PCI interrupt pins. Theallowable values are 0 (no interrupts), 1 (INTA#), 2(INTB#), 3 (INTC#), and 4 (INTD#). The defaultpower-up value assumes INTA#.

CPCI 1228

87

MINIMUM GRANT REGISTER (MINGNT)Register Name: Minimum Grant

Address Offset: 3EhPower-up value: 00hBoot-load: External nvRAM offset

7EhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how long a burst period the device needs.A value of zero indicates that the bus master has nostringent requirement. The units defined by the leastsignificant bit are in 250-ns increments. This registeris treated as “information only” and has no furtherimplementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

MAXIMUM LATENCY REGISTER (MAXLAT)

Register Name: Maximum LatencyAddress Offset: 3FhPower-up value: 00hBoot-load: External nvRAM offset

7FhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how often this device needs PCI bus ac-cess. A value of zero indicates that the bus masterhas no stringent requirement. The units defined bythe least significant bit are in 250-ns increments. Thisregister is treated as “information only” and has nofurther implementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

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88

PCI BUS OPERATION REGISTERS

Address Offset Abbreviation Register Name

00h OMB1 Outgoing Mailbox Register 1



0Ch OMB4 Outgoing Mailbox Register 4

10h IMB1 Incoming Mailbox Register 1



1Ch IMB4 Incoming Mailbox Register 4

20h FIFO FIFO Register port (bidirectional)

24h MWAR Master Write Address Register

28h MWTC Master Write Transfer Count Register

2Ch MRAR Master Read Address Register

30h MRTC Master Read Transfer Count Register

34h MBEF Mailbox Empty/Full Status

38h INTCSR Interrupt Control/Status Register

3Ch MCSR Bus Master Control/Status Register

PCI BUS OPERATION REGISTERSThe PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can beeither exchanged through the mailboxes, transferred through the FIFO in blocks under program control, ortransferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.

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OUTGOING MAILBOX REGISTERS (OMB)Register Names: Outgoing Mailboxes 1-4

PCI Address Offset: 00h, 04h, 08h, 0Ch

Power-up value: XXXXXXXXh

Attribute: Read/Write

Size: 32 bits

These four DWORD registers provide a method forsending command or parameter data to the Add-Onsystem. PCI bus operations to these registers maybe in any width (byte, word, or DWORD). Writing tothese registers can be a source for Add-On bus inter-rupts (if desired) by enabling their interrupt genera-tion through the use of the Add-On’s interrupt control/status register.

INCOMING MAILBOX REGISTERS (IMB)Register Names: Incoming Mailboxes 1-4

PCI Address Offset: 10h, 14h, 18h, 1Ch


Attribute: Read Only

Size: 32 bits

These four DWORD registers provide a method forreceiving user defined data from the Add-On system.PCI bus read operations to these registers may be inany width (byte, word, or DWORD). Only read opera-tions are supported. Reading from these registers canoptionally cause an Add-On bus interrupt (if desired)by enabling their interrupt generation through the useof the Add-On’s interrupt control/status register.

Mailbox 4, byte 3 only exists as device pins on theS5933 devices when used with a serial nonvolatilememory.

This location provides access to the bidirectionalFIFO. Separate registers are used when readingfrom or writing to the FIFO. Accordingly, it is not pos-sible to read what was written to this location. TheFIFO registers are implicitly involved in all bus masteroperations and, as such, should not be accessedduring active bus master transfers. When operatingupon the FIFOs with software program transfers in-volving word or byte operations, the sequenceof the FIFO should be established as described un-der FIFO Endian Conversion Management in order topreserve the internal FIFO data ordering and flagmanagement. The FIFO’s fullness may be observedby reading the master control- status registerorMCSR register.

FIFO REGISTER PORT (FIFO)

Register Name: FIFO Port

PCI Address Offset: 20h


Attribute: Read/Write

Size: 32 bits

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PCI CONTROLLED BUS MASTER WRITEADDRESS REGISTER (MWAR)Register Name: Master Write AddressPCI Address Offset: 24hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving from the Add-On bus to the PCI busduring PCI bus memory write operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MWTC, and must begin on a DWORD boundary.This DWORD boundary starting constraint is placedupon this controller’s PCI bus master transfers sothat byte lane alignment can be maintained betweenthe S5933 controller’s internal FIFO data path, theAdd-On interface, and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Write Address Register is continually up-dated during the transfer process and will always bepointing to the next unwritten location. Reading ofthis register during a transfer process (done when theS5933 controller is functioning as a target, i.e. not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master write transfers, the two leastsignificant bits presented on the PCI bus pinsAD[31:0] will always be zero. This identifies to thetarget memory that the burst address sequence willbe in a linear order rather than in an Intel 486 orPentium™ cache line fill sequence. Also, the PCI busaddress bit A1 will always be zero when this control-ler is the bus master. This signifies to the target thatthe S5933 controller is burst capable and that thetarget should not arbitrarily disconnect after the firstdata phase of this operation.

Under certain circumstances, MWAR can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Write Transfer Address (R/W)

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91

PCI CONTROLLED BUS MASTER WRITETRANSFER COUNT REGISTER (MWTC)Register Name: Master Write Transfer CountPCI Address Offset: 28hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master write transfer count register is used toconvey to the S5933 controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIwrite operation until the transfer count reaches zero.

Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MWTC can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = O's (RO)

26

00

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PCI CONTROLLED BUS MASTER READADDRESS REGISTER (MRAR)Register Name: Master Read AddressPCI Address Offset: 2ChPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving to the Add-On bus from the PCI busduring PCI bus memory read operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MRTC (Section 5.7) and must begin on a DWORDboundary. This DWORD boundary starting constraintis placed upon this controller’s PCI bus master trans-fers so that byte lane alignment can be maintainedbetween the S5933 controller’s internal FIFO datapath, the Add-On interface and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Read Address Register is continually up-dated during the transfer process and will always bepointing to the next unread location. Reading of thisregister during a transfer process (done when theS5933 controller is functioning as a target—i.e., not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master read transfers, the two leastsignificant bits presented on the PCI bus AD[31:0]will always be zero. This identifies to the targetmemory that the burst address sequence will be in alinear order rather than in an Intel 486 or Pentium™cache line fill sequence. Also, the PCI bus addressbit A1 will always be zero when this controller is thebus master. This signifies to the target that the con-troller is burst capable and that the target should notarbitrarily disconnect after the first data phase of thisoperation.

Under certain circumstances, MRAR can be ac-cessed from the Add-On bus instead of the PCI bus.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Read Transfer Address (R/W)

CPCI 1228

93

PCI CONTROLLED BUS MASTER READTRANSFER COUNT REGISTER (MRTC)

Register Name: Master Read Transfer CountPCI Address Offset: 30hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master read transfer count register is used toconvey to the PCI controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIread operation until the transfer count reaches zero.Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MRTC can be ac-cessed from the Add-On bus instead of the PCI bus.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = 0's (RO)

26

00

CPCI 1228

94

MAILBOX EMPTY FULL/STATUSREGISTER (MBEF)

Register Name: Mailbox Empty/Full Status

PCI Address Offset: 34h

Power-up value: 00000000h

Attribute: Read Only

Size: 32 bits

This register provides empty/full visibility of each bytewithin the mailboxes. The empty/full status for theOutgoing mailboxes is displayed on the low-order 16bits and the empty/full status for the Incoming mail-boxes is presented on the high-order 16 bits. A valueof 1 signifies that a given mailbox has been written byone bus interface but has not yet been read by thecorresponding destination interface. A PCI bus in-coming mailbox is defined as one in which data trav-els from the Add-On bus into the PCI bus, and anoutgoing mailbox is defined as one where data trav-els out from the PCI bus to the Add-On interface.

31 015 Bit

Value

Outgoing MailboxStatus (RO)Incoming Mailbox Status (RO)

16

CPCI 1228

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Bit Description

31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been writtenby the Add-On interface but have not yet been read by the PCI bus. Each bit location corre-sponds to a specific byte within one of the four incoming mailboxes. A value of one for each bitsignifies that the specified mailbox byte is full, and a value of zero signifies empty. The mappingof these status bits to bytes within each mailbox is as follows:

Bit 31 = Incoming mailbox 4 byte 3Bit 30 = Incoming mailbox 4 byte 2Bit 29 = Incoming mailbox 4 byte 1Bit 28 = Incoming mailbox 4 byte 0Bit 27 = Incoming mailbox 3 byte 3Bit 26 = Incoming mailbox 3 byte 2Bit 25 = Incoming mailbox 3 byte 1Bit 24 = Incoming mailbox 3 byte 0Bit 23 = Incoming mailbox 2 byte 3Bit 22 = Incoming mailbox 2 byte 2Bit 21 = Incoming mailbox 2 byte 1Bit 20 = Incoming mailbox 2 byte 0Bit 19 = Incoming mailbox 1 byte 3Bit 18 = Incoming mailbox 1 byte 2Bit 17 = Incoming mailbox 1 byte 1Bit 16 = Incoming mailbox 1 byte 0

15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been writtenby the PCI bus interface but have not yet been read by the Add-On bus. Each bit location correspondsto a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies thatthe specified mailbox byte is full, and a value of zero signifies empty. The mapping of these statusbits to bytes within each mailbox is as follows:

Bit 15 = Outgoing mailbox 4 byte 3Bit 14 = Outgoing mailbox 4 byte 2Bit 13 = Outgoing mailbox 4 byte 1Bit 12 = Outgoing mailbox 4 byte 0Bit 11 = Outgoing mailbox 3 byte 3Bit 10 = Outgoing mailbox 3 byte 2Bit 09 = Outgoing mailbox 3 byte 1Bit 08 = Outgoing mailbox 3 byte 0Bit 07 = Outgoing mailbox 2 byte 3Bit 06 = Outgoing mailbox 2 byte 2Bit 05 = Outgoing mailbox 2 byte 1Bit 04 = Outgoing Mailbox 2 byte 0Bit 03 = Outgoing Mailbox 1 byte 3Bit 02 = Outgoing Mailbox 1 byte 2Bit 01 = Outgoing Mailbox 1 byte 1Bit 00 = Outgoing Mailbox 1 byte 0

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96

INTERRUPT CONTROL/STATUSREGISTER (INTCSR)

Register Name: Interrupt Control and StatusPCI Address Offset: 38hPower-up value: 00000000hAttribute: Read/Write (R/W),

Read/Write_One_Clear (R/WC)Size: 32 bits

This register provides the method for choosing whichconditions are to produce an interrupt on the PCI businterface, a method for viewing the cause of the inter-rupt, and a method for acknowledging (removing) theinterrupt’s assertion.

Interrupt sources:

• Write Transfer Terminal Count = zero

• Read Transfer Terminal Count = zero

• One of the Outgoing mailboxes (1,2,3 or 4)becomes empty

• One of the Incoming mailboxes (1,2,3 or 4)becomes full.

• Target Abort

• Master Abort

31 015 14 12 8 4 Bit

Value16212324

FIFO and Endian Control 0

Read TransferComplete (R/WC)

Write Transfer Complete (R/WC)

Incoming Mailbox Interrupt (R/WC)

Outgoing Mailbox Interrupt (R/WC)

Interrupt Asserted (RO)

Target Abort (R/WC)

Master Abort (R/WC)

0 0 0 0

D4-D0 Outgoing Mailbox (Goes empty)

D4=Enable Interrrupt

D3-D2=Mailbox #

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D1-D0=Byte #

0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

D12-D8 Incoming Mailbox (R/W)(Becomes full)

D12=Enable Interrupt

D11-D10=Mailbox

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D9-D8=Byte #0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

Interrupt on WriteTransfer Complete

Interrupt on ReadTransfer Complete

Interrupt Source (R/W)Enable & Selection

Actual Interrupt Interrupt Selection

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0011

0 NO CONVERSION (DEFAULT)1 16 BIT ENDIAN CONV.0 32 BIT ENDIAN CONV.1 64 BIT ENDIAN CONV

FIFO ADVANCE CONTROLPCI INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

FIFO ADVANCE CONTROLADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7 (NOTE1)

INBOUND FIFO ADD-ON PCI DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7

NOTE 1: D24 and D25 MUST BE ALSO "1"

31 30 29 28 27 26 25 24

1

CPCI 1228

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Bit Description

31:24 FIFO and Endian Control.

23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interruptconditions is present. This bit is nothing more than the ORing of the interrupt conditions describedby bits 19 through 16 of this register.

22 Reserved. Always zero.

21 Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operatesas read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a writeto this bit with the data of “zero” will not change the state of this bit.

20 Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI buscycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will causethis bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.

19 Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. Thisinterrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

18 Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. Thisinterrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

17 Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of thisregister are written by the Add-On interface. This bit operates as read or write one clear. A write tothis bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”will not change the state of this bit.

16 Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this registeris read by the Add-On interface. This bit operates as read or write one clear. A write to this bit withthe data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not changethe state of this bit.

15 Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the readtransfer count reaches zero. This bit is read/write.

14 Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the writetransfer count reaches zero. This bit is read/write.


12 Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identifiedby bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.

11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to bethe source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

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9:8 Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]bselects byte 2, and [11]b selects byte 3. This field is read/write.

7:5 Reserved, Always zero.

4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailboxregister identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.

3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be thesource for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2,[10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

1:0 Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selectsbyte 2, and [11]b selects byte 3. This field is read/write.

Bit Description

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MASTER CONTROL/STATUSREGISTER (MCSR)

Register Name: Master Control/StatusPCI Address Offset: 3ChPower-up value: 000000E6hAttribute: Read/Write, Read Only,

Write OnlySize: 32 bits

This register provides for overall control of this de-vice. It is used to enable bus mastering for both datadirections as well as providing a method to performsoftware resets.

The following PCI bus controls are available:

• Write Priority over Read

• Read Priority over Write

• Write Transfer Enable

• Write master requests on 4 or more FIFO wordsavailable (full)

• Read transfer enable

• Read master requests on 4 or more FIFOavailable (empty)

• Assert reset to Add-On

• Reset Add-On to PCI FIFO flags

• Reset PCI to Add-On FIFO flags

• Reset mailbox empty full status flags

• Write external non-volatile memory

The following PCI interface status flags are provided:

• PCI to Add-On FIFO FULL

• PCI to Add-On FIFO has four or more emptylocations

• PCI to Add-On FIFO EMPTY

• Add-On to PCI FIFO FULL

• Add-On to PCI FIFO has four or more wordsloaded

• Add-On to PCI FIFO EMPTY

• PCI to Add-On Transfer Count = Zero

• Add-On to PCI Transfer Count = Zero

31 29 27 24 23 014 12 10 8 7 6 515 Bit

Value

FIFO STATUS (RO)D5=Add-on to PCI FIFO EmptyD4=Add-on to PCI FIFO 4+ WordsD3=Add-on to PCI FIFO FullD2=PCI to Add-on FIFO EmptyD1=PCI to Add-on FIFO 4+SpacesD0=PCI to Add-on FIFO Full

D7=Add-on to PCI Transfer Countequals zero (R0)

D6=PCI to Add-on Transfer Countequals zero (R0)

160

Write Transfer Control (R/W)(PCI memory writes)

D10=Write Transfer EnableD9=FIFO Management SchemeD8=Write vs Read Priority

Reset Controls (R/WC)D27=Mailbox Flags ResetD26=Add-on to PCI FIFO Status Flags ResetD25=PCI to Add-on FIFO Status Flags ResetD24=Add-On Reset nv operation address/data

Memory Read MultipleEnable = 1Disable = 0

Read Transfer Control (R/W) (PCI memory reads)

D14=Read Transfer EnableD13=FIFO Management SchemeD12=Read vs. Write Priority

nvRAM Access Ctrl

0 0

Control Status

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Bit Description

31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatilememory. Write operations are achieved by a sequence of byte operations involving these bits and the8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address,and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready forthe access to the external memory. D31 must be written to a 1 before an access can begin, andsubsequent accesses must wait for bit D31 to become zero (ready).

D31 D30 D29 W/R

0 X X W Inactive

1 0 0 W Load low address byte

1 0 1 W Load high address byte

1 1 0 W Begin write

1 1 1 W Begin read

0 X X R Ready

1 X X R Busy

Cautionary note: The nonvolatile memory interface is also available for access by the Add-Oninterface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supportedby the S5933 device. Software must be designed to prevent the simultaneous access of nvmemory to prevent data corruption within the memory and provide for accurate data retrieval.

28 FIFO loop back mode.

27 Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY).It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Sincereading of this bit will always produce zeros, this bit is write only.

26 Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus mastermemory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFOFour Plus word flag to reset. It is not necessary to write this bit as zero because it is used internallyto produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only.

25 PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Busmaster memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to resetand the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zerobecause it is used internally to produce a reset pulse. Since reading of this bit will always producezeros, this bit is write only.

24 Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing azero to this pin is necessary to remove the assertion of reset. This register bit is read/write.

23:16 Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and29 of this register to access the external non-volatile memory. The contents written are either lowaddress, high address, or data as defined by bits 30 and 29. This register will contain the externalnon-volatile memory data when the proper read sequence for bits 31 through 29 is performed.

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Bit Description

15 Enable memory read multiple during S5933 bus mastering mode.

14 Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers totake place. Writing a zero to this location will suspend an active transfer. An active transfer is onein which the transfer count is not zero.

13 Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevacant FIFO word.

12 Read versus Write priority. This bit controls the priority of read transfers over write transfers.When set to a 1 with bit D8 as zero this indicates that read transfers always have priority overwrite transfers; when set to a one with D8 as one, this indicates that transfer priorities willalternate equally between read and writes.


10 Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to takeplace. Writing a zero to this location will suspend an active transfer. An active transfer is one inwhich the transfer count is not zero.

9 Write FIFO management scheme. When set to a one this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevalid FIFO word.

8 Write versus Read priority. This bit controls the priority of write transfers over read transfers.When set to a one with bit D12 as zero this indicates that write transfers always have priority overread transfers; when set to a one with D12 as one, this indicates that transfer priorities willalternate equally between writes and reads.

7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfercount is all zeros.

6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfercount is all zeros.

5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completelyempty.

4 Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid withinthe Add-On to PCI bus FIFO.

3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.

2 PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completelyempty.

1 PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words withinthe PCI to Add-On FIFO.

0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.

CPCI 1228 S 16 A NALOG INPUTS /32 D I/O IMULTANEOUS … · Chocs 25 g - 6 ms EUROPEAN STANDARDS CE...

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