Course Catalog 2016 - Technically Speaking · Training Provider) in North America ... DSP Design...

Course Catalog2016

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In an increasingly diverse, fast-paced, and competitive

workplace you must invest in expanding your skillset in

order to increase your value to your organization.

As the industry leader, Xilinx has defined the standard for the “All Programmable” logic marketplace.

Xilinx offers a combination of innovative FPGAs, SoCs, MPSoC hardware solutions, along with leading-

edge software and development tools. Technically Speaking is the original Xilinx ATP (Authorized

Training Provider) in North America. We’re genuinely vested in the education, training, and support of

Xilinx customers and personnel.

You absolutely must be technically competent in your role. But the truth is that your soft skills are

critical to your overall success and career development. Multiple surveys of top technology companies

reaffirm that communication skills are viewed as extremely important predictors of job success, in many

cases, even more so than years of experience or advanced educational degrees. The pace of change

in the market requires that technical professionals bring more than just subject-matter expertise to the

table. Your communication skills are where your individual contribution can become singularly unique.

At Technically Speaking, we’re passionate about giving technical professionals the tools necessary to

succeed and thrive. Our long-time commitment to the specific needs of the technology industry has

yielded unparalleled results. Our clients see amazing transformations because we understand the

particular requirements of technical professionals. We talk tech!

We provide training in countries throughout the world and utilize a team of globally relevant, locally

established experts. We will furnish you with the resources that other providers simply cannot match.

We look forward to working with you, and we’re honored to be the resource for your ongoing training

and development.

Sincerely,

L. Eric Culverson Patricia Townsend

CEO/President Chief Operations Officer

Table of Contents

PRESENTATION SKILLS WORKSHOPS

Delivering Effective Presentations (DEP) – Introductory Workshop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Delivering Effective Presentations (DEP) – Advanced Workshop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Delivering Effective Presentations (DEP) – Leadership Level Workshop. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Powerful Persuasion and Influence Techniques*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Non‐Verbal Communication: The Influence of Body Language*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Cross‐Cultural Communication*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Skillfully Managing Q&A Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Conducting Dynamic Webinar and Remote Meeting Presentations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

PowerPoint – Design Fundamentals for Technical Professionals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

One‐on‐One (1:1) Executive Coaching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Deconstructing the Technical Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

INTERPERSONAL COMMUNICATION WORKSHOPS

Powerful Persuasion and Influence Techniques*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Successful Team Building and Collaboration Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Communication Essentials for Leaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Managing Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Business Etiquette. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Non‐Verbal Communication: The Influence of Body Language*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Essentials of Conflict Management and Mediation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Cross‐Cultural Communication*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Building Winning Business Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Women in Technology Seminar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Presentation and Interpersonal Skills Workshop Price Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

*Program covers both interpersonal communication and presentation skills

FPGA COURSES

Vivado for Experienced Users. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Designing FPGAs Using the Vivado Design Suite 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30,31




Designing with Ultrascale Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38,39

EMBEDDED COURSES

Embedded Systems Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Embedded Design with Petalinux Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Embedded Systems Software Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 42,43

Embedded C/C++ SDSoC Development Environment and Methodology. . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Zynq US + MPSoC for the System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Zynq US + MPSoC Software Developer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46,47

Zynq US + MPSoC Hardware Designer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Zynq All Programmable SoC Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Zynq All Programmable SoC Accelerators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

LANGUAGE COURSES

Designing with VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Designing with Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

DSP COURSES

C‐based Design with High Level Synthesis with Vivado HLS Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

DSP Design using System Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

CONNECTIVITY COURSES

Designing an Integrated PCI express System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

How to Design a High Speed Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Designing with Multi‐Gigabit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56,57

Xilinx Technical Course Price Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

POLICIES AND REGISTRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60,61

Delivering Effective Presentations - Introductory

TCW-DPB-PRS Course Specification

Course Description Course Outline

TCW-DPB-PRS www.technically-speaking.com

Our highly-acclaimed and always in demand workshop is a comprehensive session that establishes a solid foundation of speaking and presentation skills. This program will make even the most apprehensive presenters shine. For more seasoned presenters, this workshop gives you the tools to rise to the next level and stand out from other technical presenters. Technical presentations are frequently data-driven, but they do not have to be dry. You’ll learn proven methods to pair your subject matter expertise with engaging delivery to ensure that you connect with your audience members.

Introduction to the Characteristics ofEffective Presentations

Participants Deliver Prepared Presentations* In-Depth Personalized Coaching Overview of Core Concepts

o Connecting with the Audienceo Introductory Principleso Structuring the Presentationo Using Visual Aidso Non-Verbal Communicationo Vocal Varietyo Overcoming Nervousnesso Practice Techniques

Real-time Interactive Lab Participants Deliver Enhanced

Presentations* Final Review and Feedback

*Activities may be videotaped to facilitate coaching

Course Duration – One-Day Workshop

Price - $ 997 USD

Course Part Number – TCW-DPB-SDW

Who Should Attend – This course is designed for technical professionals seeking to improve and enhance fundamental presentation skills.

Register Today

We deliver public and private courses in locationsthroughout the world. Please contact us for moreinformation, to view our schedules, or to register online.

Visit technically-speaking.com for trainings in theAmericas, Europe, Asia Pacific, Japan, or India. For othergeographical regions please contact us [email protected] for logistical specifics.

After completing this comprehensive training, you will have the necessary skills to:

• Speak with confidence and clarity• Engage your audience and keep them

interested in your topic• Use vocal variety and body language for

maximum impact• Organize your content and develop visual aids

that increase understanding and retention• Persuade and influence others to support your

program, idea, or innovation

5

Delivering Effective Presentations - Advanced

TCW-DPA-PRS Course Specification


TCW-DPA-PRS www.technically-speaking.com

This workshop builds upon the foundation of our highly-acclaimed Introductory Workshop. The Advanced section delves deeper into the anatomy of a great presentation. Developed for the already skilled presenter, this workshop explores advanced techniques that will take your existing speaking skills to the next level of influence, connection, and impact.

Introduction of Course Expectations and CoreConcepts

Participants Deliver Prepared Presentations* Comprehensive Personalized Coaching in Key

Areas Instructional Presentation of High Level Skills

o Memorable Messagingo Establishing Credibility and Authorityo Originality in Visual Aidso Crafting Clear and Specific Messages

In-Depth Examination of the Science BehindEffective Storytelling

Dynamic Application of Concept* How and When to use Humor Appropriately Interactive Implementation Lesson* Participants Deliver Enhanced Presentations* Final Review and Feedback

*Activities may be videotaped to facilitate coaching

Course Duration – One or Two-Day Workshop

Price - $ 1,197 USD (1 Day) $ 1,797 USD (2 Day)

Course Part Number – TCW-DPA-SDW (1 Day) TCW-DPA-MDW (2 Day)

Who Should Attend - This course is designed for professionals with previous presentation skills training or who are frequent presenters. Completion of our Introductory Workshop is recommended but not required.


• Structure a strong message• Grab and keep the attention of your audience• Develop analytical and emotional balance in

your presentation• Utilize humor and storytelling to elevate

audience interest and engagement• Pinpoint and adapt to different learning types

Register Today

We deliver public and private courses in locations throughout the world. Please contact us for more information, to view our schedules, or to register online.

Visit technically-speaking.com for trainings in the Americas, Europe, Asia Pacific, Japan, or India. For other geographical regions please contact us at [email protected] for logistical specifics.

6

Delivering Effective Presentations - Leadership

TCW-DPL-PRS Course Specification


TCW-DPL-PRS www.technically-speaking.com

This workshop will provide you with skills to clarify your message, become more influential, and achieve desired results. This in-depth exploration of communication and presentation skills will deliver insight into what motivates others to embrace your ideas and your decisions. You’ll learn to establish and maintain trust, credibility, and support.

Exploration of Thought Leadership Participant Delivery of Prepared

Presentations* Focused Personal Feedback Building Trust and Rapport Understanding Non-Verbal Communication Psychology of Audiences Masterful Q&A Session Management Implementation of Concepts* Powerful Persuasion and Influence Methods Practical Skill Exercise* Humor and Storytelling for Improved Message

Reception Interactive Application Participant Delivery of Enhanced Message* Individualized Coaching

*Portions may be videotaped to facilitate feedback


Price - $ 1,197 USD (1 Day) $ 1,797 USD (2 Day)

Course Part Number – TCW-DPL-SDW (1 Day) TCW-DPL-MDW (2 Day)

Who Should Attend – This course is designed to support the needs of managers, directors and executives.

Register Today


Visit technically-speaking.com for trainings in the Americas, Europe, Asia Pacific, Japan, or India. For other geographical regions please contact us at [email protected] for logistical specifics. After completing this comprehensive training,

you will have the necessary skills to:

• Speak with confidence, clarity, andcommand

• Persuade difficult audiences• Maintain composure under pressure• Manage Q&A sessions like a Pro• Use non-verbal communication to connect

with and direct others

7

Powerful Persuasion and Influence Techniques

TCW-PIT-CMB Course Specification

Course Description

TCW-PIT-CMB www.technically-speaking.com

Course Outline

The most successful influencers know how to trigger cooperation and desirable outcomes, whether one-on-one or with an audience. In this high-impact, research based workshop, we will show you the secrets they know and the key factors that lead to ethical persuasion and influence. We’ll explore how the mind filters messages with an emphasis on the psychology of persuasion. You’ll leave empowered with the tools to best present your ideas and recommendations to receive optimal support.

Major Factors in Human Influence Overview of Psychology of Persuasion Determining What People Want* Establishing Likability and Trust Linguistic Techniques for Building Agreement Message Framing Exercise* Asking the Right Questions to Get the Right

Answers The “Give/Get” cycle – Maximizing the Concept

of Worthy Intent Developing Appealing Value Propositions Preparing and Delivering Messages to Appeal to

Different Personality Types Hands-on Lab - Recognizing and Adapting to

Varied Audiences* The “Must-Know” Body Language Techniques Bringing the Elements Together for Success

*Exercises are condensed for Half-Day Session

Course Duration – ½ Day or One-Day Workshop

Price - $ 597 USD (½ Day) $ 797 USD (1 Day)

Course Part Number – TCW-PIT-CDW (½ Day) TCW-PIT-SDW (1 Day)

Who Should Attend - This course is designed for Client Facing Professionals (CFPs), sales and leadership professionals, and those responsible for creating a shared vision

Register Today




• Establish trust and rapport• Generate a positive first impression• Frame your message to gain support• Build consensus• Overcome objections and resistance• Create goodwill and emotional connections

8

Non-Verbal Communication:

The Influence of Body Language

TCW-NVC-CMB Course Specification

Course Description

TCW-NVC-CMB www.technically-speaking.com

Course Outline

Imagine being able to stimulate a positive response in others before you ever say a word. What we don’t say (our non-verbal communication) is much more persuasive than the actual words that we speak. Knowing how to send the signals and messages that you most want people to receive, while simultaneously reading their responses will give you a true competitive edge. This workshop will reveal insights into creating successful relationships, creating a positive and memorable impression, and maximizing the impact of your every encounter.

Evolution of Non-Verbal Communication Historic and Current Case Studies* Posture and Positioning Interactive Application: Power Poses* Hand Usage and Other Gestures Perfecting Your Handshake Demonstration and Implementation Exercise* Facial Expressions and Eye Contact What the Eyes Say – Exercise* MicroExpressions Message and Body Language Congruence Taking Control of Your Non-Verbal

Communication The Nerves and Body Language Relationship Body Talk: How to Send it & How to Read it* Impactful Message Delivery Content Consolidation and Review




Course Part Number – TCW-NVC-CLW (½ Day) TCW-NVC-SDW (1 Day)

Who Should Attend - This course is designed for professionals who are responsible for connecting with others and delivering messages to decision makers at multiple levels. The content is suitable for interpersonal and formal presentation communicators.

Register Today




• Influence others non-verbally• Generate a positive first impression• Control and direct your body language• Establish trust and rapport• Build credibility and subject matter authority• Activate your “Honesty Gauge”

9

Cross Cultural Communication

TCW-CCC-CMB Course Specification


TCW-CCC-CMB www.technically-speaking.com

In this thought provoking workshop, we’ll explore the many facets of today’s blended workplace. At the intersection of different national origins and varied cultures, lies the opportunity for absolute synergy. In order to achieve that, effective communication is essential. With expert contributors and regional authorities, this course will provide you with tools to improve your communication amongst diverse groups and individuals and reap the benefits of differing perspectives.

*For onsite clients, we will customize segments to supportyour internal policies and regional needs

Introduction and Overview of Cross CulturalCommunication

World Views, Perspectives, and Interpretationso Views of Time, Authority, and Statuso Language Usage and Word Meaningso Individual vs. Collective Cultureso High vs. Low Context Cultures

Application and Demonstration of Concepts* Importance of Non-Verbal Communication

o Personal Space/ Position Boundarieso Eye Contact and Expressionso Handshakes, Gestures, and Contact

Etiquette in Business and Social Settings Interactive Reinforcement Exercise* Listening Techniques with Second Language

Speakers Message Interpretation, Classification, and

Response Development Working with Interpreters Synthesizing Content Exercise*

*Not all exercises are covered in the ½ day or online class

Course Duration – Online, ½ Day, or One-Day Workshop

Price - $ 197 USD (Online) $ 397 USD (½ Day) $ 597 (1 Day)

Course Part Number – TCW-CCC-OLW (Online) TCW-CCC-CLW (1/2 Day) TCW-CCC-SDW (1 Day)

Who Should Attend - This course is designed for technical professionals who interact with multicultural colleagues and/or clients.

Register Today




• Communicate successfully when speaking withdiverse professionals

• Create culturally appropriate writtencorrespondence – especially email

• Adapt and adjust quickly to the styles of othercultures

• Use appropriate body language and avoidculturally offensive gestures

• Create positive business relationships

10

Skillfully Managing Q&A Sessions

TCW-QAS-PRS Course Specification


TCW-QAS-PRS www.technically-speaking.com

This program covers the critical Dos and Don’ts to avoid “Death by Q&A”. The reality is, if your Q&A session is not a success, the perception of your entire presentation suffers. There is more to managing a Q&A session than simply answering questions, much more. In this workshop you’ll learn to read between the lines and utilize strategic methods to ensure your responses serve your prime purpose and best support your residual message.

Introduction to Workshop Goals Exploring the Value of Q&A Sessions Planning Principles Collaborative Exercise* Developing Responses to the 7 Common

Types of Questions Implementation of Concept* Phrasing Answers to Improve Retention of

Residual Message Using Body Language to Build Trust and

Support Demonstration* Handling Challenging Situations Time Management and Special Techniques Mastering Content*

*Exclusive to live training workshops

Course Duration - Online or ½ Day Workshop

Price $ 197 USD (Online) $ 397 USD (½ Day)

Course Part Number – TCW-QAS-OLW (Online)

TCW-QAS-CLW (1/2 Day)

Who Should Attend - This course is designed to support the needs of all professionals who deliver presentations in technical companies.

Register Today



After completing this comprehensive training, you will have these necessary skills:

• Preparing and planning Q&A techniques• Recognizing and handling the 7 common types

of questions• Approaches for difficult or confrontational

questioners• Keeping the Q&A session constructive• Impacts of body language on message

perception

11

Conducting Dynamic Webinar and Remote Presentations

TCW-WEB-PRS Course Specification


TCW-WEB-PRS www.technically-speaking.com

The modern workplace leverages the technology of web-based meetings with high frequency. Presenting via webinar or teleconference has many similarities to presenting to an onsite audience, but there are some distinct and critical differences that must be accounted for. Understanding and mastering the skills to conduct these meetings effectively will allow your message to be clearly understood and retained. This workshop will give you the tools to engage and connect with a remote audience with clarity and positive impact.

Introduction to Fundamentals of Web-Based Meetings

Pros and Cons of Webinars and RemoteMeetings

Reinforcement Exercise* Exploring the Roles and Responsibilities of

the Meeting Organizer Secrets of Dynamic Webinar Presenters Practical Application of Concept* Slide Design Considerations for Remote

Viewers Hands-On Lab* Methods to Incorporate Interactivity for

Increased Engagement and MessageRetention

Putting it All Together – Mastery Activity*

*Exclusive to live training workshops

Course Duration – Online or ½ Day Workshop

Price - $ 197 USD (Online) $ 397 USD (½ Day)

Course Part Number – TCW-WEB-OLW (Online) TCW-WEB-CLW (1/2 Day)

Who Should Attend - This course is designed to support the needs of professionals in technical companies who conduct meetings or deliver presentations remotely.

Register Today




• Elevate engagement of remote audiences• Understand and minimize attention span

challenges• Add interactivity for increased retention• Create critical slide design modifications• Select the most effective format

12

PowerPoint - Mastering Design and Impact

TCW-PPT-PRS Course Specification


TCW-PPT-PRS www.technically-speaking.com

YOU are the presentation; your PowerPoint slides are only visual aids. There are millions of PPT presentations created every day. These slide shows are intended as a tool to support and enhance presentations, but often they not only fail to meet the mark, they can confuse, distract, and cause message resistance in your audience. In this course, we will provide you with the strategies to design slides that deliver optimal results by increasing both audience understanding and acceptance of your message. You will be able to create slides that significantly enhance your presentation. We will show you precisely what to include and what to exclude from your next PowerPoint.

Topic Introduction and Overview of Content Psychology of Visual Aids Examination and Evaluation of Slide Decks Impact of Working Memory and Neuro-

Attention Constraints Color and Design Implications Collaborative Exercise* Effective Methods for Emphasizing Data Creating and Incorporating Charts and

Graphs Hands-on Lab* Applying the Key Concepts for Maximum

Effect**Exclusive to Full Day training workshops

Course Duration – ½ Day or Full-Day Workshop

Price - $ 397 USD (½ Day) $ 597 USD (Full Day)

Course Part Number – TCW-PPT-CLW (1/2 Day) TCW-PPT-SDW (1 Day)

Who Should Attend - This course is appropriate for any position level that gives presentations.

Register Today




• Apply techniques for simple yet powerful slides• Create technical charts and graphs that clarify

your data• Understand the importance of color and styles

for emphasis• Develop logical transitions• Incorporate required data in an engaging way• Enhance message retention

13

One-on-One (1:1) Executive Coaching – Presentations

TCW-OOO-PRS Course Specification

Course Description

TCW-OOO-PRS www.technically-speaking.com

Do you have a major presentation coming up? A report to the Board of Directors, a Stockholder’s meeting, a TedTalk, or a media event? As the top communication coaches for technical professionals, we work with you one-on-one to ensure that you deliver your message with the utmost effect and impact. As a thought leader, your voice has power and meaning, and never more so than when you give a public address. We’ll give you every advanced technique and nuanced device to help you stand as the model of excellence in your company.

Course Duration – One-Day Increments

Price – $1197 USD Per Day

Course Part Number - TCW-OOO-SDW

Who Should Attend – This intensive, individually customized coaching is designed for key professionals responsible for effective delivery of company messaging.


• Be prepared at the granular level• Formulate your message for maximum

audience understanding and retention• Speak with ultimate influence and impact• Create impressive visual aids• Meaningfully connect with your target audience• Generate compelling calls to action

Register Today



14

Deconstructing the Technical Presentation

TCW-DTP-PRS Course Specification


TCW-DTP-PRS www.technically-speaking.com

This workshop explores the essential components of working with required data, paired with elevated techniques on how to engage and connect with any audience and how to deliver a presentation that is impressive. A live technical presentation will be delivered by a working engineer, then broken into individual pieces and analyzed to reveal the process of creating an impactful presentation. We’ll explore and demonstrate step-by-step how to organize your content, design your slides, and deliver your message. There are specific methods that can subtly change a dry data-driven presentation into a memorable experience for the listeners, and we’ll share them all with you.

Overview of Technical PresentationConcepts

Sample Presentation on FPGA Design –Delivered by Co-Instructor

Analysis Exercise In-Depth Evaluation of 12 Key Components

Course Duration – Lunch & Learn (60-90 Minutes)

Price - $ 197 USD

Course Part Number – TCW-DTP-CLW

Who Should Attend - This course is intended for technical professionals at all levels of skill to demonstrate the components of an effective technical presentation.

Register Today




• Give your data meaning• Engage your audience• Use illustrative examples to reinforce key points• Connect with your audience through effective

delivery• Add passion and enthusiasm to enhance

message understanding and retention

15

Powerful Persuasion and Influence Techniques

TCW-PIT-CMB Course Specification

Course Description

TCW-PIT-CMB www.technically-speaking.com

Course Outline

The most successful influencers know how to trigger cooperation and desirable outcomes, whether one-on-one or with an audience. In this high-impact, research based workshop, we will show you the secrets they know and the key factors that lead to ethical persuasion and influence. We’ll explore how the mind filters messages with an emphasis on the psychology of persuasion. You’ll leave empowered with the tools to best present your ideas and recommendations to receive optimal support.

Major Factors in Human Influence Overview of Psychology of Persuasion Determining What People Want* Establishing Likability and Trust Linguistic Techniques for Building Agreement Message Framing Exercise* Asking the Right Questions to Get the Right

Answers The “Give/Get” cycle – Maximizing the Concept

of Worthy Intent Developing Appealing Value Propositions Preparing and Delivering Messages to Appeal to

Different Personality Types Hands-on Lab - Recognizing and Adapting to

Varied Audiences* The “Must-Know” Body Language Techniques Bringing the Elements Together for Success




Course Part Number – TCW-PIT-CDW (½ Day) TCW-PIT-SDW (1 Day)

Who Should Attend - This course is designed for Client Facing Professionals (CFPs), sales and leadership professionals, and those responsible for creating a shared vision

Register Today




• Establish trust and rapport• Generate a positive first impression• Frame your message to gain support• Build consensus• Overcome objections and resistance• Create goodwill and emotional connections

17

Successful Team Building and Collaboration Methods

TCW-TBC-CMB Course Specification

Course Description

TCW-TBC-CMB www.technically-speaking.com

Course Outline

We have the same goal, but different methods to accomplish it - now what? This interactive, exercise-driven workshop delivers a pathway to reaching decisions with buy-in and support from distinct or even contrasting parties. With hands-on lessons, you will learn the skills to bring people together to accomplish shared goals. You’ll leave empowered with tools to improve outcomes and build consensus through inspired reasoning and evaluation strategies, and to view each team member through a different lens based on individual value and unique contribution.

Introduction to Effective, Productive, &Successful Teams

Personality Intelligence (PI)™ Issue Conflicts vs. Personality Conflicts Creative Problem Solving Building Trust and Rapport Interactive Bonding Exercise* Calibrating Intellect and Emotion Applying Communication Skills* Guided Contributory Brainstorming Methods Accountability and Progress Mapping Systems Implementing and Linking Concepts* All Hands vs. Right Hands Meetings Agenda Building Lab* Special Challenges of Virtual Teams

Synthesizing Principles




Course Part Number – TCW-TBC-CDW (½ Day) TCW-TBC-SDW (1 Day)

Who Should Attend - This course is designed for leaders and their team members interested in increasing productivity and generating synergy within their team by maximizing and benefiting from the cultural, generational, and personality diversity of its individuals.

Register Today




• Create a collaborative culture• Build trust between distinctly defined groups• Bridge differences• Identify and benefit from commonalities• Maximize the KSAs of each team member for

optimal outcomes• Conduct purposeful, results-yielding meetings

18

Communication Essentials for Leaders

TCW-CEL-INT Course Specification


TCW-CEL-INT www.technically-speaking.com

In this deep-dive workshop, you will learn powerful techniques to build rapport, trust and respect through your interpersonal communication with your team and colleagues. The content is based on the H.E.A.R.T. model of building winning business relationships. These organizational communication insights will allow you to inspire confidence and action. You’ll learn the keys to increasing collaboration and reducing conflict, which lead to higher productivity.

Introduction to the Principles of EffectiveLeadership Communication

Personality Types and Emotional Intelligence Self-Analysis Exercise H.E.A.R.T. Model – Building Rapport and Trust Techniques for Effective Listening (Reading

Between the Lines) Collaborative Application of Concepts Practices for Thought Leadership Persuasion and Influence Methods Practical Application Building Teams and Collaborative Working

Groups Cross-Cultural Considerations Implementing Content Mitigating Conflict and Leading Solutions Synopsis and Review of Theories

Course Duration – One-Day Workshop

Price - $ 797 USD

Course Part Number – TCW-CEL-SDW

Who Should Attend - This course is designed for management personnel, team leaders, and key personnel.

Register Today




• Maximize your motivational and influentialimpact in dynamic settings

• Reduce misunderstandings to increaseproductivity

• Adapt to the communication styles of others• Develop enhanced listening skills• Elevate your cross-cultural acumen

19

Managing Change

TCW-MCW-INT Course Specification


TCW-MCW-INT www.technically-speaking.com

This workshop provides a flexible and scalable process to prepare for and implement organizational change whether small or large. We’ll give you the tools to navigate through the crossroads of the way things were to the way things will be, while maximizing the benefits and minimizing resistance. This program is founded on the psychology of behavior and motivation and will empower you to handle change in programs, projects, personnel, and even organizational crisis while maintaining integrity and productivity.

Introduction to the Change Acceptance Journey Preparing for Change

o Assessing Values and Objectives Aligning the Needs and Wants of Disparate

Stakeholders Interactive Application* Managing Unexpected Change Identifying the Underlying Issues Causing

Resistance Impact Analysis Effectively Communicating Change Information

o Message Development & Deliveryo Reframing

Content Reinforcement Exercise* The Pathway to Positive Outcomes The Behavioral Change Platform* Garnering Agreement and Support Strengthening and Moving Forward

*Exercises are condensed or excluded for ½ day session


Price - $ 397 USD (½ Day) $ 597 (1 Day)

Course Part Number – TCW-MCW-CLW (½ Day)

TCW-MCW-SDW (1 Day)

Who Should Attend – This course is designed for professionals responsible for administering and managing change. This is also appropriate for teams and groups affected by change.

Register Today




• Promote readiness for change• Communicate with the affected parties to

facilitate a smooth transition• Attain maximize buy-in• Help team members accept change• Reduce drops in morale and productivity

20

Business Etiquette

TCW-BEW-INT Course Specification


TCW-BEW-INT www.technically-speaking.com

The most successful business people in the world understand that even in more casual times, how we present ourselves has powerful influence on how we are regarded personally and professionally. In this unique workshop, we’ll cover the critical components of business etiquette through a pragmatic program of modern manners and business relationship development.

A deep-dive after class formal dinner is available as an optional add-on to reinforce and practice the lessons from the workshop. (Available in most markets)

Manners Matter! An Overview of SuccessfulBusiness Behavior

Process of Perception Development Making a Great First Impression* Generational, Gender, and Orientation

Considerations Appropriate Conduct with the Opposite Sex Non-Verbal Communication

o Perfecting Your Handshake*o Comfort Zones and Contexts

Concept Implementation Exercises* Proper Introductions* Etiquette in Formal and Informal Settings Correspondence The Rules of Social Media and Email* Table Manners*

*Exercises are condensed or excluded in ½ Day SessionCourse Duration – ½ Day or One-Day Workshop

Price - $ 397 USD (½ Day) $ 597 (1 Day)

Course Part Number – TCW-BEW-CLW (½ Day)

TCW-BEW-SDW (1 Day)

Who Should Attend – This course is designed for professionals in leadership positions, Client-Facing Professionals (CFPs), and staff who interact with organizational stakeholders.


• Create a positive first impression• Read and adapt to expectation cues of others• Build rapport through body language• Interact effectively at meetings, conferences,

meals, social mixers and networking events• Generate professional respect, regard, and

reverence

Register Today


Visit technically-speaking.com for trainings in the Americas, Europe, Asia Pacific, Japan, or India. For other geographical regions please contact us at [email protected] for logistical specifics

21

Non-Verbal Communication:

The Influence of Body Language

TCW-NVC-CMB Course Specification

Course Description

TCW-NVC-CMB www.technically-speaking.com

Course Outline

Imagine being able to stimulate a positive response in others before you ever say a word. What we don’t say (our non-verbal communication) is much more persuasive than the actual words that we speak. Knowing how to send the signals and messages that you most want people to receive, while simultaneously reading their responses will give you a true competitive edge. This workshop will reveal insights into creating successful relationships, creating a positive and memorable impression, and maximizing the impact of your every encounter.

Evolution of Non-Verbal Communication Historic and Current Case Studies* Posture and Positioning Interactive Application: Power Poses* Hand Usage and Other Gestures Perfecting Your Handshake Demonstration and Implementation Exercise* Facial Expressions and Eye Contact What the Eyes Say – Exercise* MicroExpressions Message and Body Language Congruence Taking Control of Your Non-Verbal

Communication The Nerves and Body Language Relationship Body Talk: How to Send it & How to Read it* Impactful Message Delivery Content Consolidation and Review




Course Part Number – TCW-NVC-CLW (½ Day) TCW-NVC-SDW (1 Day)

Who Should Attend - This course is designed for professionals who are responsible for connecting with others and delivering messages to decision makers at multiple levels. The content is suitable for interpersonal and formal presentation communicators.

Register Today




• Influence others non-verbally• Generate a positive first impression• Control and direct your body language• Establish trust and rapport• Build credibility and subject matter authority• Activate your “Honesty Gauge”

22

Essentials of Conflict Management and Mediation

TCW-CMM-INT Course Specification


TCW-CMM-INT www.technically-speaking.com

Resolving conflict can be difficult, but learning the system to find solutions quickly and equitably will make your job as a manager much easier and keep your teams more productive. Conflict management is a process and a skill that can be learned. This workshop will give you the tools you need to deal well with the challenges of conflict in the workplace. Conflict can have positive aspects and handling it effectively will actually strengthen your teams through meaningful dialogues and exploration of complications that hinder productivity and lower morale.

Sources of Conflicts Personality and Emotional Intelligence Exercise* Team Dynamics Critical Thinking and Problem Solving Models Active Listening Conflict Management Styles Practical Application of Concepts* The Manager as Mediator Linguistic Techniques and Language Choices

with Demonstrations* Objective Criteria and Reason-Based Standards Communication Flow

o Barriers to Effective Communication Collaborating vs. Compromising Maintaining Professionalism, and Integrity Resolving vs. Winning The Winding Road to Win-Win*

*Exercises are condensed in the One-Day session


Price - $ 597 USD (1 Day) $ 997 (2 Day)

Course Part Number – TCW- CMM-SDW (1 Day)

TCW-CMM-MDW (2 Day)

Who Should Attend – This course is designed for professionals in management or supervisory positions, and those who lead teams.


• Identify the underlying factors of conflicts• Negotiate solutions successfully• Separate people from issues• Stay calm and maintain composure under

pressure• Reach fair, expeditious, and constructive

results

Register Today



23

Cross Cultural Communication

TCW-CCC-CMB Course Specification


TCW-CCC-CMB www.technically-speaking.com

In this thought provoking workshop, we’ll explore the many facets of today’s blended workplace. At the intersection of different national origins and varied cultures, lies the opportunity for absolute synergy. In order to achieve that, effective communication is essential. With expert contributors and regional authorities, this course will provide you with tools to improve your communication amongst diverse groups and individuals and reap the benefits of differing perspectives.

*For onsite clients, we will customize segments to supportyour internal policies and regional needs

Introduction and Overview of Cross CulturalCommunication

World Views, Perspectives, and Interpretationso Views of Time, Authority, and Statuso Language Usage and Word Meaningso Individual vs. Collective Cultureso High vs. Low Context Cultures

Application and Demonstration of Concepts* Importance of Non-Verbal Communication

o Personal Space/ Position Boundarieso Eye Contact and Expressionso Handshakes, Gestures, and Contact

Etiquette in Business and Social Settings Interactive Reinforcement Exercise* Listening Techniques with Second Language

Speakers Message Interpretation, Classification, and

Response Development Working with Interpreters Synthesizing Content Exercise*

*Not all exercises are covered in the ½ day or online class

Course Duration – Online, ½ Day, or One-Day Workshop

Price - $ 197 USD (Online) $ 397 USD (½ Day) $ 597 (1 Day)

Course Part Number – TCW-CCC-OLW (Online) TCW-CCC-CLW (1/2 Day) TCW-CCC-SDW (1 Day)

Who Should Attend - This course is designed for technical professionals who interact with multicultural colleagues and/or clients.

Register Today




• Communicate successfully when speaking withdiverse professionals

• Create culturally appropriate writtencorrespondence – especially email

• Adapt and adjust quickly to the styles of othercultures

• Use appropriate body language and avoidculturally offensive gestures

• Create positive business relationships

24

Building Winning Business Relationships

TCW-HRT-INT Course Specification


TCW-HRT-INT www.technically-speaking.com

The process of starting, growing, and maintaining a business relationship is a critical skill that cannot be left to chance or “natural” ability. This workshop, based on the book, “The HEART of the Deal: Creating Winning Business Relationships”, provides an in-depth exploration of the psychology of why people prefer to do business with some people or organizations over others. We will delve into the HEART skills practiced by the most successful business people in the world and provide you the tools to connect with others instantly to initiate or bolster your business connection.

Introduction to the HEART Modelo Characteristics that Create Winning

Business Relationships Personality Intelligence (PI)™

o Identifying and Adapting for OptimalConnection

The Power of Principled Intent The “EE” Principle Authenticity Exercise The Pathway to Connecting There is NO Relationship Without Trust

o Building and Maintaining Trust Body Talk

o Sending the Right Messageso Reading Others

Optimizing Communicationo In Person, Phone, and Email Variances

Creating Reciprocal RespectCourse Duration – One-Day Workshop

Price - $ 797 USD

Course Part Number – TCW-HRT-SDW

Who Should Attend – This course is designed for individuals that have face to face contact with important business partners. Sessions can be customized for administrative, sales, or executive levels.


• Create a highly productive first meeting• Connect with clients and set a powerful positive

impression of you and your company• Know what to say and how to say it• Read and respond to the body language of

others• Create the comfort and rapport that lead to long- term beneficial relationships

Register Today



25

Women in Technology Seminar

TCW-WIT-INT Course Specification

Course Description Event Dates and Speakers vary by location.

Please check our website for upcoming seminars.

TCW-WIT-INT www.technically-speaking.com

Decades of expertise come together and focus on the unique role of women in the technology industry. This travelling workshop provides tools to craft your career and empower your life. This one-of-a-kind seminar brings together some of the brightest minds and most successful women in technology and allied fields to share their insights, firsthand experiences, and secrets to success. Don’t leave your potential on the table. Learn how to rise and thrive in the world of technology.

*This program can be scaled for onsite delivery

Course Duration – One-Day Seminar

Price - $ 597 USD

Course Part Number – TCW-WIT-SDW

Who Should Attend – This course is designed for professional women who work in the technology industry. Although the seminar is intended for women, it is open for everyone interested in this subject matter.

What you can expect at the Women In Technology Seminar:

• Astute insights from industry experts• Relevant skill building strategies• How to identify opportunities for growth in an

ever-changing environment• Exploration of emerging trends• Techniques to prioritize competing demands• Discussion of the evolutionary trajectory of

women in technology

Register Today



26

Course List and Price Guide

All prices are USD

www.technically-speaking.com

Course Title Code One-Day Two-Day ½ Day Online

Building Winning Business Relationships TCW-HRT 797 - - - Business Etiquette TCW-BEW 597 - 397 - Communication Essentials for Leaders TCW-CEL 797 - - - Conducting Dynamic Webinar and Remote Presentations

TCW-WEB - - 397 197

Cross-Cultural Communication TCW-CCC 597 - 397 197 Deconstructing the Technical Presentation - Lunch & Learn (60-90 Minutes)

TCW-DTP - - 197 -

Delivering Effective Presentations (DEP) – Advanced

TCW-DPA 1197 1797 - -

Delivering Effective Presentations (DEP) – Introductory

TCW-DPB 997 - - -

Delivering Effective Presentations (DEP) – Leadership

TCW-DPL 1197 1797 - -

Essentials of Conflict Management and Mediation

TCW-CMM 597 997 - -

Managing Change TCW-MCW 597 - 397 - Non-Verbal Communication: The Influence of Body Language

TCW-NVC 797 - 597 -

One-on-One (1:1) Executive Coaching TCW-OOO 1197 - - - Powerful Persuasion and Influence Techniques

TCW-PIT 797 - 597 -

PowerPoint – Mastering Design and Impact TCW-PPT 597 - 397 - Skillfully Managing Q&A Sessions TCW-QAS - - 397 197 Successful Team Building and Collaboration Methods

TCW-TBC 597 - 397 -

Women in Technology Seminar TCW-WIT 597 - - -

27

Vivado™ for Experienced Xilinx Users FPGA 3

FPGA-VEU-ILT (v1.0) Course Specification

Course Description This custom class bridges the gap for existing ISE users, Moving to Vivado 2014.1 (or later). This is a comprehensive update and introduction to the most powerful and useful features of Xilinx Vivado® Design Suite. You’ll learn the underlying database and static timing analysis (STA) mechanisms.

You’ll learn to utilize Tcl for navigating the design, creating the complete range of Xilinx design timing constraints (XDC), and creating timing reports.

That includes multi-cycle paths, false path, and min/max timing constraints.

Finally, you will learn how to maximize productivity by using the Vivado Tcl scripting capabilities for both the project-based and non-project batch flows, as well as Guided Design Flows.

Level – FPGA 3 Course Duration – 2 days Price – $1400 Course Part Number – FPGA-VEU-ILT Who Should Attend? – Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity. Prerequisites ▪ Some knowledge of FPGA design techniques is

helpful▪ Experience with the Xilinx ISE tools or attendance

of one of our introductory Vivado Design Suitetraining courses is helpful

▪ Intermediate knowledge of Verilog or VHDLSoftware Tools▪ Vivado Design or System Edition 2015.3Hardware▪ Architecture: UltraScale™ and 7 series FPGAs*▪ Demo board: None*

Course Outline and Lab Descriptions Day 1 Comparing ISE to Vivado XST versus Vivado Synthesis

Accessing the Design Database ▪ Lab 1: Vivado Database

Leveraging IP Integrator

▪ Lab 2: IP IntegratorXDC Constraints & Timing Report

Input/Output Path Exceptions Advanced I/O

UCF to XDC Conversion

• Lab 3: Timing Constraints

Day 2 ▪ Lab 4: Timing Exceptions

Project and Non-Project FlowsTcl Scripting in Vivado Instantiation

▪ Lab 5: Tcl ScriptingTiming closure in Vivado

Register Today Xilinx’s network of Authorized Training Providers (ATP) delivers public and private courses in locations throughout the world. Please contact your closest ATP for more information, to view schedules, or to register online. Visit www.xilinx.com/training and click on the region where you want to attend a course. Americas, contact your training provider at www.xilinx.com/training/atp.htm#NA or send your inquiries to [email protected]. Europe, contact your training provider at www.xilinx.com/training/atp.htm#EU or send your inquiries to [email protected]. Asia Pacific, contact your training provider at www.xilinx.com/training/atp.htm#AP, or send your inquiries to [email protected], or call +852-2424-5200. Japan, contact your training provider at www.xilinx.com/training/atp.htm#JP, or send your inquiries to [email protected], or call +81-3-6744-7970.

© 2015 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

FPGA-VEU-ILT (v1.0) www.xilinx.com Course Specification 1-800-255-7778

29


Designing FPGAs Using the Vivado Design Suite 1 FPGA 1

FPGA-VDES1-ILT (v1.0) Course Specification

FPGA-VDES1-ILT (v1.0) updated June 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow.

For those uninitiated to FPGA design, this course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

Level – FPGA 1

Course Duration – 2 days

Price –

Course Part Number – FPGA-VDES1-ILT

Who Should Attend? – Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite

Prerequisites

▪ Basic knowledge of the VHDL or Verilog language

▪ Digital design knowledge

Recommended Recorded Videos

▪ Basic FPGA Architecture: Slice and I/O Resources*

▪ Basic FPGA Architecture: Memory and Clocking Resources*

Software Tools

▪ Vivado Design or System Edition 2016.1

Hardware

▪ Architecture: UltraScale™ and 7 series FPGAs**

▪ Demo board (optional): Kintex® UltraScale FPGA KCU105 board orKintex-7 FPGA KC705 board**

* Go to www.xilinx.com/training and click the Online Training tab to view these videos.

** This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Use the New Project Wizard to create a new Vivado IDE project

▪ Describe the supported design flows of the Vivado IDE

▪ Generate a DRC report to detect and fix design issues early in the flow

▪ Use the Vivado IDE I/O Planning layout to perform pin assignments

▪ Synthesize and implement the HDL design

▪ Apply clock and I/O timing constraints and perform timing analysis

▪ Describe the "baselining" process to gain timing closure on a design

▪ Use the Schematic and Hierarchy viewers to analyze and cross-probe a design

▪ Use the Vivado logic analyzer and debug flows to debug a design

Course Outline Day 1

▪ Introduction to FPGA Architecture, 3D IC, SoC {Lecture}

▪ UltraFast Design Methodology Introduction {Lecture, Demo}

▪ Introduction to Vivado Design Flows {Lecture}

▪ Vivado Design Suite Project-Based Flow {Lecture, Lab}

▪ Introduction to Digital Coding Guidelines {Lecture}

▪ Synthesis and Implementation {Lecture, Lab}

▪ Vivado Design Rule Checks {Lab}

▪ Timing Constraints Wizard {Lecture, Lab}

▪ Timing Constraints Editor {Lecture}

▪ Report Clock Networks {Lecture, Demo}

▪ Introduction to Clock Constraints {Lecture, Lab, Demo}

▪ Vivado Design Suite I/O Pin Planning {Lecture, Lab}

▪ I/O Constraints and Virtual Clocks {Lecture, Lab}

Day 2

▪ Basic Design Analysis in the Vivado IDE {Lab, Demo}

▪ Setup and Hold Timing Analysis {Lecture}

▪ Introduction to Vivado Timing Reports {Lecture, Demo}

▪ Vivado IP Flow {Lecture, Lab, Demo}

▪ Xilinx Power Estimator Spreadsheet {Lecture, Lab}

▪ Introduction to the Vivado Logic Analyzer {Lecture, Demo}

▪ HDL Instantiation Flow {Lecture, Lab}

▪ Introduction to Triggering {Lecture}

▪ Netlist Insertion Flow {Lecture, Lab}

▪ Debug Cores {Lecture}

▪ Introduction to the Tcl Environment {Lecture, Lab}

▪ Using Tcl Commands in the Vivado Design Suite Project Flow {Lecture, Demo}

▪ Tcl Syntax and Structure {Lecture}

Topic Descriptions Day 1

▪ Introduction to FPGA Architecture, 3D IC, SoC – Overview of FPGAarchitecture, SSI technology, and SoC device architecture.

▪ UltraFast Design Methodology Introduction – Introduces themethodology guidelines covered in this course and the UltraFastDesign Methodology checklist.

▪ Introduction to Vivado Design Flows – Introduces the Vivado designflows: the project flow and non-project batch flow.

▪ Vivado Design Suite Project-Based Flow – Create a project, add filesto the project, explore the Vivado IDE, and simulate the design.

▪ Introduction to Digital Coding Guidelines – Covers basic digital coding guidelines used in an FPGA design.

▪ Synthesis and Implementation – Make timing constraints according to the design scenario and synthesize and implement the design.Optionally, generate and download the bitstream to the demo board.

▪ Vivado Design Rule Checks – Run a DRC report on the elaborateddesign to detect design issues early in the flow. Fix the DRCviolations.

▪ Timing Constraints Wizard – Use the Timing Constraints Wizard to apply missing timing constraints in a design.

▪ Timing Constraints Editor – Introduces the timing constraints editor tool to create timing constraints.

▪ Report Clock Networks – Use report clock networks to view the

primary and generated clocks in a design.

▪ Introduction to Clock Constraints – Apply clock constraints and perform timing analysis.

▪ Vivado Design Suite I/O Pin Planning – Use the I/O Pin Planning layout to perform pin assignments in a design.

▪ I/O Constraints and Virtual Clocks – Apply I/O constraints and performtiming analysis.

Day 2

▪ Basic Design Analysis in the Vivado IDE – Use the various design analysis features in the Vivado Design Suite.

30





▪ Setup and Hold Timing Analysis – Understand setup and hold timing analysis.

▪ Introduction to Vivado Timing Reports – Generate and use Vivado timing reports to analyze failed timing paths.

▪ Vivado IP Flow – Customize IP, instantiate IP, and verify the hierarchyof your design IP.

▪ Xilinx Power Estimator Spreadsheet – Estimate the amount ofresources and default activity rates for a design and evaluate the estimated power calculated by XPE.

▪ Introduction to the Vivado Logic Analyzer – Overview of the Vivadologic analyzer for debugging a design.

▪ HDL Instantiation Flow – Covers the HDL instantiation flow to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.

▪ Introduction to Triggering – Introduces the trigger capabilities of theVivado logic analyzer.

▪ Netlist Insertion Flow – Use the Netlist Insertion flow to insert ILA cores into an existing synthesized netlist and debug a common problem.

▪ Debug Cores – Understand how the debug hub core is used toconnect debug cores in a design.

▪ Introduction to the Tcl Environment – Introduces Tcl (tool command language).

▪ Using Tcl Commands in a Vivado Design Suite Project Flow –Explains what Tcl commands are executed in a Vivado Design Suite project flow.

▪ Tcl Syntax and Structure – Understand the Tcl syntax and structure.

Register Today Xilinx’s network of Authorized Training Providers (ATP) delivers public and private courses in locations throughout the world. Please contact your closest ATP for more information, to view schedules, or to register online.

Visit www.xilinx.com/training and click on the region where you want to attend a course.

Americas, contact your training provider at www.xilinx.com/training/atp.htm#NA or send your inquiries to [email protected].

Europe, contact your training provider at www.xilinx.com/training/atp.htm#EU or send your inquiries to [email protected].

Asia Pacific, contact your training provider at www.xilinx.com/training/atp.htm#AP, or send your inquiries to [email protected], or call +852-2424-5200.

Japan, contact your training provider at www.xilinx.com/training/atp.htm#JP, or send your inquiries to [email protected], or call +81-3-6744-7970

31




FPGA-VDES2-ILT (v1.0) updated May 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Level – FPGA 2


Price –


Who Should Attend? – Digital designers who have a working knowledge of

HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

▪ Designing FPGAs Using the Vivado Design Suite 1 course

▪ Working HDL knowledge (VHDL or Verilog)

▪ Digital design experience

Optional Videos

▪ Basic HDL Coding Techniques*

Software Tools


Hardware


▪ Demo board (optional): Kintex®-7 FPGA KC705 board**

* Go to www.xilinx.com/training and click the Online Training tab to view thisvideo.

** This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Create a Tcl script to create a project, add sources, and implement adesign

▪ Describe and use the clock resources in a design

▪ Build resets into your system for optimum reliability and design speed

▪ Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design

▪ Use the Vivado IP integrator to create a block design

▪ Create and package your own IP and add to the Vivado IP catalog toreuse

▪ Describe the HLx design flow that increases productivity

▪ Debug a design with multiple clock domains with the help of multipledebug cores using the Vivado logic analyzer

▪ Identify synchronous design techniques

▪ Describe how an FPGA is configured


▪ UltraFast Design Methodology Introduction {Lecture}

▪ Scripting in Vivado Design Suite Project Mode {Lecture, Lab}

▪ Clocking Resources {Lecture, Lab}

▪ Synchronous Design Techniques {Lecture}

▪ Register Duplication {Lecture}

▪ Resets {Lecture, Lab}

▪ I/O Logic Resources {Lecture}

▪ Timing Summary Report {Lecture, Demo}

▪ Introduction to Timing Exceptions {Lecture, Lab, Demo}

▪ Generated Clocks {Lecture, Demo}

▪ Clock Group Constraints {Lecture, Demo}

Day 2

▪ Creating and Packaging Custom IP {Lecture, Lab}

▪ Using an IP Container {Lecture, Demo}

▪ Designing with IP Integrator {Lecture, Lab, Demo}

▪ Introduction to the HLx Design Flow {Lecture, Lab, Demo}

▪ Configuration Process {Lecture}

▪ Sampling and Capturing Data in Multiple Clock Domains {Lecture,Lab}

▪ Design Analysis Using Tcl Commands {Lecture, Demo, Lab}

▪ Power Analysis and Optimization Using the Vivado Design Suite{Lecture, Lab}


▪ UltraFast Design Methodology Introduction – Overview of the methodology guidelines covered in this course.

▪ Scripting in Vivado Design Suite Project Mode – Explains how to writeTcl commands in the project-based flow for a design.

▪ Clocking Resources – Describes various clock resources, clocking layout, and routing in a design.

▪ Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.

▪ Register Duplication – Use register duplication to reduce high fanoutnets in a design.

▪ Resets – Investigates the impact of using asynchronous resets in adesign.

▪ I/O Logic Resources – Overview of I/O resources and the IOBproperty for timing closure.

▪ Timing Summary Report – Use the post-implementation timingsummary report to sign-off criteria for timing closure.

▪ Introduction to Timing Exceptions – Introduces timing exception constraints and applying them to fine tune design timing.

▪ Generated Clocks – Use the report clock networks report to determineif there are any generated clocks in a design.

▪ Clock Group Constraints – Apply clock group constraints for asynchronous clock domains.

Day 2

▪ Creating and Packaging Custom IP – Create your own IP andpackage and include it in the Vivado IP catalog.

▪ Using an IP Container – Use a core container file as a single file representation for an IP.

▪ Designing with IP Integrator – Use the Vivado IP integrator to create the uart_led subsystem.

▪ Introduction to the HLx Design Flow – Use the HLx design flow toincrease productivity and reduce run time when designing andverifying a design.

▪ Configuration Process – Understand the FPGA configuration process,such as device power up, CRC check, etc.

▪ Sampling and Capturing Data in Multiple Clock Domains – Overview of debugging a design with multiple clock domains that requiremultiple ILAs.

▪ Design Analysis Using Tcl Commands – Analyze a design using Tclcommands.

▪ Power Analysis and Optimization Using the Vivado Design Suite –Use report power commands to estimate power consumption.

32




FPGA-VDES2-ILT (v1.0) updated May 2016 www.xilinx.com Course Specification 1-800-255-7778







33





Course Description This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

Level – FPGA 3


Price –


Who Should Attend? – FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite

Prerequisites



▪ Intermediate HDL knowledge (VHDL or Verilog)

▪ Solid digital design background

Optional Videos

▪ Basic HDL Coding Techniques*

▪ Power Estimation*

Software Tools


Hardware


▪ Demo board: Kintex®-7 FPGA KC705 board

* Go to www.xilinx.com/training and click the Online Training tab to view these videos.

** This course focuses on the UltraScale and 7 series architectures. Check with your local Authorized Training Provider for specifics or other customizations.


▪ Employ good alternative design practices to improve design reliability

▪ Define a properly constrained design

▪ Apply baseline constraints to determine if internal timing paths meetdesign timing objectives

▪ Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals

▪ Build a more reliable design that is less vulnerable to metastabilityproblems and requires less design debugging later in the developmentcycle

▪ Increase performance by utilizing FPGA design techniques

▪ Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report


▪ UltraFast Design Methodology Introduction {Lecture, Demo}

▪ Timing Simulation {Lecture, Lab}

▪ Vivado Design Suite Non-Project Mode {Lecture}

▪ Revision Control Systems in the Vivado Design Suite {Lecture, Lab}

▪ Baselining {Lecture, Lab, Demo}

▪ Pipelining {Lecture, Lab}

▪ Inference {Lecture, Lab}

▪ Synchronization Circuits {Lecture, Demo}

Day 2

▪ Report Datasheet {Lecture, Demo}

▪ Report Clock Interaction {Lecture, Demo}

▪ Configuration Modes {Lecture}

▪ Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}

▪ Debug Flow in an IP Integrator Block Design {Lecture, Lab}

▪ Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}

▪ JTAG to AXI Master Core {Lecture, Demo}

▪ Trigger Using the Trigger State Machine in the Vivado Logic Analyzer{Lecture, Lab}

▪ Manipulating Design Properties Using Tcl {Lecture, Lab}


▪ UltraFast Design Methodology Introduction – Introduces themethodology guidelines covered in this course.

▪ Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware.

▪ Vivado Design Suite Non-Project Mode – Create a design in theVivado Design Suite non-project mode.

▪ Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.

▪ Baselining – Use Xilinx-recommended baselining procedures toprogressively meet timing closure.

▪ Pipelining – Use pipelining to improve design performance.

▪ Inference – Infer Xilinx dedicated hardware resources by writingappropriate HDL code.

▪ Synchronization Circuits – Use synchronization circuits for clock domain crossings.

Day 2

▪ Report Datasheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.

▪ Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.

▪ Configuration Modes – Understand various configuration modes andselect the suitable mode for a design.

▪ Dynamic Power Estimation Using Vivado Report Power – Use anSAIF (switching activity interface format) file to determine accuratepower consumption for a design.

▪ Debug Flow in an IP Integrator Block Design – Insert the debug coresinto IP integrator block designs.

▪ Remote Debugging Using the Vivado Logic Analyzer – Use the Vivadologic analyzer to configure an FPGA, set up triggering, and view thesampled data from a remote location.

▪ JTAG to AXI Master Core – Use this debug core to write/read datato/from a peripheral connected to an AXI interface in a system that isrunning in hardware.

▪ Trigger Using the Trigger State Machine in the Vivado Logic Analyzer– Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.

▪ Manipulating Design Properties Using Tcl – Query your design andmake pin assignments by using various Tcl commands.

34











35





Course Description This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.

Level – FPGA 4


Price –


Who Should Attend? – Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Prerequisites



▪ At least six months of design experience with Xilinx tools and FPGAs

Software Tools


Hardware

▪ Architecture: UltraScale™ and 7 series FPGAs*


* This course focuses on the UltraScale and 7 series architectures. Checkwith your local Authorized Training Provider for specifics or othercustomizations.


▪ Apply appropriate I/O timing constraints and design modifications forsource-synchronous and system-synchronous interfaces

▪ Analyze a timing report to identify how to center the clock in the dataeye

▪ Use Tcl scripting in non-project batch flows to synthesize, implement,and generate custom timing reports

▪ Utilize floorplanning techniques to improve design performance

▪ Employ advanced implementation options, such as incrementalcompile flow, physical optimization techniques, and re-entrant modeas last mile strategies

▪ Utilize Xilinx security features, bitstream encryption, andauthentication using AES for design and IP security

▪ Identify advanced FPGA configurations, such as daisy chains andgangs, for configuring multiple FPGAs in a design

▪ Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset


▪ UltraFast Design Methodology Introduction {Lecture}

▪ Scripting in Vivado Design Suite Non-Project Mode {Lecture, Lab}

▪ Using Procedures and Lists in Tcl Scripting {Lecture}

▪ Using regexp in Tcl Scripting {Lecture, Lab}

▪ Introduction to the Xilinx Tcl Store {Lecture, Demo}

▪ Debugging and Error Management in Tcl Scripting {Lecture}

▪ I/O Timing Scenarios {Lecture}

▪ Source-Synchronous I/O Timing {Lecture, Lab}

▪ System-Synchronous I/O Timing {Lecture, Demo}

▪ Timing Constraints Priority {Lecture}

▪ Case Analysis {Lecture}

▪ Daisy Chains and Gangs in Configuration {Lecture}

▪ Managing Remote IP {Lecture, Lab}

Day 2

▪ Introduction to Floorplanning {Lecture}

▪ Design Analysis and Floorplanning {Lecture, Lab}

▪ Incremental Compile Flow {Lecture, Lab}

▪ Re-entrant Implementation Mode {Lecture, Lab}

▪ Physical Optimization {Lecture, Lab}

▪ Vivado Design Suite ECO Flow {Lecture, Lab}

▪ Trigger and Debug at Device Startup {Lecture, Demo}

▪ Scripting for a VLA Design {Lecture, Lab}

▪ Vivado Design Suite Debug Methodology {Lecture}

▪ Power Management Techniques {Lecture}

▪ Bitstream Security {Lecture, Lab}


▪ UltraFast Design Methodology Introduction – Introduces theUltraFast™ design methodology guidelines covered in this course.

▪ Scripting in Vivado Design Suite Non-Project Mode – Write Tclcommands in the non-project batch flow for a design.

▪ Using Procedures and Lists in Tcl Scripting – Employ procedures and lists in Tcl scripting.

▪ Using regexp in Tcl Scripting – Use regular expressions to find apattern in a text file while scripting an action in the Vivado Design Suite.

▪ Introduction to the Xilinx Tcl Store – Introduces the Xilinx Tcl Store.

▪ Debugging and Error Management in Tcl Scripting - Understand how to debug errors in a Tcl script.

▪ I/O Timing Scenarios – Overview of various I/O timing scenarios, suchas source- and system-synchronous, direct/MMCM capture, andedge/center aligned data.

▪ Source-Synchronous I/O Timing – Apply I/O delay constraints andperform static timing analysis for a source-synchronous, double datarate (DDR) interface.

▪ System-Synchronous I/O Timing – Apply I/O delay constraints andperform static timing analysis for a system-synchronous inputinterface.

▪ Timing Constraints Priority – Identify the priority of timing constraints.

▪ Case Analysis – Understand how to analyze timing when usingmultiplexed clocks in a design.

▪ Daisy Chains and Gangs in Configuration – Introduces advancedconfiguration schemes for multiple FPGAs.

▪ Managing Remote IP – Store IP and related files remote to the currentworking project directory.

Day 2

▪ Introduction to Floorplanning – Introduction to floorplanning and how to use Pblocks while floorplanning.

▪ Design Analysis and Floorplanning – Explore the pre- and post-implementation design analysis features of the Vivado IDE.

▪ Incremental Compile Flow – Utilize the incremental compile flow whenmaking last-minute RTL changes.

▪ Re-entrant Implementation Mode – Use re-entrant mode on partial routed nets.

▪ Physical Optimization – Use physical optimization techniques for timing closure.

▪ Vivado Design Suite ECO Flow – Use ECO flow to make changes to apreviously implemented design and apply changes to the original design.

36





▪ Trigger and Debug at Device Startup – Debug the events around the device startup.

▪ Scripting for a VLA Design – Use Tcl scripting for VLA designs foradding probes and making connections to probes.

▪ Vivado Design Suite Debug Methodology – Understand and follow thedebug core recommendations. Employ the debug methodology fordebugging a design using the Vivado logic analyzer.

▪ Power Management Techniques – Identify techniques used for low power design.

▪ Bitstream Security – Understand the Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication.







37


Designing with the UltraScale Architecture FPGA 3

FPGA-US-ILT (v1.0) Course Specification

FPGA-US-ILT (v1.0) updated November 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ architecture. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Level – FPGA 3


Price –

Course Part Number – FPGA-US-ILT

Who Should Attend? – Anyone who would like to build a design for the UltraScale device family

Prerequisites

▪ Completion of the Essentials of FPGA Design course and Vivado Design Suite STA and Xilinx Design Constraints course

▪ OR completion of the Vivado Design Suite Advanced XDC and StaticTiming Analysis for ISE Software Users course

Software Tools


Hardware

▪ Architecture: UltraScale FPGAs*

▪ Demo board: None*

* This course focuses on the UltraScale architecture. Check with your localAuthorized Training Provider for specifics or other customizations.


▪ Take advantage of the primary UltraScale architecture resources

▪ Describe the new CLB capabilities and the impact that they make onyour HDL coding style

▪ Define the block RAM, FIFO, and DSP resources available

▪ Properly design for the I/O and SERDES resources

▪ Identify the MMCM, PLL, and clock routing resources included

▪ Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces

▪ Describe the additional features of the dedicated transceivers

▪ Effectively migrate your IP and design to the UltraScale architecture as quickly as possible


▪ UltraScale Architecture Overview

▪ Design Migration Software Recommendations

▪ CLB Architecture and HDL Coding Styles

▪ Lab 1: Optimal Coding Styles for CLB Resources

▪ Clocking Resources

▪ Lab 2: Clocking Migration

▪ Lab 3: Clocking Resources

▪ Memory and DSP Resources

▪ Lab 4: DDR3 MIG Design Migration

▪ Lab 5: DDR4 MIG Design Creation

Day 2

▪ I/O Resources

▪ Lab 6: Component Mode IO

▪ FPGA Design Migration

▪ Design Migration Case Study

▪ Lab 7: QSGMII Design Migration

▪ Lab 8: 10G PCS/PMA and MAC Design Migration

▪ Demo: Transceiver Wizard

▪ Transceiver Overview

▪ Lab 9: Transceiver Core Resources

Lab Descriptions ▪ Lab 1: Optimal Coding Styles for CLB Resources – Analyze a design

that has asynchronous resets by generating various reports such asthe Timing Summary report and Utilization report. Convert theasynchronous resets to synchronous resets by removing the resetsignal from the sensitivity list. Also examine the CLB resources, suchas the LUT and the dedicated carry chain.

▪ Lab 2: Clocking Migration – Migrate a 7 series design to theUltraScale architecture with a focus on clocking resources.

▪ Lab 3: Clocking Resources –Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.

▪ Lab 4: DDR3 MIG Design Migration – Migrate a 7 series MIG design to the UltraScale architecture. The provided MIG design was targetedto a Kintex® UltraScale device (KC705 evaluation board) with DDR3memory on board. In this case, the design will be migrated to use an UltraScale DDR3 memory interface.

▪ Lab 5: DDR4 MIG Design Creation – Create a DDR4 memorycontroller with the Memory Interface Generator (MIG) utility.

▪ Lab 6: Component Mode I/O– Implement a high-performance, source-synchronous interface using the UltraScale architecture SelectIO in Component mode.

▪ Lab 7: QSGMII Design Migration – Migrate an existing 7 seriesQSGMII example design to a Kintex UltraScale architecture-baseddevice. This lab will show you how to update your port connectionsand use the optimum logic resources available.

▪ Lab 8: 10G PCS/PMA and MAC Design Migration – Migrate asuccessfully implemented 7 series design containing 10G EthernetMAC and 10G PCS/PMA IP to an UltraScale FPGA.

▪ Lab 9: Transceiver Core Resources – Use the Transceiver Wizard to build a design that uses a single serial transceiver and observe the file structures created.





38


Designing with the UltraScale Architecture FPGA 3

FPGA-US-ILT (v1.0) Course Specification

FPGA-US-ILT (v1.0) updated November 2015 www.xilinx.com Course Specification 1-800-255-7778



39


Embedded Systems Design

Embedded Hardware 3

EMBD-HW-ILT (v1.0) Course Specification

EMBD-HW-ILT (v1.0) updated May 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado® Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze™ soft processor are covered in lectures and labs, in addition to general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.

The Xilinx Zynq All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

Level – Embedded Hardware 3


Price –

Course Part Number – EMBD-HW-ILT

Who Should Attend? – Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC or MicroBlaze soft processor core

Prerequisites

▪ FPGA design experience

▪ Completion of the Essentials of FPGA Design course or equivalentknowledge of Xilinx Vivado® software implementation tools

▪ Basic understanding of C programming

▪ Basic understanding of microprocessors

▪ Some HDL modeling experience

Software Tools


Hardware

▪ Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*

▪ Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard or Kintex®-7 FPGA KC705 board*

* This course focuses on the Zynq All Programmable SoC and 7 seriesFPGA architectures. Check with your local Authorized Training Provider forthe specifics of the in-class lab board or other customizations.


▪ Describe the various tools that encompass a Xilinx embedded design

▪ Rapidly architect an embedded system containing a MicroBlaze™ orCortex™-A9 processor using the Vivado IP Integrator andCustomization Wizard

▪ Develop software applications utilizing the Eclipse-based SoftwareDevelopment Kit (SDK)

▪ Create and integrate an IP-based processing system component in the Vivado Design Suite

▪ Design and add a custom AXI interface-based peripheral to theembedded processing system

▪ Simulate a custom AXI interface-based peripheral using a busfunctional model (BFM)


▪ Embedded Design Overview

▪ IP Integrator and the PS Configuration Wizard

▪ Lab 1: Hardware Construction Using the Vivado IP Integrator

▪ Software Development Using SDK

▪ Lab 2: Adding and Downloading Software

▪ Introduction to AXI

▪ Interrupts

▪ Adding Hardware to an Embedded System

▪ Lab 3: Adding IP to a Hardware Design

Day 2

▪ Designing a Custom AXI Peripheral

▪ Using the Create and Package IP Wizard to Build a Custom AXIPeripheral

▪ Lab 4: Building Custom AXI IP for an Embedded System

▪ Bus Functional Model Simulation

▪ Lab 5: BFM Simulation – AXI Peripheral

▪ MicroBlaze Processor Basics

▪ Zynq All Programmable SoC Processor Basics

▪ Lab 6: Testing Custom AXI IP on Hardware

▪ Managing Embedded System Design Projects

▪ Lab 7: Integrating a Custom Peripheral

Lab Descriptions ▪ Lab 1: Hardware Construction Using the Vivado IP Integrator – Create

a project using the IP integrator to develop a basic hardware systemand generate a series of netlists for the embedded design.

▪ Lab 2: Adding and Downloading Software – Continuing from a completed hardware system, begin software development using theSDK tools to create a software BSP and sample application.Download and run the application.

▪ Lab 3: Adding IP to a Hardware Design – Add IP to an existingprocessing system. Configure the device and download the application.

▪ Lab 4: Building Custom AXI IP for an Embedded System – Add a custom AXI peripheral to the Vivado IP catalog using the Create and Package IP Wizard.

▪ Lab 5: BFM Simulation – AXI Peripheral – Test custom IP via busfunctional model (BFM) simulation.

▪ Lab 6: Testing Custom AXI IP on Hardware – Use debug cores and the Vivado hardware manager to test custom IP.

▪ Lab 7: Integrating a Custom Peripheral – Add the custom IP created in Lab 4 to an existing processor system.






Japan, contact your training provider at www.xilinx.com/training/atp.htm#JP, or send your inquiries to [email protected], or call +81-3-6744-7970.

40


Embedded Design with PetaLinux Tools Embedded Software 4

EMBD-PLNX-ILT (v1.0) Course Specification

EMBD-PLNX-ILT (v1.0) updated August 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded Linux system targeting a Zynq® All Programmable System on a Chip (SoC) processor development board using PetaLinux Tools. The course offers students hands-on experience with building the environment and booting the system using a Zynq All Programmable SoC design with PetaLinux Tools on the ARM® Cortex™-A9 processor.

This course also introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.

Level – Embedded Software 4

Price –


Course Part Number – EMBD-PLNX-ILT

Who Should Attend? – Embedded software developers interested in customizing the PetaLinux kernel on an ARM processor design for a Xilinx Zynq All Programmable SoC

Prerequisites

▪ Essentials of FPGA Design (introductory FPGA design course)

▪ Embedded Systems Software Development course (softwaredevelopment for FPGA embedded systems course)

Software Tools

▪ Vivado® Design or System Edition 2015.2

▪ PetaLinux Tools 2015.2

Hardware

▪ Architecture: Zynq-7000 All Programmable SoC*

▪ Demo board: ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoCarchitecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Explain what an embedded Linux kernel is

▪ Describe the Linux device driver architecture

▪ Create a PetaLinux project to configure and build an image using PetaLinux tools

▪ Create a working ARM Cortex-A9 MPCore Linux system using theVivado Design Suite and PetaLinux tools

▪ List various hardware interfacing options available for the ARMCortex-A9 MPCore

▪ Build custom hardware cores and device drivers using the user spaceI/O (UIO) framework


▪ Embedded Linux Overview

▪ Lab 1: A First Look

▪ Introduction to the PetaLinux Tools

▪ Lab 2: Build and Boot an Image

▪ Application Development and Debugging

▪ Lab 3: Application Development and Debugging

▪ Networking and TCP/IP

▪ Lab 4: Networking and TCP/IP

▪ Device Drivers, User Space I/O, and Loadable Modules

▪ Lab 5: Accessing Hardware Devices from User Space

Day 2

▪ Board Bring Up with the Vivado Design Suite and PetaLinux Tools

▪ Lab 6: Basic Hardware Design with the Vivado Design Suite andPetaLinux Tools

▪ Custom Hardware Development and Interfacing

▪ Lab 7: Custom Hardware Development

▪ Custom Driver Development (quick review)

▪ Lab 8: Custom Driver Development

Lab Descriptions ▪ Lab 1: A First Look – Log in to the ARM processor Linux system and

make comparisons between the embedded Linux and desktop Linuxenvironments.

▪ Lab 2: Build and Boot an Image – Explore the Linux configuration menus and build the ARM processor Linux kernel and applications.Download the resulting system image to the development board.

▪ Lab 3: Application Development and Debugging – Create a simple user application with PetaLinux Tools and debug the application withSystem Debugger.

▪ Lab 4: Networking and TCP/IP – Explore the kernel configuration menu. Log in to the ARM processor Linux system by using telnet.Transfer files to and from Linux by using FTP. Build and experimentwith web-based applications under Linux.

▪ Lab 5: Accessing Hardware Devices from User Space – Access ahardware device directly from user space. Use the UIO framework to access a hardware device. Experience loading and unloading kernel modules.

▪ Lab 6: Basic Hardware Design with the Vivado Design Suite andPetaLinux Tools – Use the Vivado IP integrator (IPI) to create a basichardware design with the ARM Cortex-A9 MPCore. Use PetaLinuxTools to create a new embedded Linux target for the hardware design.

▪ Lab 7: Custom Hardware Development – Design a customized IP core. Integrate the IP core with the AXI interface and debug.

▪ Lab 8: Custom Driver Development – Write a UIO program to accessthe PWM AXI IP core. Boot from Flash and verify it on the targetboard.







41


Embedded Systems Software Design

Embedded Software 3

EMBD-SW-ILT (v1.0) Course Specification

EMBD-SW-ILT (v1.0) updated May 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This two-day course introduces you to software design and development for the Xilinx Zynq® All Programmable System on a Chip (SoC) using the Xilinx Software Development Kit (SDK). You will learn the concepts, tools, and techniques required for the software phase of the design cycle.

Topics are comprehensive, covering the design and implementation of the board support package (BSP) for resource access and management of the Xilinx Standalone library. Major topics include device driver use, user application debugging and integration. Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. You will have enough practical information to start developing software applications for the ARM® Cortex™-A9 and MicroBlaze™ processors.

Additionally, this course covers developing software applications for a Xilinx embedded system based on a MicroBlaze processor.



Price –

Course Part Number – EMBD-SW-ILT

Who Should Attend? Software design engineers interested in system design and implementation and software application development and debugging using the Xilinx Standalone library

Prerequisites

▪ C or C++ programming experience, including general debugging techniques

▪ Conceptual understanding of embedded processing systems including device drivers, interrupt routines, writing / modifying scripts, userapplications, and boot loader operation

Software Tools


Hardware

▪ Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*

▪ Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard or Kintex®-7 FPGA KC705 board*

* This course focuses on the Zynq All Programmable SoC and 7 seriesFPGA architectures. Check with your local Authorized Training Provider forthe specifics of the in-class lab board or other customizations.


▪ Implement an effective software design environment for a Xilinx embedded system using the Xilinx SDK tools

▪ Write a basic user application (under Standalone or Linux) using theXilinx Software Development Kit (SDK) and run it on an embedded system platform

▪ Use Xilinx debugger tools to troubleshoot user applications

▪ Apply software techniques to improve operability

▪ Maintain and update software projects with changing hardware


▪ Processors, Peripherals, and Tools

▪ Standalone Software Platform Development

▪ Lab 1: Basic System Implementation

▪ Linux Software Application Development

▪ Linux Lab 1: Running a Linux Application on the Zynq All Programmable SoC

▪ Software Development Using SDK

▪ Writing Code in the Xilinx Standalone Environment

▪ Lab 2: Linker Script

▪ Writing Code in the Xilinx Linux Environment

▪ Lab 3: Application Development

▪ Demo: SDK Batch Mode

▪ Linux Lab 2: Linux Application Development

▪ Address Management

▪ Interrupts

▪ Lab 4: Software Interrupts

Day 2

▪ Software Platform Download and Boot

▪ Application Debugging

▪ Lab 5: Debugging

▪ Linux Lab 3: Linux Debugging

▪ Application Profiling

▪ Lab 6: SDK Profiling

▪ Linux Lab 4: Linux SDK Profiling

▪ Writing a Custom Device Driver

▪ Lab 7: Writing a Device Driver

▪ Advanced Services and Operating Systems

▪ Project Management with the Xilinx Design Tools

▪ Lab 8: File Systems

Lab Descriptions Standalone

▪ Lab 1: Basic System Implementation – Construct the hardware and software platforms used for the course labs. Begin with Vivado IP Integrator to create the hardware design for the Zynq AllProgrammable SoC or MicroBlaze processor. Specify a basic softwareplatform and add a software application to the system.

▪ Lab 2: Linker Script – Configure the linker script and observeincreased performance when utilizing different memory sections.

▪ Lab 3: Application Development – Create a simple softwareapplication project with the provided source files for a softwareloop-based stopwatch. Verify proper BSP settings and linker scriptgeneration. Use API documentation for the GPIO peripheral tocomplete the software application. Verify proper operation of the stopwatch in hardware.

▪ Lab 4: Software Interrupts – Replace a software timing loop with an interrupt-driven timer. Add the timer software and implement aninterrupt handler for the timer. Download into hardware and test theapplication.

▪ Lab 5: Debugging – Launch the SDK debug perspective and the previous lab’s stopwatch application for debugging, settingbreakpoints, calculating interrupt latency, and stepping through the program’s operation.

▪ Lab 6: SDK Profiling – Profile a program, interpret reports, and verifythe performance with multiple calls.

▪ Lab 7: Writing a Device Driver – Create the skeleton driver framework, add an LCD device driver to the BSP, and verify proper device driver operation via a download to hardware test.

▪ Lab 8: File Systems – Implement a standalone software platform thatincorporates the XilMFS memory file system. Develop an applicationthat performs file-related tasks on external memory.

Linux

▪ Lab 1: Running a Linux Application on the Zynq All ProgrammableSoC – Create a simple hello_world application using the SDK. Theevaluation board will automatically boot from an SD card with the Linux kernel installed as part of the boot image.

42


Embedded Systems Software Design

Embedded Software 3

EMBD-SW-ILT (v1.0) Course Specification

EMBD-SW-ILT (v1.0) updated May 2015 www.xilinx.com Course Specification 1-800-255-7778

▪ Lab 2: Linux Application Development – Access the general-purpose input/output (GPIO) that is connected to the evaluation board.

▪ Lab 3: Linux Debugging – Use the SDK software debugger. Theapplication accessing the GPIO created in the "Linux ApplicationDevelopment" lab will be set up for debugging and observations willbe made using the debugger’s features.

▪ Lab 4: Linux SDK Profiling – Profile a program, interpret reports, andverify performance with multiple function calls.


Visit www.xilinx.com/training and click on the region where you want to

attend a course.





43


Embedded C/C++ SDSoC Development Environment and Methodology Embedded 1 and Embedded 2

EMBD-SDSOC-ILT (v1.0) Course Specification

EMBD-SDSOC-ILT (v1.0) updated March 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This one-day course is structured to help designers new to the SDSoC™ development environment to quickly create accelerated systems. The focus is on utilizing the tools to accelerate an existing design at the system architecture level, not on the optimization of the accelerator microarchitectures.

Several optional modules are provided to quickly provide students with the necessary background on both hardware and software. The first half of this class is Level 1 while the afternoon's topics are at Level 2.

Level – Embedded 1 (morning), Embedded 2 (afternoon)

Course Duration – 1 day

Price –

Course Part Number – EMBD-SDSOC-ILT

Who Should Attend? – Anyone interested in quickly adding hardware acceleration to a software system.

Prerequisites

▪ Understanding of Zynq®-7000 architecture (with emphasis onACP, HP ports, and internal routing)

▪ Comfort with the C programming language

▪ Familiarity with the Vivado® Design Suite, Vivado HLS tool, andXilinx SDK

Software Tools

▪ SDSoC development environment 2015.4

Hardware


▪ Demo board: Zynq-7000 All Programmable SoC ZC702 orZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC.Check with your local Authorized Training Provider for the specifics ofthe in-class lab board or other customizations.


▪ Identify candidate functions for hardware acceleration by usingthe TCF profiling tool

▪ Use the System Debugger's capabilities to control the executionflow and examine memory and variables during a debug session

▪ Move designated software functions to hardware and estimate theperformance of the accelerator and the effect on the entire system

▪ Override tool defaults to improve the performance of the individualaccelerators and the overall system

Course Outline ▪ Course Introduction

▪ Zynq AP SoC Architecture Support for Accelerators [Optional]

▪ Software Overview [Optional]

▪ SDSoC Tool Overview {Lecture, Demos, Lab}

▪ SDSoC Design Best Practices {Lecture, Demo}

▪ Profiling {Lecture, Demo, Lab}

▪ Debugging {Lecture, Demo, Lab}

▪ Understanding Estimations {Lecture, Demo, Lab}

▪ Blocking vs. Non-Blocking Implementations {Lecture, Lab}

▪ Multiple Accelerators {Lecture, Lab}

Topic Descriptions ▪ Zynq AP SoC Architecture Support for Accelerators [Optional] –

Discusses the relevant aspects of the Zynq All ProgrammableSoC architecture for accelerator design. The focus is on AXI portsand protocols, system latency, and memory utilization.

▪ Software Overview [Optional] – Provides a thoroughunderstanding of how the integrated design environment works,including how the compiler and linker behave, basics of makefiles,DMA usage, and variable scope.

▪ SDSoC Tool Overview {Lecture, Demos, Lab} – Introduces thepurpose, underlying structures, and basic functionality of theSDSoC development environment through a combination oflecture and demonstration. Student will cement their knowledgewith a lab that reinforces the concepts provided in the lecture anddemo.

▪ SDSoC Design Best Practices {Lecture, Demo} – Illustratescommon mistakes and how to avoid them. Also describesapproaches to refactoring software for hardware acceleration.

▪ Profiling {Lecture, Demo, Lab} – Profiling is the process thatidentifies how the processor is spending its time. Throughprofiling, the user can quickly identify which functions must beoptimized or moved to hardware to satisfy the performancerequirements.

▪ Debugging {Lecture, Demo, Lab} – Through the use of theSystem Debugger, students will learn how to follow the controlflow in an executing application and see the effects of the code onmemory to successfully debug software issues.

▪ Understanding Estimations {Lecture, Demo, Lab} – Once afunction is moved to hardware, questions remain: Will theaccelerator fit in hardware? Will it fun fast enough? Estimationscan provide the answers.

▪ Blocking vs. Non-Blocking Implementations {Lecture, Lab} –Addresses how the processor behaves while the accelerator isproducing solutions—does it wait or continue on?

▪ Multiple Accelerators {Lecture, Lab} – There are times whenmoving a single function to hardware is not enough—multiplefunctions must be moved to hardware, or one accelerator must beduplicated. Here students will learn to control how the toolproduces the accelerators.







44


Zynq UltraScale+ MPSoC for the System Architect Embedded System Architect 3

EMBD-ZUPSA-ILT (v1.0) Course Specification

EMBD-ZUPSA-ILT (v1.0) updated February 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.

Level – Embedded System Architect 3


Price –

Course Part Number – EMBD-ZUPSA-ILT

Who Should Attend? – System architects interested in understanding the capabilities and ecosystem of the Zynq UltraScale+ MPSoC device.

Prerequisites

▪ Suggested: Understanding of the Zynq-7000 architecture

▪ Familiarity with embedded operating systems

Software Tools

▪ Vivado® Design Suite 2015.4○ May require special Zynq UltraScale+ MPSoC family license

▪ Hardware emulation environment:○ VirtualBox○ QEMU○ Ubuntu desktop○ PetaLinux

Hardware

▪ Host computer for running the above software*

* This course focuses on the Zynq UltraScale+ MPSoC architecture.Check with your local Authorized Training Provider for the specifics ofthe in-class lab environment or other customizations. The 2015.4version of this class does not use a physical board, but rather a localemulation environment and the Vivado Design Suite.


▪ Effectively use power management strategies and leverage thecapabilities of the platform management unit (PMU)

▪ Identify mechanisms to secure and safely run the system

▪ Outline the high-level architecture of the devices

▪ Define the boot sequences appropriate to the needs of the system


▪ Zynq UltraScale+ MPSoC Overview {Lecture}

▪ Zynq UltraScale+ MPSoC HW-SW Virtualization {Lecture, Lab}

▪ Introduction to QEMU {Lecture, Demo, Lab}

▪ Zynq UltraScale+ MPSoC Security and Software Test Library{Lecture}

▪ Zynq UltraScale+ MPSoC System Protection {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Security Features {Lecture, Demo}

Day 2

▪ Zynq UltraScale+ MPSoC Power Management {Lecture, Demo,Lab}

▪ Zynq UltraScale+ MPSoC System Coherency {Lecture}

▪ Zynq UltraScale+ MPSoC DDR and QoS {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Boot and Configuration {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Ecosystem Support {Lecture}


▪ Zynq UltraScale+ MPSoC Overview – Overview of the ZynqUltraScale+ MPSoC device.

▪ Zynq UltraScale+ MPSoC HW-SW Virtualization – Covers thehardware and software elements of virtualization. The labdemonstrate how hypervisors can be used.

▪ Introduction to QEMU – Introduction to the Quick Emulator, whichis the tool used to run software for the Zynq UltraScale+ MPSoCdevice when hardware is not available.

▪ Zynq UltraScale+ MPSoC Security and Software Test Library –Introduction to the purpose and API of the Software Test Library.

▪ Zynq UltraScale+ MPSoC System Protection – Covers all thehardware elements that support the separation of softwaredomains.

▪ Zynq UltraScale+ MPSoC Security Features – Aspects thatimplement tamper resistance and control access to the hardwareand bitstream.

Day 2

▪ Zynq UltraScale+ MPSoC Power Management – Overview of thePMU and the power-saving features of the device.

▪ Zynq UltraScale+ MPSoC System Coherency – Learn howinformation is synchronized within the API and through theACE/AXI ports.

▪ Zynq UltraScale+ MPSoC DDR and QoS {Lecture, Demo, Lab} –Understand how DDR can be configured to provide the bestperformance for your system.

▪ Zynq UltraScale+ MPSoC Boot and Configuration – How toimplement the embedded system, including the boot process andboot image creation.

▪ Zynq UltraScale+ MPSoC Ecosystem Support – Overview ofsupported operating systems, software stacks, hypervisors, etc.







45


Zynq UltraScale+ MPSoC for the Software Developer Embedded Software 3

EMBD-ZUPSW-ILT (v1.0) Course Specification

EMBD-ZUPSW-ILT (v1.0) updated February 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This two-day course is structured to provide software developers with a catalog of OS implementation options, including hypervisors, various Linux implementations, booting and configuring a system, and power management for the Zynq® UltraScale+™ MPSoC family.



Price –

Course Part Number – EMBD-ZUPSW-ILT

Who Should Attend? – Software developers interested in understanding the

OS and other capabilities of the Zynq UltraScale+ MPSoC device.

Prerequisites

▪ General understanding of embedded and real-time operating systems

▪ Familiarity with issues related to implementing a complex embeddedsystem

Software Tools

▪ Vivado® Design Suite 2015.4

○ May require special Zynq UltraScale+ MPSoC family license

▪ Hardware emulation environment:

○ VirtualBox

○ QEMU

○ Ubuntu desktop

○ PetaLinux

Hardware


* This course focuses on the Zynq UltraScale+ MPSoC architecture. Checkwith your local Authorized Training Provider for the specifics of the in-classlab environment or other customizations. The 2015.4 version of this classdoes not use a physical board, but rather a local emulation environmentand the Vivado Design Suite.


▪ Distinguish between asymmetric multi-processing (AMP) andsymmetric multi-processing (SMP) environments

▪ Identify situations when the ARM® TrustZone technology and/or a hypervisor should be used

▪ Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)

▪ Define the boot sequences appropriate to the needs of the system

▪ Define the underlying implementation of the application processingunit (APU) and real-time processing unit (RPU) to make best use oftheir capabilities


▪ Zynq UltraScale+ MPSoC Application Processing Unit {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Real-Time Processing Unit {Lecture, Demo,Lab}

▪ ARM TrustZone Technology {Lecture}



▪ Introduction to the Xen Hypervisor {Lecture, Lab} (pairs withOpenAMP, but not SMP)

▪ OpenAMP {Lecture, Lab} (pairs with the Xen Hypervisor, but not SMP)

▪ Symmetric Multi-Processing Linux {Lecture, Demo}

Day 2

▪ Yocto and PetaLinux {Lecture, Demo, Lab}

▪ Open Source Library/PetaLinux Tools {Lecture, Demo, Lab}

▪ Zynq UltraScale+ MPSoC FreeRTOS {Lecture, Demo, Lab}

▪ Zynq UltraScale+ MPSoC Software Stack {Lecture, Demo}

▪ Zynq UltraScale+ MPSoC PMU Development and Debugging {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Power Management {Lecture, Demo, Lab}



▪ Zynq UltraScale+ MPSoC Application Processing Unit – Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.

▪ Zynq UltraScale+ MPSoC Real-Time Processing Unit – Introduction to the various elements within the RPU and different modes ofconfiguration.

▪ ARM TrustZone Technology – Illustrates the use of the ARM® TrustZone technology.

▪ Introduction to QEMU – Introduction to the Quick Emulator, which isthe tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.

▪ Zynq UltraScale+ MPSoC HW-SW Virtualization – Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.

▪ Introduction to the Xen Hypervisor – Description of generichypervisors and discussion of some of the details of implementing ahypervisor using Xen.

▪ OpenAMP – Introduction to the concept of OpenAMP.

▪ Symmetric Multi-Processing Linux – Discussion and examplesshowing how to configure Linux to manage multiple processors.

Day 2

▪ Yocto and PetaLinux – Compares and contrasts the kernel buildingmethods between a "pure" Yocto build and the PetaLinux build (whichuses Yocto "under-the-hood").

▪ Open Source Library/PetaLinux Tools – Introduction to open-source Linux and the effort and risk-reducing PetaLinux tools.

▪ Zynq UltraScale+ MPSoC FreeRTOS – Overview of FreeRTOS withexamples of how it can be used.

▪ Zynq UltraScale+ MPSoC Software Stack – Introduction to what asoftware stack is and a number of stacks used with the Zynq UltraScale+ MPSoC.

▪ Zynq UltraScale+ MPSoC PMU Development and Debugging – Investigation into the the tools and techniques for debugging a ZynqUltraScale+ MPSoC device.

▪ Zynq UltraScale+ MPSoC Power Management – Overview of the PMU and the power-saving features of the device.

▪ Zynq UltraScale+ MPSoC Boot and Configuration – How to implementthe embedded system, including the boot process and boot imagecreation.





46


Zynq UltraScale+ MPSoC for the Software Developer Embedded Software 3

EMBD-ZUPSW-ILT (v1.0) Course Specification

EMBD-ZUPSW-ILT (v1.0) updated February 2016 www.xilinx.com Course Specification 1-800-255-7778



47


Zynq UltraScale+ MPSoC for the Hardware Designer Embedded Hardware 3

EMBD-ZUPHW-ILT (v1.0) Course Specification

EMBD-ZUPHW-ILT (v1.0) updated February 2016 www.xilinx.com Course Specification 1-800-255-7778

Course Description This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

Level – Embedded Hardware 3


Price –

Course Part Number – EMBD-ZUPHW-ILT

Who Should Attend? – Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

Prerequisites

▪ Suggested: Understanding of the Zynq-7000 architecture

▪ Basic familiarity with embedded software development using C (tosupport testing of specific architectural elements)

Software Tools

▪ Vivado® Design Suite 2015.4○ May require special Zynq UltraScale+ MPSoC family license

▪ Hardware emulation environment:○ VirtualBox○ QEMU○ Ubuntu desktop○ PetaLinux

Hardware


* This course focuses on the Zynq UltraScale+ MPSoC architecture.Check with your local Authorized Training Provider for the specifics ofthe in-class lab environment or other customizations. The 2015.4version of this class does not use a physical board, but rather a localemulation environment and the Vivado Design Suite.


▪ Enumerate the key elements of the application processing unit(APU) and real-time processing unit (RPU)

▪ List the various power domains and how they are controlled

▪ Describe the connectivity between the processing system (PS)and programmable logic (PL)

▪ Utilize QEMU to emulate hardware behavior

Course Outline ▪ Zynq UltraScale+ MPSoC Application Processing Unit {Lecture,

Lab}


▪ Zynq UltraScale+ MPSoC Real-Time Processing Unit {Lecture,Demo, Lab}



▪ Zynq UltraScale+ MPSoC System Protection {Lecture, Lab}

▪ Zynq UltraScale+ MPSoC Clocks and Resets {Lecture, Demo}

▪ Introduction to AXI {Lecture, Demo, Lab}

▪ Zynq UltraScale+ MPSoC PMU Hardware Perspective {Lecture,Lab}

Topic Descriptions ▪ Zynq UltraScale+ MPSoC Application Processing Unit –

Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.

▪ Zynq UltraScale+ MPSoC HW-SW Virtualization – Covers thehardware and software elements of virtualization. The labdemonstrates how hypervisors can be used.

▪ Zynq UltraScale+ MPSoC Real-Time Processing Unit –Introduction to the various elements within the RPU and differentmodes of configuration.

▪ Introduction to QEMU – Introduction to the Quick Emulator, whichis the tool used to run software for the Zynq UltraScale+ MPSoCdevice when hardware is not available.

▪ Zynq UltraScale+ MPSoC Boot and Configuration – How toimplement the embedded system, including the boot process andboot image creation.

▪ Zynq UltraScale+ MPSoC System Protection – Covers all thehardware elements that support the separation of softwaredomains.

▪ Zynq UltraScale+ MPSoC Clocks and Resets – Overview ofclocking and reset, focusing more on capabilities than specificimplementations.

▪ Introduction to AXI – Understanding how the PS and PL connectenables designers to create more efficient systems.

▪ Zynq UltraScale+ MPSoC PMU Hardware Perspective –Overview of the PMU and the power-saving features of thedevice.







48


Zynq All Programmable SoC System Architecture Embedded Architect 3

EMBD-ZSA-ILT (v1.0) Course Specification

EMBD-ZSA-ILT (v1.0) updated May 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description The Xilinx Zynq® All Programmable System on a Chip (SoC) provides a new level of system design capabilities. This course provides system architects with the knowledge to effectively architect a Zynq All Programmable SoC.

This course presents the features and benefits of the Zynq architecture for making decisions on how to best architect a Zynq All Programmable SoC project. It covers the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the connections to the programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq All Programmable SoC.

The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Level – Embedded Architect 3


Price –

Course Part Number – EMBD-ZSA-ILT

Who Should Attend? – System architects who are interested in architecting a

system on a chip using the Zynq All Programmable SoC.

Prerequisites

▪ Digital system architecture design experience

▪ Basic understanding of microprocessor architecture


▪ Basic HDL modeling experience

Software Tools


Hardware


▪ Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check withyour local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)

▪ Relate a user design goal to the function, benefit, and use of the ZynqAll Programmable SoC

▪ Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals

▪ Analyze the tradeoffs and advantages of performing a function insoftware versus PL


▪ Zynq All Programmable SoC Overview

▪ Inside the Application Processor Unit (APU)

▪ Lab 1: Building a Zynq All Programmable SoC Platform

▪ Processor Input/Output Peripherals

▪ Introduction to AXI

▪ Zynq All Programmable SoC PS-PL Interface

▪ Lab 2: Integrating Programmable Logic on the Zynq All Programmable SoC

▪ Zynq All Programmable SoC Booting

▪ Lab 3: Using DMA on the Zynq All Programmable SoC

Day 2

▪ Zynq All Programmable SoC Memory Resources

▪ Meeting Performance Goals

▪ Lab 4: Impact of Port Selection on System Performance

▪ Zynq All Programmable SoC Hardware Design

▪ Zynq All Programmable SoC Software Design

▪ Debugging the Zynq All Programmable SoC

▪ Lab 5: Debugging on the Zynq All Programmable SoC

▪ Zynq All Programmable SoC Tools and Reference Designs

▪ Lab 6: Running and Debugging a Linux Application on the Zynq AllProgrammable SoC

Lab Descriptions ▪ Lab 1: Building a Zynq All Programmable SoC Platform – Examine the

process of using the Vivado IP Integrator tool to create a simple processing system.

▪ Lab 2: Integrating Programmable Logic on the Zynq All ProgrammableSoC – Connect a programmable logic (PL) design to the embedded processing system (PS).

▪ Lab 3: Using DMA on the Zynq All Programmable SoC – Experimentwith effectively using the PS DMA controller to move data betweenDDRx memory and a custom PL peripheral.

▪ Lab 4: Impact of Port Selection on System Performance – Explorebandwidth issues surrounding the use of the Accelerator CoherencyPort (ACP) and the High Performance (HP) ports.

▪ Lab 5: Debugging on the Zynq All Programmable SoC – Evaluate debugging the hardware and software components of a Zynq AllProgrammable SoC design.

▪ Lab 6: Running and Debugging a Linux Application on the Zynq AllProgrammable SoC – Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.






Japan, contact your training provider at www.xilinx.com/training/atp.htm#JP,

or send your inquiries to [email protected], or call +81-3-6744-7970.

49


Zynq All Programmable SoC Accelerators Embedded 2

EMBD ZACCEL (v1.0) Course Specification

EMBD ZACCEL (v1.0) updated March 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description Custom processor accelerators are quickly becoming standard practice for reaching system performance goals. This one-day introduction to the accelerator development flow focuses on how to measure system performance, determine what software functionality should be moved to hardware, how to assemble a custom accelerator using the Vivado® HLS tool, add the custom accelerator to a Zynq® All Programmable SoC design, and finally measure accelerated performance.

Emphasis is placed on the Zynq AP SoC's architectural features that make coupling an accelerator to the multi-processor core a possibility as well as the many techniques for implementing accelerated systems. Discussion of typical tradeoffs that a system architect will likely make is also included. The specifics of the accelerator itself is secondary as the focus is on how to integrate an accelerator rather than accelerator design techniques.

Level – Embedded 2


Price –

Course Part Number – EMBD ZACCEL

Who Should Attend? – System architects who are interested in architecting a system on a chip using the Zynq All Programmable SoC with hardware acceleration.

Prerequisites

▪ Digital system architecture design experience

▪ Basic understanding of microprocessor architecture


▪ Basic understanding of system architecture

Software Tools


▪ Vivado HLS tool

▪ Xilinx SDK

Hardware


▪ Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC. Check withyour local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Identify which system architecture best fits the design needs: data flow or accelerator

▪ Determine if software is meeting behavioral and performance specifications

▪ Profile an existing application to determine which functions are candidates for moving to hardware; design, from the ground up, anappropriately architected accelerator system

▪ Construct an accelerator using the Vivado HLS tool

▪ Assemble an embedded system using the Vivado IP integrator,including the custom accelerator

▪ Architect a memory system and memory access to best support an accelerator architecture

▪ Measure the performance of the complete system, including AXIloading


▪ Introduction and Agenda

▪ Zynq AP SoC Architecture Support for Accelerators

▪ Lab 1: Impact of Port Selection on System Performance

▪ Accelerator Development Process

▪ Lab 2: Measuring Performance and Profiling

▪ Coding Techniques for Accelerators

Day 2

▪ Developing the Accelerator Using HLS

▪ Lab 3: Building a Hardware Accelerator Using the Vivado HLS Tool

▪ Building the Embedded Design Using IPI

▪ Lab 4: Building an Accelerated Embedded System (Accelerator Model)

▪ Memory Concepts

▪ Measuring Embedded System Performance

▪ Lab 5: Measuring Accelerated System Performance

Lab Descriptions ▪ Lab 1: Impact of Port Selection on System Performance – The Zynq

AP SoC has a number of ports. Connecting the accelerator to the wrong one could significantly hamper system performance. This lab explores the balance between loading the AXI ports and processor performance.

▪ Lab 2: Measuring Performance and Profiling – Here you will learn how to measure system performance and determine through profiling which software functions should be moved to hardware in the form ofan accelerator.

▪ Lab 3: Building a Hardware Accelerator Using the Vivado HLS Tool – The Vivado HLS tool is a powerful C/C++ to netlist building tool thatgreatly facilitates converting software functions to hardwareaccelerators.

▪ Lab 4: Building an Accelerated Embedded System (Accelerator Model) – This lab explores how the accelerator can be attached to thePS.

▪ Lab 5: Measuring Accelerated System Performance – Havingcompleted a full build of the accelerated embedded system, you willnow confirm proper behavior and overall system performance.







50


Designing with VHDL

FPGA 1

LANG11000-ILT (v1.0) Course Specification

LANG11000-ILT (v1.0) updated November 2014 www.xilinx.com Course Specification 1-800-255-7778

Course Description This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level – FPGA 1


Price –

Course Part Number – LANG11000-ILT

Who Should Attend? – Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs

Prerequisites

▪ Basic digital design knowledge

Software Tools


Hardware

▪ Architecture: N/A*

▪ Demo board: Kintex®-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check withyour local Authorized Training Provider for the specifics of the in-classlab board or other customizations.


▪ Implement the VHDL portion of coding for synthesis

▪ Identify the differences between behavioral and structural codingstyles

▪ Distinguish coding for synthesis versus coding for simulation

▪ Use scalar and composite data types to represent information

▪ Use concurrent and sequential control structure to regulateinformation flow

▪ Implement common VHDL constructs (Finite State Machines[FSMs], RAM/ROM data structures)

▪ Simulate a basic VHDL design

▪ Write a VHDL testbench and identify simulation-only constructs

▪ Identify and implement coding best practices

▪ Optimize VHDL code to target specific silicon resources within theXilinx FPGA

▪ Create and manage designs within the Vivado Design Suiteenvironment


▪ HDL Design Flow Overview

▪ Hardware Modeling Concepts

▪ VHDL Design Units

▪ Lab 1: Creating Hierarchy

▪ Introduction to Testbenches

▪ Lab 2: Build Testbench, Run Simulation

▪ VHDL Signals & Datatypes

▪ Operators and Expressions

▪ Lab 3: Build RAM / ROM Module

Day 2

▪ Concurrent & Sequential Statements

▪ Lab 4: Build Clock Divider – Address Counter

▪ Controlled Operation Statements, If/else – Case -Loops

▪ Lab 5: Build Binary Counter with Generics

▪ Using VITAL

▪ Lab 6: Running Timing Simulation

▪ Behavioral to RTL Coding

Day 3

▪ Coding FSMs in VHDL

▪ Lab 7: Modify & Test Existing FSM Source Code

▪ Targeting Xilinx FPGAs

▪ Lab 8: Xilinx Tool Flow, Download to Demo Board

▪ VHDL Subprograms, Functions and Procedures

▪ Advanced Process Statements

▪ Lab 9: Simulation with VHDL Text I/O

Lab Descriptions The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.







51


Designing with Verilog

FPGA 1

LANG-VERILOG-ILT (v1.0) Course Specification

LANG-VERILOG-ILT (v1.0) updated November 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Level – FPGA 1


Price –

Course Part Number – LANG-VERILOG-ILT

Who Should Attend? – Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisites

▪ Basic digital design knowledge

Software Tools


Hardware

▪ Architecture: N/A*


* This course does not focus on any particular architecture. Check withyour local Authorized Training Provider for the specifics of the in-classlab board or other customizations.


▪ Write RTL Verilog code for synthesis

▪ Write Verilog test fixtures for simulation

▪ Create a Finite State Machine (FSM) by using Verilog

▪ Target and optimize Xilinx FPGAs by using Verilog

▪ Use enhanced Verilog file I/O capability

▪ Run a timing simulation by using Xilinx Simprim libraries

▪ Create and manage designs within the Vivado Design Suiteenvironment

▪ Download to the evaluation demo board


▪ Hardware Modeling Overview

▪ Verilog Language Concepts

▪ Modules and Ports

▪ Demo: Multiplexer

▪ Lab 1: Building Hierarchy

▪ Introduction to Testbenches

▪ Lab 2: Verilog Simulation and RTL Verification

Day 2

▪ Verilog Operators and Expressions

▪ Continuous Assign Statements

▪ Lab 3: Memory

▪ Verilog Procedural Statements

▪ Lab 4: Clock Divider and Address Counter

▪ Controlled Operation Statements

▪ Lab 5: n-bit Binary Counter and RTL Verification

Day 3

▪ Verilog Tasks and Functions

▪ Advanced Language Concepts

▪ Finite State Machines

▪ Lab 6: Finite State Machines

▪ Targeting Xilinx FPGAs

▪ Lab 7: Implement and Download

▪ Advanced Verilog Testbenches

▪ Lab 8: Using Verilog File I/O

Lab Descriptions The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.







52


C-based Design: High-Level Synthesiswith the Vivado HLS Tool DSP 3

DSP-HLS-ILT (v1.0) Course Specification

DSP-HLS-ILT (v1.0) updated November 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description The course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

Level – DSP 3


Price –

Course Part Number – DSP-HLS-ILT

Who Should Attend? – Software and hardware engineers looking to utilize high-level synthesis

Prerequisites

▪ C, C++, or System C knowledge

▪ High-level synthesis for software engineers OR high-levelsynthesis for hardware engineers

Software Tools

▪ Vivado System Edition 2015.3

Hardware

▪ Architecture: Zynq®-7000 All Programmable SoC and 7 seriesFPGAs*

▪ Demo board: Zynq-7000 All Programmable SoC ZC702 orZedBoard*

* This course focuses on the Zynq-7000 All Programmable SoC and 7series FPGA architectures. Check with your local Authorized TrainingProvider for the specifics of the in-class lab board or othercustomizations.


▪ Enhance productivity using the Vivado HLS tool

▪ Describe the high-level synthesis flow

▪ Use the Vivado HLS tool for a first project

▪ Identify the importance of the testbench

▪ Use directives to improve performance and area and select RTLinterfaces

▪ Identify common coding pitfalls as well as methods for improvingcode for RTL/hardware

▪ Perform system-level integration of IP generated by the VivadoHLS tool

▪ Describe how to use OpenCV functions in the Vivado HLS tool


▪ Introduction to High-Level Synthesis and the Vivado HLS Tool

▪ Using the Vivado HLS Tool: GUI Flow

▪ Demo: Vivado HLS Tool Overview

▪ Lab 1: Introduction to the Vivado HLS Tool Flow

▪ Vivado HLS Tool Command Line Interface

▪ Lab 2: Introduction to the Vivado Tool HLS CLI Flow

▪ Optimizing for Latency

▪ Lab 3: The Impact of Unrolling Loops

▪ Optimizing for Throughput

▪ Lab 4: Optimizing for Throughput

Day 2

▪ Optimizing Arrays

▪ Lab 5: Handling Memories

▪ Optimizing for Area

▪ I/O Interfaces

▪ Demo: AXI4-Streaming Interfaces

▪ Lab 6: System Integration

▪ HLS UltraFast Design Methodology

▪ Vivado HLS Tool: C Code

▪ Lab 7: Matrix Multiplication

Lab Descriptions ▪ Lab 1: Introduction to the Vivado HLS Tool Flow – Utilize the GUI

to simulate and create a project. Perform RTL synthesis,verification, and exporting the C design as an IP.

▪ Lab 2: Introduction to the Vivado HLS Tool CLI Flow – Utilize amake file to perform C simulation. Create a project and perform Csynthesis, RTL verification, and RTL packaging.

▪ Lab 3: The Impact of Unrolling Loops – Analyze multiple results ofthe design and apply directives to optimize loop latency.

▪ Lab 4: Optimizing for Throughput – Optimize loop performanceand modify pipelining and its effect on performance.

▪ Lab 5: Handling Memories – Analyze the impact of manipulatingarrays. Utilize directives to optimize the design for area.

▪ Lab 6: System Integration – Set up an embedded design, createan HLS IP with the AXI Lite interface, import the IP into theembedded design, and validate the system on the demo board.

▪ Lab 7: Matrix Multiplication – Write a C-code 3x3 matrix multiplier,verify the design, and apply directives to improve performance.







53


DSP Design Using System Generator

DSP 3

DSP-SYSGEN-ILT (v1.0) Course Specification

DSP-SYSGEN-ILT (v1.0) updated December 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

Level – DSP 3


Price –

Course Part Number – DSP-SYSGEN-ILT

Who Should Attend? – System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design

Prerequisites

▪ Experience with the MATLAB and Simulink software

▪ Basic understanding of sampling theory

Software Tools

▪ Vivado® System Edition 2015.3

▪ MATLAB with Simulink software R2015b

Hardware

▪ Architecture: 7 series FPGAs*

▪ Demo board: Kintex®-7 FPGA KC705 board and Zynq®-7000 All Programmable SoC ZC702 or ZedBoard*

* This course focuses on the 7 series architectures. Check with your localAuthorized Training Provider for the specifics of the in-class lab board or other customizations. The ZC702 or ZedBoard is required for the "AXI4-Lite Interface Synthesis" lab.


▪ Describe the System Generator design flow for implementing DSPfunctions

▪ Identify Xilinx FPGA capabilities and how to implement a design fromalgorithm concept to hardware simulation

▪ List various low-level and high-level functional blocks available in System Generator

▪ Run hardware co-simulation

▪ Identify the high-level blocks available for FIR and FFT designs

▪ Implement multi-rate systems in System Generator

▪ Integrate System Generator models into the Vivado IDE

▪ Design a processor-controllable interface using System Generator for DSP

▪ Generate IPs from C-based design sources for use in the SystemGenerator environment


▪ Introduction to System Generator

▪ Simulink Software Basics

▪ Lab 1: Using the Simulink Software

▪ Basic Xilinx Design Capture

▪ Demo: System Generator Gateway Blocks

▪ Lab 2: Getting Started with Xilinx System Generator

▪ Signal Routing

▪ Lab 3: Signal Routing

▪ Implementing System Control

▪ Lab 4: Implementing System Control

Day 2

▪ Multi-Rate Systems

▪ Lab 5: Designing a MAC-Based FIR

▪ Filter Design

▪ Lab 6: Designing a FIR Filter Using the FIR Compiler Block

▪ System Generator, Vivado Design Suite, and Vivado HLS Integration

▪ Lab 7: System Generator and Vivado IDE Integration

▪ Kintex-7 FPGA DSP Platforms

▪ Lab 8: System Generator and Vivado HLS Tool Integration

▪ Lab 9: AXI4-Lite Interface Synthesis

Lab Descriptions ▪ Lab 1: Using the Simulink Software – Learn how to use the toolbox

blocks in the Simulink software and design a system. Understand the effect sampling rate.

▪ Lab 2: Getting Started with Xilinx System Generator – Illustrates aDSP48-based design. Perform hardware co-simulation verificationtargeting a Xilinx evaluation board.

▪ Lab 3: Signal Routing – Design padding and unpadding logic by usingsignal routing blocks.

▪ Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.

▪ Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach,design a MAC-based bandpass FIR filter and verify through hardwareco-simulation by using a Xilinx evaluation board.

▪ Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Designa bandpass FIR filter by using the FIR Compiler block to demonstrateincreased productivity. Verify the design through hardwareco-simulation by using a Xilinx evaluation board.

▪ Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.

▪ Lab 8: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.

▪ Lab 9: AXI4-Lite Interface Synthesis – Package a System Generatorfor DSP design with an AXI4-Lite interface and integrate thispackaged IP into a Zynq All Programmable SoC processor system.


Visit www.xilinx.com/training and click on the region where you want to

attend a course.





54


Designing an Integrated PCI Express System Connectivity 3

PCIE28000-ILT (v1.0) Course Specification

PCIE28000-ILT (v1.0) updated December 2014 www.xilinx.com Course Specification 1-800-255-7778

Course Description Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express® core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.

Level – Connectivity 3


Price –

Course Part Number – PCIE28000-ILT

Who Should Attend?

▪ Hardware designers who want to create applications using Xilinx IPcores for PCI Express

▪ Software engineers who want to understand the deeper workings of theXilinx PCI Express solution

▪ System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Prerequisites

▪ Experience with PCIe specification protocol

▪ Knowledge of VHDL or Verilog

▪ Some experience with Xilinx implementation tools

▪ Some experience with a simulation tool, preferably the Vivado® simulator

▪ Moderate digital design experience

Software Tools


Hardware



* This course focuses on the 7 series architecture. Check with your localAuthorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Construct a basic PCIe system by:

○ Selecting the appropriate core for your application

○ Specifying requirements of an endpoint application

○ Connecting this endpoint with the core

○ Utilizing FPGA resources to support the core

○ Simulating the design

▪ Identify the advanced capabilities of the PCIe specification protocol and feature set


▪ Introduction to the PCIe Architecture

▪ Review of the PCIe Protocol

▪ PCIe Core Customization

▪ Lab 1: Constructing the PCIe Core

▪ Simulating a PCIe System Design

▪ Connecting Logic to the Core – AXI Interface

▪ Packet Formatting Details

▪ Lab 2: Downstream Port Model Simulation

Day 2

▪ Endpoint Application Considerations

▪ Lab 3: Pseudo-Transactional Modeling

▪ Application Focus: DMA

▪ Lab 4: Design Implementation

▪ 7 Series Root Port

▪ PCIe Configuration

▪ Compliance and Debugging

▪ Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer**

▪ Interrupts and Error Management

▪ Course Summary

▪ Appendix: Mechanicals, Hot Plug, and Power

▪ Appendix: 7 Series Gen3 PCIe Core Solutions

**Will be available in a future release.

Lab Descriptions ▪ Lab 1: Constructing the PCIe Core – This lab familiarizes you with the

necessary flow for generating a Xilinx Integrated PCI Express Endpointcore from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.

▪ Lab 2: Downstream Port Model Simulation – This lab demonstrateshow timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture the effects of link training and write packets to the endpoint application for later use.

▪ Lab 3: Pseudo-Transactional Modeling – This lab illustratespseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.

▪ Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.

▪ Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer – Thislab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.






Japan, contact your training provider at www.xilinx.com/training/atp.htm#JP,

or send your inquiries to [email protected], or call +81-3-6744-7970.

55


Designing with Multi-Gigabit Serial I/O

Connectivity 3

CONN-MGT-ILT (v1.0) Course Specification

CONN-MGT-ILT (v1.0) updated June 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the 7 Series FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.



Price –

Course Part Number – CONN-MGT-ILT

Who Should Attend? – FPGA designers and logic designers

Prerequisites

▪ Verilog or VHDL experience (or the Designing with Verilog or the Designing with VHDL course)

▪ Familiarity with logic design (state machines and synchronous design)

▪ Basic knowledge of FPGA architecture and Xilinx implementation tools ishelpful

▪ Familiarity with serial I/O basics and high-speed serial I/O standards isalso helpful

Software Tools

▪ Vivado® System Edition 2015.1

▪ Mentor Graphics QuestaSim simulator 10.3d

Hardware



* This course focuses on the Kintex-7 architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Describe and utilize the ports and attributes of the serial transceivers in the 7 series FPGAs

▪ Effectively utilize the following features of the gigabit transceivers:

○ 8B/10B and other encoding/decoding, comma detection, clockcorrection, and channel bonding

○ Pre-emphasis and linear equalization

▪ Use the 7 Series FPGAs Transceivers Wizard to instantiate GT primitives in a design

▪ Access appropriate reference material for board design issuesinvolving the power supply, reference clocking, and trace design


▪ 7 Series FPGAs Overview

▪ 7 Series FPGAs Transceivers Overview

▪ 7 Series FPGAs Transceivers Clocking and Resets

▪ 8B/10B Encoder and Decoder

▪ Lab 1: 8B/10B Encoding and Bypass

▪ Commas and Deserializer Alignment

▪ Lab 2: Commas and Data Alignment

Day 2

▪ RX Elastic Buffer and Clock Correction

▪ Lab 3: Clock Correction

▪ Channel Bonding

▪ Lab 4: Channel Bonding

▪ Transceiver Wizard Overview

▪ Lab 5: Transceiver Core Generation

▪ Transceiver Simulation

▪ Lab 6: Simulation

▪ Transceiver Implementation

▪ Lab 7: Implementation

▪ Physical Media Attachments

Day 3

▪ 64B/66B Encoding and the Gearbox

▪ Lab 8: 64B/66B Encoding

▪ Transceiver Board Design Considerations

▪ Transceiver Test and Debugging

▪ Lab 9: Transceiver Debugging

▪ Lab 10: IBERT Lab or

▪ Lab 11: System Lab

▪ Transceiver Application Examples

Lab Descriptions ▪ Lab 1: 8B/10B Encoding and Bypass – Utilize the 8B/10B encoder and

decoder and observe running disparity. Learn how to bypass the8B/10B encoder and decoder.

▪ Lab 2: Commas and Data Alignment – Use programmable commadetection to align a serial data stream.

▪ Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.

▪ Lab 4: Channel Bonding – Modify a design to use two transceiversbonded together to form one virtual channel.

▪ Lab 5: Transceiver Core Generation – Use the 7 Series FPGAsTransceivers Wizard to create instantiation templates.

▪ Lab 6: Simulation – Simulate the transceiver IP using the IP exampledesign.

▪ Lab 7: Implementation – Implement the transceiver IP using the IP example design.

▪ Lab 8: 64B/66B Encoding – Generate a 64B/66B transceiver core byusing the 7 Series FPGAs Transceivers Wizard, simulate the design,and analyze the results.

▪ Lab 9: Transceiver Debugging – Debug the transceiver IP using the IPexample design and Vivado debug cores.

▪ Lab 10: IBERT – Create an IBERT design to verify physical links.

▪ Lab 11: System – Perform all design steps from planning the design,generating the core, integrating the core into a design, simulating,implementing and debugging the design, and optimizing the linkparameter using an evaluation board.





62


Designing with Multi-Gigabit Serial I/O

Connectivity 3

CONN-MGT-ILT (v1.0) Course Specification

CONN-MGT-ILT (v1.0) updated June 2015 www.xilinx.com Course Specification 1-800-255-7778



63


How to Design a High-Speed Memory Interface Connectivity 3

CONN-MIF-ILT (v1.0) Course Specification

CONN-MIF-ILT (v1.0) updated July 2015 www.xilinx.com Course Specification 1-800-255-7778

Course Description This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debug using Xilinx 7 series FPGAs.

Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.



Price –

Course Part Number – CONN-MIF-ILT

Who Should Attend? – FPGA designers and logic designers

Prerequisites

▪ VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course

▪ Familiarity with logic design: state machines and synchronous design

▪ Very helpful to have:

○ Basic knowledge of FPGA architecture

○ Familiarity with Xilinx implementation tools

▪ Nice to have:

○ Familiarity with I/O basics

○ Familiarity with high-speed I/O standards

Software Tools


▪ Mentor Graphics Questa Advanced Simulator 10.3d

▪ Mentor Graphics HyperLynx SI 9.x

Hardware


▪ Demo board: Kintex-7 FPGA KC705 board*

* This course focuses on the 7 series architecture. Check with your localAuthorized Training Provider for the specifics of the in-class lab board or other customizations.


▪ Identify the FPGA resources required for memory interfaces

▪ Describe different types of memories

▪ Utilize Xilinx tools to generate memory interface designs

▪ Simulate memory interfaces with the Xilinx Vivado simulator

▪ Implement memory interfaces

▪ Identify the board design options for the realization of memoryinterfaces

▪ Test and debug your memory interface design

▪ Run basic memory interface signal integrity simulations


▪ Course Introduction

▪ 7 Series FPGAs Overview

▪ Memory Devices Overview

▪ 7 Series Memory Interface Resources

▪ Memory Controller Details and Signals

▪ MIG Design Generation

▪ Lab 1: MIG Core Generation

▪ MIG Design Simulation

▪ Lab 2: MIG Design Simulation

Day 2

▪ Memory Design Implementation

▪ Lab 3: MIG Design Implementation

▪ Memory Interface Test and Debugging

▪ Lab 4: MIG Design Debugging

▪ MIG in Embedded Designs

▪ Lab 5: MIG in IP Integrator

▪ Memory Interface Board-Level Design

▪ DDR3 PCB Simulation (optional)

▪ Lab 6: DDR3 Signal Integrity Simulation (optional)

Lab Descriptions ▪ Lab 1: MIG Core Generation – Create a DDR3 memory controller

using the Memory Interface Generator (MIG) in the Vivado IP catalog.Customize the soft core memory controller for the board.

▪ Lab 2: MIG Design Simulation – Simulate the memory controllercreated in Lab 1 using the Vivado simulator or Mentor GraphicsQuestaSim simulator.

▪ Lab 3: MIG Design Implementation – Implement the memorycontroller created in the previous labs. Modify constraints, synthesize,implement, create the bitstream, program the FPGA, and check the functionality.

▪ Lab 4: MIG Design Debugging – Debug the memory interface designutilizing the Vivado logic analyzer.

▪ Lab 5: MIG in IP Integrator – Use the block design editor to includethe MIG IP in a given processor design.

▪ Lab 6: DDR3 Signal Integrity Analysis – Learn basic signal analysisoptions to check waveforms and design optimization (optional).







58

Course List and Price Guide

All prices are USD

www.technically-speaking.com

Course Title Code One-Day

Two-Day Three-Day

C-based Design: High-Level Synthesis with theVivado HLS Tool

DSP-HLS-ILT - 1400 -

Designing an Integrated PCI Express System PCIE28000-ILT - 1400 -

Designing FPGAs Using the Vivado Design Suite 1 FPGA-VDES1-ILT




Designing with Multi-Gigabit Serial I/O CONN-MGT-ILT - - 2100

Designing with the UltraScale Architecture FPGA-US-ILT - 1400 -

Designing with Verilog LANG-VERILOG-ILT

- - 2100

Designing with VHDL LANG11000-ILT - - 2100

DSP Design Using System Generator DSP-SYSGEN-ILT - 1400 -

Embedded C/C++ SDSoC Development Environment and Methodology

EMBD-SDSOC-ILT

700 - -

Embedded Design with PetaLinux Tools EMBD-PLNX-ILT - 1400 -

Embedded Systems Design EMBD-HW-ILT - 1400 -

Embedded Systems Software Design EMBD-SW-ILT - 1400 -

Essentials of FPGA Design 101 TSI-FPGA13000-ILT

- 1400 -

How to Design a High-Speed Memory Interface CONN-MIF-ILT - 1400 -

Vivado for Experienced Xilinx Users - 1400 -

Zynq All Programmable SoC Accelerators EMBD ZACCEL 700 - -

Zynq All Programmable SoC System Architecture EMBD-ZSA-ILT - 1400 -

Zynq UltraScale+ MPSoC for the Hardware Designer

EMBD-ZUPHW-ILT

700 - -

Zynq UltraScale+ MPSoC for the Software Developer

EMBD-ZUPSW-ILT

- 1400 -

Zynq UltraScale+ MPSoC for the System Architect EMBD-ZUPSA-ILT - 1400 -

1400

1400

1400

1400

--

-

- -

-

-

-

Policies and

Registration Information

REGISTRATION

Registration may be completed online at

www.technically-speaking.com.

For registration assistance or other course information regarding the Communication and Presentation Skills Workshops, please email [email protected] or call (702) 776-7467.

For custom quotes or onsite training requests for the Communication and Presentation Skills Workshops, please email [email protected] or call (702) 581-4667.

For registration assistance with the Xilinx Technical Courses, please email [email protected] or call (714) 388-7712.

For specific course information, custom quotes, or onsite training requests for Xilinx Technical Courses, please email [email protected] or call (714) 227-8666.

PAYMENT OPTIONS

All Communication and Presentation Skills Workshops may be paid by Credit Card (MC, Visa, AMEX, Discover), PayPal, Check, or Purchase Order at the time of registration.

All Xilinx Technical Courses may be paid by Credit Card (MC, Visa, AMEX, Discover), PayPal, Check, Purchase Order, or Xilinx Training Credits at the time of registration.

TRAVEL INFORMATION

Travel expenses are the sole responsibility of the course participant. For public workshops, participants will be provided with a list of nearby hotels and restaurants, however, Technically Speaking, Inc. does not require nor recommend any specific establishment.

65

PROGRAM TIMES

Unless otherwise stated:

Full-day public workshops begin at 9:00 a.m. Registration begins at 8:30 a.m.

Half-day public workshops begin at either 8:30 a.m. or 1:30 p.m.

Onsite private workshops begin as scheduled by the client.

CANCELLATION POLICY

Should a participant be unable to attend, cancellation fees are assessed as follows:

100% refund for withdrawals 14 or more days before the start of the program.

50% refund for withdrawals 7-13 days before the start of the program.

Refunds are not provided for cancellations/withdrawals less than 7 days in advance of the start of the program, or for those who fail to attend.

Onsite courses held outside of the United States require a 45-day cancellation notice. Public courses held outside of the United States are subject to the same cancellation policy as US Domestic locations.

TRANSFER POLICY

Registration is fully transferrable. If for any reason, the scheduled participant is unable to attend the course, their registration may be transferred to another party without fee or penalty.

COURSE CANCELLATION POLICY

Courses may be cancelled within 14 days of a class start date due to enrollment thresholds or certain other conditions. Such cancellations will result in a full refund to the participant regardless of the date, however, please keep this in mind when making travel arrangements, as travel costs are the participant’s responsibility.

DISPUTES

All claims, disputes, and controversies shall be referred to mediation before, and as a condition precedent to, the initiation of any adjudicative action or proceeding, including arbitration. The parties will be bound by the applicable laws and statutes of the State of Nevada, United States of America.

66

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NOTES:

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empowering message. Partners in business and in life, Eric, the engineer, and Patricia, the business relationship guru, provide a unique co-presented program for technical professionals that is in constant demand. They are one of only a handful of professional speaking teams that present in tandem. According to their clients, they are

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