Course Agenda
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Transcript of Course Agenda
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Course Agenda
DSP Design Flow
Agenda - 2 © 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only
After completing this course, you will be able to:
Objectives
• Describe the different design flows for implementing DSP functions, with a large focus on the System Generator
• Understand the Xilinx FPGA capabilities and know how to implement a design from algorithm concept to hardware simulation
• Perform Hardware in the Loop and HDL co-simulations and improve productivity
Agenda - 3 © 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only
Day 1
• Introduction– Power of Parallelism– Platform FPGA Virtex-II/ Virtex-II Pro Series– Spartan-3 Architecture
• DSP Design Flows in FPGA– Using VHDL– Using the Xilinx CORE Generator– Using the Xilinx System Generator for DSP– Hardware in the Loop Accelerated Verification
Agenda - 4 © 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only
Day 2
• Digital Filtering– Digital Filtering Blocks– Use the FDA Tool in Conjunction
with the Xilinx Blockset• HDL Co-Simulation
– Concept– Supporting Blocks– Co-Simulation Procedure
Agenda - 5 © 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only
Day 2
• Looking Under the Hood– Quantization and Overflow– Hardware Cost– Data Path Management
• Controlling the System– Control Mechanism– Control Blocks
• Multi-rate Systems– Sample Rates– Sample Rate Changing Blocks– Hardware Realization of Sample Rate
Changing Blocks
Agenda - 6 © 2003 Xilinx, Inc. All Rights ReservedFor Academic Use Only
Bonus Material
• Advanced Features– Multiple FPGAs– Multiple System Generator versions – PicoBlaze microcontroller– User IP Library– Parametric Design Techniques