Cost Efficient Gateway Architectures for Deterministic Automotive ...

Cost Efficient Gateway Architecture for Deterministic Automotive Networks

C/AI-Ls | 21.08.2013 | © Robert Bosch GmbH 2013. All rights reserved, also regarding any disposal,

exploitation, reproduction, editing, distribution, as well as in the event of applications for industrial property rights.

Automotive Technology

1

Cost Efficient Gateway Architecture

for Deterministic Automotive Networks

Ethernet & IP TechDay, Sep. 26, 2013

Thomas Hogenmüller

Burkhard Triess






2

Agenda

Overview E/E-Architecture

Hardware Acceleration – Summary Ethernet & IP Techday 2012

ETAS Data Engine (EDE) – Principle of Operation

EDE in Context of OSI Eco-System

Vision – Cost Efficient Gateway Architecture

Demonstrator: CAN Tunneling over Gigabit Ethernet Backbone


Integration of SW from various sources

Swift introduction of innovations

One scalable E/E architecture

Reuse of application SW





3

Driver for E/E Architectures 202x

Automated driving functionalities

Customization/personalization

Powertrain diversification

Market Strategy

Technology

Increasing number of calculation intensive functionalities (Infotainment, ADAS)

Continuously growing variance (e.g. powertrain electrification)

Increasing number of cross domain functionalities

Remote communication / cloud connectivity


4 C/AI-Ls | 21.08.2013 | © Robert Bosch GmbH 2013. All rights reserved, also regarding any disposal,


Bottleneck of Today's E/E Architectures


Communication Bandwidth

Inter-domain and cross-domain

communication bandwidths not

sufficient for future data traffic

Increasing Number of Variants

Many segments, markets and

technologies leading to complex,

and expensive variant handling

External Communication

Lead to higher data traffic and

significant security risks

Extensibility & Flexibility

Future E/E systems need to

allow swift introduction of new

innovations

Computing Power

Serial computing in embedded

systems is hitting the

technological limits





E/E Architecture 202x - Quo vadis?

5





Cost Efficient Gateway Architecture - Today

6

Central Gateway

CPU

Eth

ern

et

Fle

xR

ay

CA

N (

FD

)

Eth

ern

et

Diagnostics

Eth

ern

et

DLC

Security Gateway





Cost Efficient Gateway Architecture - Tomorrow

7

Central Gateway

CPU

Eth

ern

et

Fle

xR

ay

CA

N (

FD

)

Eth

ern

et

Diagnostics

ETAS Data Engine

“Any to any” interface, non-blocking

bridging with low latency and low

jitter

Hardware data-pipeline for high

performance data communication

Offloads the CPU and reduces the

interrupt rates

Supports typical automotive

interfaces: CAN-FD, FlexRay,

Ethernet up to 1 Gbit/s

Configurable, flexible and

extendable by dedicated software and

hardware functionalities

Flashing

Eth

ern

et

DLC

Gateway

Security





8

Cost Efficient Domain Architecture - Today

Eth

ern

et

CPU

Memory GPU / DSP

HW

CPU Switch

Core 1 Core 2

Flashing Data

Extracting Gateway

Ethernet

Fle

xR

ay

Domain Control Unit

Eth

ern

et





9

Cost Efficient Domain Architecture - Tomorrow

Eth

ern

et

CPU

Memory GPU / DSP

HW

CPU Switch

Core 1 Core 2

Flashing Data

Extracting Gateway

Ethernet

Fle

xR

ay

ETAS Data Engine Data

Extracting

Gateway

Flashing

ETAS Data Engine

Hardware data-pipeline for high

performance data communication

Offloads the data processing units

in a Domain Control Unit

Extracts and moves the data payload

in the central memory

Domain Control Unit

Eth

ern

et

10 Public | ETAS/ETH | 2013-09-26 | © ETAS GmbH 2013. All rights reserved, also regarding any disposal, exploitation, reproduction, editing,

distribution, as well as in the event of applications for industrial property rights.


Hardware Acceleration – Summary Ethernet & IP Techday 2012

70 µs (29 Bit Identifier, payload 0 Bytes)

7 µs (total 64 Byte min., payload 46 Bytes)

0.7 µs (total 64 Byte min., payload 46 Bytes)

CAN 1 Mbit/s

Ethernet 100 Mbit/s

Ethernet 1 Gbit/s

− Real Time communication demands low latency, low jitter, high determinism

Cannot be fulfilled by increasing computing performance High computing performance leads to high power consumption

− Low latency communication is achieved by segmentation of data frames

Short data frames lead to high event rates High event rates lead to high interrupt rates, system efficiency decreases

Hardware Acceleration of data handling overcomes the limitations of software solutions




ETAS Data Engine – Principle of Operation (1/3)

CPU

SECURITY Encryption/Decryption

P I P E L I N E

Data Memory

Address Pool

CPU

Ethernet 1

Ethernet 2

CAN 1

CAN 2

CAN 3

FlexRay 1

FlexRay 2

Security

Input Devices

CPU

Ethernet 1

Ethernet 2

CAN 1

CAN 2

CAN 3

FlexRay 1

FlexRay 2

Security

Output Devices

< 5 µs




ETAS Data Engine – Principle of Operation (3/3)

CPU

SECURITY Encryption/Decryption

P I P E L I N E

Data Memory

Address Pool

CPU

Ethernet 1

Ethernet 2

CAN 1

CAN 2

CAN 3

FlexRay 1

FlexRay 2

Security

Input Devices

CPU

Ethernet 1

Ethernet 2

CAN 1

CAN 2

CAN 3

FlexRay 1

FlexRay 2

Security

Output Devices

< 5 µs

1 2 3 4

1

1 2 3 4




Layer 2 – IEEE MAC – Implemented in Hardware on Automotive µC

Ethernet OSI-Ecosystem

1: Physical

2b: Logic Link Control

2a: Media Access Control

4: Transport

3: Network

5: Session

6: Presentation

7: Application

IEEE OSI Cam Multimedia

Real Time Control

IEEE802.1 AVB - 802.1 Qav - 802.1 AS (1588v2)

IEEE1722

IEEE Ethernet MAC

IPv4 (6)

TCP and/or UDP UDP

DoIP SOME/

IP

Bonjour mDNS & DNS SD

DHCP

ICMP

ARP

Diagnosis Flashing

Device Control

Service Discovery

Address Config.

OPENsig IEEE Autosar

Standards in Development at

Middleware supported by AUTOSAR and GENIVI

100 Mbit BroadR-Reach 1 Gbit IEEE802.3bp Next speed grade (2,5…10

GE)

IEEE802.1 TSN - FT Clock - FT Multi Path - Preemption - Burst Limiting

Shaper - Time Aware

Shaper (Scheduled Com.)

IEEE1722a

Implemented on µC-Chips




EDE – High Performance Data Communication up to OSI-Layer 4

Ethernet OSI-Ecosystem – Supported by ETAS Data Engine

1: Physical

2b: Logic Link Control

2a: Media Access Control

4: Transport

3: Network

5: Session

6: Presentation

7: Application

IEEE OSI Cam Multimedia

Real Time Control

IEEE802.1 AVB - 802.1 Qav - 802.1 AS (1588v2)

IEEE1722

IEEE Ethernet MAC

IPv4 (6)

TCP and/or UDP UDP

DoIP SOME/

IP

Bonjour mDNS & DNS SD

DHCP

ICMP

ARP

Diagnosis Flashing

Device Control

Service Discovery

Address Config.

OPENsig IEEE Autosar

Standards in Development at

Middleware supported by AUTOSAR and GENIVI

100 Mbit BroadR-Reach 1 Gbit IEEE802.3bp Next speed grade (2,5…10

GE)

IEEE802.1 TSN - FT Clock - FT Multi Path - Preemption - Burst Limiting

Shaper - Time Aware

Shaper (Scheduled Com.)

IEEE1722a

EDE





15

Vision - Cost Efficient Gateway Architecture

Timeline

Costs

First step: Companion Chip - reduces the risk and enables the market launch

Integration into SoC decreases costs by: Reducing the amount of associate components (Power Supply, Stabilizer, …)

Less PCB surface needed

Reduced Packaging effort

EDE leads to high integrated (cost-efficient) and high performance gateway solutions n*E

thern

et

n*F

lexR

ay

Electronic Control Unit

µC HSM

GTM

µC Companion Chip

Interf.

peripheral

EDE Core

Eth PHYs MAC

µC

CAN FR

CAN BD FR BD

n*C

AN

PCIe

HSM


µC

M-CAN E-Ray

CAN BD FR BD

HSM

MAC

µC Switch

GTM

peripheral

Switch fabric

Eth PHYs MAC xMII

µC

n*E

thern

et

n*F

lexR

ay

n*C

AN


HSM

µC SoC

EDE Core

Eth PHYs MAC

Core 1

CAN FR

CAN BD FR BD

HSM

GTM

peripheral

Core 2

Core 3 Core 4

n*E

thern

et

n*F

lexR

ay

n*C

AN





16






17


23 µs




ETAS Data Engine – Open Market Aspects

ECU-Suppliers (Tier1) Silicon-Suppliers (Tier2) Car Manufacturers (OEM)

OEM1 OEM2 OEM3 OEM4

Supplier 1

Supplier 2

Supplier 3

Supplier 4

Supplier 5

Supplier 1

Supplier 2

Supplier 3

Supplier 4

Supplier 5

Future E/E-Architecture Vehicle Network Design Vehicle Network Visualization

API, Development-,Test-Tools FPGA-Prototypes AUTOSAR, Basic Software Int.

IP-Core VHDL Model Simulation, Test

ETAS Data Engine +

BOSCH-AE

(Tier3)





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for Deterministic Automotive Networks

Ethernet & IP TechDay, Sep. 26, 2013

Thomas Hogenmüller

Burkhard Triess

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Cost Efficient Gateway Architectures for Deterministic Automotive ...

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