Cost-Effective A/D Flash 8-Bit MCU with EEPROM...8-pin SOP (150 il) Outline Di ensions ..... 1 8...

Cost-Effective A/D Flash 8-Bit MCU with EEPROM

HT50F50/HT50F51

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HT50F50/HT50F51Cost-Effective A/D Flash 8-Bit MCU with EEPROM


Table of Contents

Features ............................................................................................................ 6CPU Featu�es ......................................................................................................................... 6Pe�iphe�al Featu�es ................................................................................................................. 6

General Description ......................................................................................... 7Selection Table ................................................................................................. 7Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 8Pin Description ................................................................................................ 9Absolute Maximum Ratings .......................................................................... 12D.C. Characteristics ....................................................................................... 12A.C. Characteristics ....................................................................................... 13ADC Electrical Characteristics ..................................................................... 14LVR Electrical Characteristics ...................................................................... 14LCD Electrical Characteristics ..................................................................... 14Power on Reset Electrical Characteristics .................................................. 15System Architecture ...................................................................................... 15

Clo�king and Pipelining ......................................................................................................... 15P�og�a� Counte� ................................................................................................................... 16Sta�k ..................................................................................................................................... 17A�ith�eti� and Logi� Unit – ALU ........................................................................................... 17

Flash Program Memory ................................................................................. 18St�u�tu�e ................................................................................................................................ 18Spe�ial Ve�to�s ..................................................................................................................... 18Look-up Ta�le ........................................................................................................................ 18Ta�le P�og�a� Exa�ple ........................................................................................................ 19In Ci��uit P�og�a��ing ......................................................................................................... �0On-Chip De�ug Suppo�t – OCDS ......................................................................................... �1

RAM Data Memory ......................................................................................... 21St�u�tu�e ................................................................................................................................ �1Gene�al Pu�pose Data Me�o�y ............................................................................................ �1Spe�ial Pu�pose Data Me�o�y ............................................................................................. ��

Special Function Register Description ........................................................ 24Indi�e�t Add�essing Registe�s – IAR0� IAR1 ......................................................................... ��Me�o�y Pointe�s – MP0� MP1 .............................................................................................. ��Bank Pointe� – BP ................................................................................................................. �5A��u�ulato� – ACC ............................................................................................................... �5P�og�a� Counte� Low Registe� – PCL .................................................................................. �5Look-up Ta�le Registe�s – TBLP� TBLH ................................................................................ �5Status Registe� – STATUS .................................................................................................... �6

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EEPROM Data Memory .................................................................................. 27EEPROM Data Me�o�y St�u�tu�e ........................................................................................ �7EEPROM Registe�s .............................................................................................................. �8Reading Data f�o� the EEPROM ........................................................................................ �9W�iting Data to the EEPROM ................................................................................................ �0W�ite P�ote�tion ..................................................................................................................... �0EEPROM Inte��upt ................................................................................................................ �0P�og�a��ing Conside�ations ................................................................................................ �1

Oscillators ...................................................................................................... 32Os�illato� Ove�view ............................................................................................................... ��System Clock Configurations ................................................................................................ ��Inte�nal RC Os�illato� – HIRC ............................................................................................... ��Inte�nal ��kHz Os�illato� – LIRC ........................................................................................... ��Supple�enta�y Os�illato� ...................................................................................................... ��

Operating Modes and System Clocks ......................................................... 33Syste� Clo�ks ...................................................................................................................... ��Syste� Ope�ation Modes ...................................................................................................... ��Cont�ol Registe� .................................................................................................................... �5Ope�ating Mode Swit�hing .................................................................................................... �7NORMAL Mode to SLOW Mode Swit�hing ........................................................................... �8SLOW Mode to NORMAL Mode Swit�hing .......................................................................... �9Ente�ing the SLEEP0 Mode .................................................................................................. �9Ente�ing the SLEEP1 Mode .................................................................................................. �0Ente�ing the IDLE0 Mode ...................................................................................................... �0Ente�ing the IDLE1 Mode ...................................................................................................... �0Stand�y Cu��ent Conside�ations ........................................................................................... �1Wake-up ................................................................................................................................ �1

Watchdog Timer ............................................................................................. 42Wat�hdog Ti�e� Clo�k Sou��e .............................................................................................. ��Wat�hdog Ti�e� Cont�ol Registe� ......................................................................................... ��Wat�hdog Ti�e� Ope�ation ................................................................................................... ��

Reset and Initialisation .................................................................................. 44Reset Fun�tions .................................................................................................................... �5Reset Initial Conditions ......................................................................................................... �8

Input/Output Ports ......................................................................................... 51Pull-high Resisto�s ................................................................................................................ 5�Po�t A Wake-up ..................................................................................................................... 5�I/O Po�t Cont�ol Registe�s ..................................................................................................... 5�Pin-sha�ed Fun�tions ............................................................................................................ 5�I/O Pin St�u�tu�es .................................................................................................................. 56Syste� Clo�k output pin CLO ............................................................................................... 57P�og�a��ing Conside�ations ................................................................................................ 57

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Timer Modules – TM ...................................................................................... 58Int�odu�tion ........................................................................................................................... 58TM Ope�ation ........................................................................................................................ 58TM Clo�k Sou��e ................................................................................................................... 58TM Inte��upts ......................................................................................................................... 59TM Exte�nal Pins ................................................................................................................... 59TM Input/Output Pin Cont�ol Registe� ................................................................................... 59P�og�a��ing Conside�ations ................................................................................................ 60

Standard Type TM – STM .............................................................................. 61Standa�d TM Ope�ation ......................................................................................................... 61Standa�d Type TM Registe� Des��iption ............................................................................... 6�Standa�d Type TM Ope�ating Modes .................................................................................... 66Co�pa�e Output Mode .......................................................................................................... 66Ti�e�/Counte� Mode ............................................................................................................. 69PWM Output Mode ................................................................................................................ 69Single Pulse Mode ................................................................................................................ 7�Captu�e Input Mode .............................................................................................................. 7�

Periodic Type TM – PTM ................................................................................ 75Pe�iodi� TM Ope�ation .......................................................................................................... 75Pe�iodi� Type TM Registe� Des��iption ................................................................................. 76Pe�iodi� Type TM Ope�ating Modes ...................................................................................... 80Co�pa�e Mat�h Output Mode ............................................................................................... 80Ti�e�/Counte� Mode ............................................................................................................. 8�PWM Output Mode ................................................................................................................ 8�Single Pulse Output Mode .................................................................................................... 85Captu�e Input Mode .............................................................................................................. 87

Analog to Digital Converter .......................................................................... 89A/D Ove�view ........................................................................................................................ 89A/D Conve�te� Registe� Des��iption ...................................................................................... 90A/D Conve�te� Data Registe�s – SADOL� SADOH ................................................................ 90A/D Conve�te� Cont�ol Registe�s – SADC0� SADC1� SADC�� PASR� PBSR ....................... 91A/D Ope�ation ....................................................................................................................... 9�A/D Conve�te� Input Signal ................................................................................................... 95Conve�sion Rate and Ti�ing Diag�a� .................................................................................. 96Su��a�y of A/D Conve�sion Steps ....................................................................................... 97P�og�a��ing Conside�ations ................................................................................................ 98A/D T�ansfe� Fun�tion ........................................................................................................... 98A/D P�og�a��ing Exa�ples ................................................................................................. 99

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Interrupts ...................................................................................................... 101Inte��upt Registe�s ............................................................................................................... 101Inte��upt Ope�ation .............................................................................................................. 106Exte�nal Inte��upt ................................................................................................................. 108Multi-fun�tion Inte��upt ........................................................................................................ 108A/D Conve�te� Inte��upt ....................................................................................................... 108Ti�e Base Inte��upts ........................................................................................................... 109EEPROM Inte��upt ...............................................................................................................110TM Inte��upts ........................................................................................................................110Inte��upt Wake-up Fun�tion ..................................................................................................110P�og�a��ing Conside�ations ...............................................................................................110

SCOM Function for LCD ...............................................................................111LCD ope�ation ......................................................................................................................111LCD Bias Cu��ent Cont�ol ....................................................................................................11�

Application Circuits ......................................................................................113Instruction Set ...............................................................................................114

Int�odu�tion ..........................................................................................................................11�Inst�u�tion Ti�ing .................................................................................................................11�Moving and T�ansfe��ing Data ..............................................................................................11�A�ith�eti� Ope�ations ...........................................................................................................11�Logi�al and Rotate Ope�ation ..............................................................................................115B�an�hes and Cont�ol T�ansfe� ............................................................................................115Bit Ope�ations ......................................................................................................................115Ta�le Read Ope�ations ........................................................................................................115Othe� Ope�ations ..................................................................................................................115

Instruction Set Summary .............................................................................116Ta�le Conventions ................................................................................................................116

Instruction Definition ....................................................................................118Package Information ................................................................................... 127

8-pin SOP (150�il) Outline Di�ensions ............................................................................. 1�816-pin NSOP (150�il) Outline Di�ensions ......................................................................... 1�9�0-pin SSOP (150�il) Outline Di�ensions ......................................................................... 1�0

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Note that 8-pin MCU package types are not marketed in the following countries: USA, UK, Germany, The Netherlands, France and Italy.

Features

CPU Features• OperatingVoltage

♦ fSYS=8MHz:2.2V~5.5V

• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• TwoOscillators♦ InternalRC--HIRC♦ Internal32kHz--LIRC

• Fullyintergratedinternal8MHzoscillatorrequiresnoexternalcomponents

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• Upto4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:1K×14/2K×15

• RAMDataMemory:64×8/96×8

• EEPROMMemory:32×8

• WatchdogTimerfunction

• Upto18bidirectionalI/Olines

• Softwarecontrolled4-SCOMlinesLCDdriverwith1/2bias(onlyavailableforHT50F51)

• Multiplepin-sharedexternalinterrupts

• MultipleTimerModulesfortimemeasure,comparematchoutput,captureinput,PWMoutput,singlepulseoutputfunctions

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• Multi-channel12-bitresolutionA/Dconverter

• Lowvoltageresetfunction

• Widerangeofavailablepackagetypes

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General DescriptionThedevicesareFlashMemorytype8-bithighperformanceRISCarchitecturemicrocontrollers.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures, thesedevicesalsoincludeawide rangeof functionsandfeatures.Othermemory includesanareaofRAMDataMemoryaswellasanareaofEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeatures includeamulti-channel12-bitA/Dconverterfunction.MultipleandextremelyflexibleTimerModulesprovide timing,pulsegeneration,capture input,comparematchoutput,singlepulseoutputandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimerandLowVoltageResetcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

AfullchoiceofHIRCandLIRCoscillator functionsareprovided includinga fully integratedsystemoscillatorwhichrequiresnoexternalcomponentsforitsimplementation.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethatthedeviceswillfindexcellentuseinapplicationssuchaselectronicmetering,environmentalmonitoring,handheldinstruments,householdappliances,electronicallycontrolledtools,motordrivinginadditiontomanyothers.

Selection TableMostfeaturesarecommontoalldevices,themainfeaturedistinguishingthemareProgramMemoryandDatamemorycapacity.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. Program Memory

Data Memory

DataEEPROM I/O A/D

ConverterTimer

ModuleTime Base Stack R-Type

LCD Package

HT50F50 1K×1� 6�×8 ��×8 8 1�-�it×� 10-�it STM×1 � � — 8SOP

HT50F51 �K×15 96×8 ��×8 18 1�-�it×8 10-�it PTM×� � � �SCOM 16NSOP �0SSOP

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Block Diagram

8-bitRISCMCUCore

I/O

TimeBases

Low Voltage Reset

InterruptController

ResetCircuit

12-bit A/DConverter

RAM Data Memory

TimerModules

WatchdogTimer

Internal RCOscillators

Flash Program Memory

EEPROMData

Memory

Flash/EEPROM Programming Circuitry

Note:LCDfunctionisonlyavailableforHT50F51.

Pin Assignment

VDD/AVDD

PB�/PTCK0/AN�PA�/PTCK1/AN�PA5/AN�/VREFPA6/AN5/VREFOPA7/PTP1/AN6PB�/SCOM�/AN7PB�/CLO/SCOM�

VSS/AVSSPC0/SCOM0PC1/SCOM1

PC�/RESPA0/PTP0/ICPDA/OCDSDA

PA1/PTP0IPA�/ICPCK/OCDSCK

PA�/PTP1IPB6/PTP1BPB5/PTP0B

PB0/INT0/AN0PB1/INT1/AN1

�019181716151�1�1�11

1��5678910

16151�1�1�11109

��5678

1VSS/AVSSPC0/SCOM0PC1/SCOM1

PC�/RESPA0/PTP0/ICPDA/OCDSDA

PA1/PTP0IPA�/ICPCK/OCDSCK

PA�/PTP1I

VDD/AVDD

PB�/PTCK0/AN�PA�/PTCK1/AN�PA5/AN�/VREFPA6/AN5/VREFOPA7/PTP1/AN6

PB0/INT0/AN0PB1/INT1/AN1

HT50F508 SOP-A

VDD/AVDDPA6/STP0I/[STCK0] PA5/INT/STP0B/AN�

PA7/[INT]/STCK0/RES/ICPCKVSS/AVSS

PA0/[STP0]/[STP0I]/AN0/ICPDA PA1/[STP0B]/AN1/VREFPA�/[INT]/STP0/AN�/VREFO

8765

1��

HT50F51/HT50V5116 NSOP-A

HT50F51/HT50V5120 SSOP-A

Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.2.AVDD&VDDmeans theVDDandAVDDare thedoublebonding.VSS&AVSSmeans theVSSandAVSSarethedoublebonding.

3.TheOCDSDAandOCDSCKpinsaretheOCDSdedicatedpins

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Pin DescriptionWiththeexceptionofthepowerpinsandsomerelevanttransformercontrolpins,allpinsonthesedevicescanbereferencedby theirPortname,e.g.PA0,PA1etc,whichrefer to thedigital I/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchastheAnalogtoDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

HT50F50Pin Name Function OPT I/T O/T Description

PA0/[STP0]/[STP0I]/AN0/ICPDA

PA0PAWUPAPUPASR

ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up

STP0 PASR — CMOS TM0 (STM) output

STP0I PASRIFS0 ST — TM0 (STM) input

AN0 PASR AN — ADC input �hannel 0 ICPDA — ST CMOS ICP Data Line

PA1/[STP0B]/AN1/VREF

PA1PAWUPAPUPASR


STP0B PASR — CMOS TM0 (STM) inve�ting outputAN1 PASR AN — ADC input �hannel 1

VREF PASR AN — ADC VREF Input

PA�/[INT]/STP0/AN�/VREFO

PA�PAWUPAPUPASR


INT PASRIFS0 ST — Exte�nal inte��upt input

STP0 PASR — CMOS TM0 (STM) outputAN� PASR AN — ADC input �hannel �

VREFO PASR — AN ADC �efe�en�e voltage output

PA�/[INT]PA�

PAWUPAPUPASR



PA� PA� PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and

wake-up

PA5/INT/STP0B/AN�

PA5PAWUPAPUPASR



STP0B PASR — CMOS TM0 (STM) inve�ting outputAN� PASR AN — ADC input �hannel �

PA6/STP0I/[STCK0]

PA6 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and

wake-upSTP0I IFS0 ST — TM0 (STM) inputSTCK0 IFS0 ST — TM0 (STM) �lo�k input

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Pin Name Function OPT I/T O/T Description

PA7/[INT]/STCK0/RES/ICPCK

PA7 PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and

wake-upINT IFS0 ST — Exte�nal inte��upt input

STCK0 IFS0 ST — TM0 (STM) �lo�k inputRES RSTC ST — Exte�nal �eset input

ICPCK — ST CMOS ICP Clo�k LineVDD VDD — PWR — Digital positive powe� supplyAVDD AVDD — PWR — Analog positive powe� supplyVSS VSS — PWR — Digital negative powe� supplyAVSS AVSS — PWR — Analog negative powe� supply

HT50F51Pin Name Function OPT I/T O/T Description

PA0/PTP0/OCDSDA/ICPDA

PA0PAWUPAPUPASR


PTP0 PASR — CMOS PTM0 outputOCDSDA — ST CMOS On Chip De�ug Syste� Data Line (OCDS EV only)

ICPDA — ST CMOS ICP Data Line

PA1/PTP0IPA1 PAWU

PAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up

PTP0I — ST — PTM0 input

PA�/ICPCK/OCDSCK

PA� PAWUPAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and

wake-upICPCK — ST CMOS ICP Clo�k Line

OCDSCK — ST — On Chip De�ug Syste� Clo�k Line (OCDS EV only)

PA�/PTP1IPA� PAWU

PAPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up and wake-up

PTP1I — ST — PTM1 input

PA�/PTCK1/AN�

PA�PAWUPAPUPASR


PTCK1 PASR ST — PTM1 �lo�k inputAN� PASR AN — ADC input �hannel �

PA5/AN�/VREFPA5

PAWUPAPUPASR


AN� PASR AN — ADC input �hannel �VREF PASR AN — ADC VREF Input

PA6/AN5/VREFO

PA6PAWUPAPUPASR


AN5 PASR AN — ADC input �hannel 5VREFO PASR — AN ADC �efe�en�e voltage output

PA7/PTP1/AN6PA7

PAWUPAPUPASR


PTP1 PASR — CMOS PTM1 outputAN6 PASR AN — ADC input �hannel 6

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Pin Name Function OPT I/T O/T Description

PB0/INT0/AN0PB0 PBPU

PBSR ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up

INT0 PBSR ST — Exte�nal inte��upt inputAN0 PBSR AN — ADC input �hannel 0

PB1/INT1/AN1PB1 PBPU


INT1 PBSR ST — Exte�nal inte��upt inputAN1 PBSR AN — ADC input �hannel 1

PB�/PTCK0/AN�

PB� PBPUPBSR ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up

PTCK0 PBSR ST — PTM0 �lo�k inputAN� PBSR AN — ADC input �hannel �

PB�/SCOM�/AN7


SCOM� SCOMC — SCOM LCD d�ive� output fo� LCD panel �o��onAN7 PBSR AN — ADC input �hannel 7

PB�/CLO/SCOM�


CLO PBSR — CMOS Syste� �lo�k outputSCOM� SCOMC — SCOM LCD d�ive� output fo� LCD panel �o��on

PB5/PTP0BPB5 PBPU


PTP0B PBSR ST CMOS PTM0 inve�ting output

PB6/PTP1BPB6 PBPU


PTP1B PBSR ST CMOS PTM1 inve�ting output

PC0/SCOM0PC0 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up

SCOM0 SCOMC — SCOM LCD d�ive� output fo� LCD panel �o��on

PC1/SCOM1PC1 PCPU ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up

SCOM1 SCOMC — SCOM LCD d�ive� output fo� LCD panel �o��on

PC�/RESPC1 PCPU

RSTC ST CMOS Gene�al pu�pose I/O. Registe� ena�led pull-up

RES RSTC ST — Exte�nal �eset inputVDD VDD — PWR — Digital positive powe� supply

AVDD AVDD — PWR — Analog positive powe� supply

VSS VSS — PWR — Digital negative powe� supplyAVSS AVSS — PWR — Analog negative powe� supply

Legend:I/T:Inputtype O/T:Outputtype PWR:Power OP:Optionalbyregisteroption SCOM:SoftwarecontrolledLCDCOM ST:SchmittTriggerinput CMOS:CMOSoutput AN:Analogsignal *:VDDisthedevicepowersupplywhileAVDDistheADCpowersupply.TheAVDDpinisbonded togetherinternallywithVDD.

**:VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.TheAVSSpinisbondedtogether internallywithVSS.

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Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa = �5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Ope�ating Voltage (HIRC) — fSYS=8MHz �.� — 5.5 V

IDD1Ope�ating Cu��ent�No��al Mode� fSYS=fH (HIRC)

�V No load� fH=8MHz� ADC off� WDT ena�le� LVR ena�le

— 1.0 �.0 �A5V — �.0 �.0 �A

IDD�Ope�ating Cu��ent�Slow Mode� fSYS=fL=LIRC

�V No load� fSYS=LIRC� ADC off� WDT ena�le � LVR ena�le

— �0 �0 μA5V — �0 60 μA

IDD�Ope�ating Cu��ent�No��al Mode� fH=8MHz (HIRC)

�V No load� fSYS=fH/�� ADC off� WDT ena�le� LVR ena�le

— 1.0 1.5 �A5V — 1.5 �.0 �A�V No load� fSYS=fH/�� ADC off�

WDT ena�le� LVR ena�le— 0.9 1.� �A

5V — 1.� 1.8 �A�V No load� fSYS=fH/8� ADC off�

WDT ena�le� LVR ena�le— 0.8 1.1 �A

5V — 1.1 1.6 �A�V No load� fSYS=fH/16� ADC off�


5V — 1.0 1.� �A�V No load� fSYS=fH/�� ADC off�


5V — 0.9 1.� �A�V No load� fSYS=fH/6�� ADC off�


5V — 0.8 1.1 �A

IIDLE0IDLE0 Mode Stand�y Cu��ent(LIRC on)

�V No load� ADC off� WDT ena�le� LVR disa�le

— 1.� �.0 μA

5V — 5.0 10 μA

IIDLE1IDLE1 Mode Stand�y Cu��ent(HIRC)

�V No load� ADC off� WDT ena�le� fSYS=8MHz on

— 0.8 1.6 �A

5V — 1.0 �.0 �A

ISLEEP0SLEEP0 Mode Stand�y Cu��ent(LIRC off)

�V No load� ADC off� WDT disa�le� LVR disa�le

— 0.1 1.0 μA

5V — 0.� �.0 μA

ISLEEP1SLEEP1 Mode Stand�y Cu��ent(LIRC on)

�V No load� ADC off� WDT ena�le� LVR disa�le

— 1.� 5.0 μA

5V — �.� 10 μA

VIL1Input Low Voltage fo� I/O Po�ts o� Input Pins ex�ept RES pin

5V — 0 — 1.5 V— — 0 — 0.�VDD V

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VIH1Input High Voltage fo� I/O Po�ts o� Input Pins ex�ept RES pin

5V — �.5 — 5.0 V— — 0.8VDD — VDD V

VIL� Input Low Voltage (RES) — — 0 — 0.�VDD VVIH� Input High Voltage (RES) — — 0.9VDD — VDD V

IOL I/O Po�t Sink Cu��ent�V VOL=0.1VDD 18 �6 — �A5V VOL=0.1VDD �0 80 — �A

IOH I/O Po�t� Sou��e Cu��ent�V VOH=0.9VDD -� -6 — �A5V VOH=0.9VDD -7 -1� — �A

RPH Pull-high Resistan�e fo� I/O Po�ts�V — �0 60 100 kΩ5V — 10 �0 50 kΩ

IOCDS

Ope�ating Cu��ent� No��al Mode� fSYS=fH (HIRC) (fo� OCDS EV testing� �onne�t to an e-Link)

�V No load� fH=8MHz� ADC off� WDT ena�le — 1.� �.0 �A

A.C. CharacteristicsTa = �5°C


Min. Typ. Max. UnitVDD Condition

fCPU Ope�ating Clo�k �.�V~5.5V — DC — 8 MHz

fHIRC Syste� Clo�k (HIRC)

�V/5V Ta = �5°C -�% 8 +�% MHz�V/5V Ta = 0°C to 70°C -5% 8 +5% MHz

�.�V~5.5V Ta = 0°C to 70°C -8% 8 +8% MHz�.�V~5.5V Ta = -�0°C to 85°C -1�% 8 +1�% MHz

fLIRC Syste� Clo�k (LIRC) �.�V~5.5V Ta = -�0°C to 85°C 8 �� 50 kHztTIMER xTCKn� xTPnI Input Pulse Width — — 0.� — — μstRES Exte�nal Reset Low Pulse Width — — 10 — — μstINT Inte��upt Pulse Width — — 0.� — — μstEERD EEPROM Read Ti�e — — — � � tSYS

tEEWR EEPROM W�ite Ti�e — — — � 5 �s

tSST

Syste� Sta�t-up Ti�e� Pe�iod(Wake-up f�o� HALT� fSYS off at HALT state)

—fSYS =HIRC 16 — —

tSYSfSYS =LIRC � — —

tRSTD

Syste� Reset Delay Ti�e(Powe� On Reset� LVR �eset� WDT S/W �eset(WDTC)

— — �5 50 100 �s

Syste� Reset Delay Ti�e(RES �eset� WDT no��al �eset) — — 8.� 16.7 ��.� �s

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

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ADC Electrical CharacteristicsTa = �5°C



AVDD A/D Conve�te� Ope�ating Voltage — — �.7 — 5.5 VVADI A/D Conve�te� Input Voltage — — 0 — AVDD/VREF VVREF A/D Conve�te� Refe�en�e Voltage — — � — AVDD V

DNL Diffe�ential Non-linea�ity�.7V

VREF=AVDD=VDD

tADCK =0.5μs -� — +� LSB�V5V

INL Integ�al Non-linea�ity�.7V

VREF=AVDD=VDD

tADCK =0.5μs -� — +� LSB�V5V

IADCAdditional Powe� Consu�ption if A/D Conve�te� is used

�V No load (tADCK =0.5μs ) — 1.0 �.0 �A5V No load (tADCK =0.5μs ) — 1.5 �.0 �A

tADCK A/D Conve�te� Clo�k Pe�iod �.7V~5.5V — 0.5 — 10 μs

tADCA/D Conve�sion Ti�e (In�lude Sa�ple and Hold Ti�e) �.7V~5.5V 1�-�it ADC 16 — �0 tADCK

tADS A/D Conve�te� Sa�pling Ti�e �.7V~5.5V — — � — tADCK

tON�ST A/D Conve�te� On-to-Sta�t Ti�e �.7V~5.5V — � — — μs

LVR Electrical Characteristics



VDD Ope�ating Voltage — — 1.9 — 5.5 VVLVR Low Voltage Reset Voltage — LVR Ena�le� �.1V option -5% �.10 +5% VVBG Refe�en�e Output with Buffe� — TJ = �5°C @�.15V -5% 1.0� +5% VtLVR Low Voltage Width to Reset — — 160 ��0 6�0 μs

LCD Electrical Characteristics



IBIAS VDD/� Bias Cu��ent fo� LCD 5V

ISEL[1:0]=00 17.5 �5.0 ��.5 μAISEL[1:0]=01 �5 50 65 μAISEL[1:0]=10 70 100 1�0 μAISEL[1:0]=11 1�0 �00 �60 μA

VSCOM VDD/� Voltage fo� LCD COM Po�t �.�V~5.5V No load 0.�75 0.5 0.5�5 VDD

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Power on Reset Electrical CharacteristicsTa = �5°C



VPOR VDD Sta�t Voltage to Ensu�e Powe�-on Reset — — — — 100 �VRRVDD VDD Rising Rate to Ensu�e Powe�-on Reset — — 0.0�5 — — V/�s

tPORMini�u� Ti�e fo� VDD Stays at VPOR to Ensu�e Powe�-on Reset — — 1 — — �s

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthesedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

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System Clock and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Program CounterHigh byte PCL Register

HT50F50 PC9~PC8 PCL7~PCL0HT50F51 PC10~PC8 PCL7~PCL0

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Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Device Stack LevelsHT50F50 �HT50F51 �

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC• IncrementandDecrement:INCA,INC,DECA,DEC• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

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Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthesedevicestheProgramMemoryareFlash type,whichmeans itcanbeprogrammedandre-programmeda largenumberof times,allowingtheuser theconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof1K×14or2K×15bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

000H00�H

�FFH

Reset

Inte��upt Ve�to�

1� �its

HT50F50

018H

Reset

Inte��upt Ve�to�

15 �its

HT50F51

01CH

7FFH

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000Hisreservedforusebythesedevicesresetforprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregister,TBLP.Thisregisterdefinesthetotaladdressofthelook-uptable.Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“300H”whichreferstothestartaddressofthelastpagewithinthe1KwordsProgramMemoryofthedeviceHT50F50.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“306H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthespecifiedpageif the“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or present page::tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “306H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address “305H” transferred to tempreg2 and TBLH in this ; example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2::org 300h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::

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In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

Holtek Write PinsMCU Programming Pins

FunctionHT50F50 HT50F51

ICPDA PA0 P�og�a��ing Se�ial DataICPCK PA7 PA� P�og�a��ing Se�ial Clo�kVDD VDD Powe� SupplyVSS VSS G�ound

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandground.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

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HT50F50 HT50F51Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitance

of*mustbelessthan1nF.

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On-Chip Debug Support – OCDSThere isanEVchipwhichisusedtoemulate theHT50F51deviceseries.ThisEVchipdevicealsoprovidesan“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnecting theOCDSDAandOCDSCKpins to theHoltekHT-IDEdevelopment tools.TheOCDSDApinis theOCDSData/Address input/outputpinwhile theOCDSCKpinis theOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpins in theactualMCUdevicewillhavenoeffect in theEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription,refertothecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-�hip De�ug Suppo�t Data/Add�ess input/outputOCDSCK OCDSCK On-�hip De�ug Suppo�t Clo�k input

VDD VDD Powe� SupplyGND VSS G�ound

RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforalldevicesistheaddress00H.

General Purpose Data MemoryThereis64or96bytesofgeneralpurposedatamemorywhicharearrangedinBank0andBank1.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

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Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

Device Capacity Bank 0 Bank 1HT50F50 6�×8 �0H~7FH �0H EEC �egiste� onlyHT50F51 96×8 �0H~9FH �0H EEC �egiste� only

00H IAR001H MP00�H IAR10�H MP10�H05H ACC06H PCL07H TBLP08H TBLH09H

INTC1

0AH STATUS0BH0CH0DH0EH0FH10H

SMOD

11H

EEA

1�H

19H18H

1BH1AH

1DH1CH

1FH1EH

1�H1�H15H16H17H

INTEG

Unused

STM0AL

PAPUPAWU

�0H�1H��H

�9H�8H

�BH�AH

�DH�CH

�EH~

�FH

��H��H�5H�6H�7H

BP

STM0DLSTM0C1

STM0DH

PAPAC

STM0C0

INTC0

: Unused� �ead as “00”

EED

Unused

Unused

STM0AHUnused

UnusedMFI0

UnusedUnused

IFS0WDTC

TBCSMOD1

PASRRSTC

SADC1SADC0

SADC�

SADOLSADOH

Unused

Unused

Bank0 & Bank1 Bank0 & Bank1

HT50F50 Special Purpose Data Memory Structure

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00H IAR001H MP00�H IAR10�H MP10�H05H ACC06H PCL07H TBLP08H TBLH09H

INTC1

0AH STATUS0BH0CH0DH0EH0FH10H

SMOD

11H

EEA

1�H

19H18H

1BH1AH

1DH1CH

1FH1EH

1�H1�H15H16H17H

INTEG

SCOMC

PTM0DH

PAPUPAWU

�0H�1H��H

�9H�8H

�BH�AH

�DH�CH

�EH

��H��H�5H�6H�7H

BP

PTM0C1PTM0C0

PTM0DL

PAPAC

INTC0

: Unused� �ead as “00”

EED

Unused

Unused

PTM0ALUnused

UnusedMFI0

Unused

WDTC

TBCSMOD1

PASRRSTC

SADC1SADC0

SADC�

SADOLSADOH

Bank0 & Bank1 Bank0 & Bank1

PTM1AH

PTM1DHPTM1DL

PTM1AL

PTM1C1

PTM1RPL

PTM0RPHPTM0RPL

��H��H

�5H��H

�7H�6H

�8H

�FH�0H�1H

PTM1RPH�9H

PTM0AH

PTM1C0

PBSR

Unused

Unused

Unused

Unused

PCC

PBPUPBC

PC

PB

PCPU

�AH

�CH�BH

�DH�EH�FH

HT50F51 Special Purpose Data Memory Structure

Unused

EECGene�alPu�pose

Data Me�o�y

�0H

7FH

HT50F50 General Purpose Data Memory

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Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org00hstart: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

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Bank Pointer – BPForthisseriesofdevices,theDataMemoryisdividedintotwobanks,Bank0andBank1.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBLHThese twospecial functionregistersareused tocontroloperationof the look-up tablewhich isstoredintheProgramMemory.TBLPisthetablepointerandindicatethelocationwherethetabledata is located. Itsvaluemustbesetupbeforeanytablereadcommandsareexecuted. Itsvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHis thelocationwherethehighorderbyteof thetabledata isstoredaftera tablereaddatainstructionhasbeenexecuted.Notethat thelowerordertabledatabyteistransferredtoauserdefinedlocation.

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Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

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STATUS RegisterBit 7 6 5 4 3 2 1 0

Na�e — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 × × × ×

"×" unknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:nooverflow1:anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:noauxiliarycarry1:anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:nocarry-out1:anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

EEPROM Data MemoryThesedevicescontainanareaof internalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupplyisremoved.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproduct informationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis32×8bitsforthisseriesofdevices.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemory isnotdirectlymappedand isthereforenotdirectlyaccessible in thesamewayas theother typesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusingtwoaddressregistersandonedataregisterinBank0andasinglecontrolregisterinBank1.

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EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregisters,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Control Registers List

NameBit

7 6 5 4 3 2 1 0EEA — — — D� D� D� D1 D0EED D7 D6 D5 D� D� D� D1 D0EEC — — — — WREN WR RDEN RD

EEA RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — D� D� D� D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas“0”Bit4~0 DataEEPROMaddress

DataEEPROMaddressbit4~bit0

EED RegisterBit 7 6 5 4 3 2 1 0

Na�e D7 D6 D5 D� D� D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 DataEEPROMdataDataEEPROMdatabit7~bit0

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EEC RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

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Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided in severalways.After thedevicesarepowered-ontheWriteEnablebit in thecontrolregisterwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.Iftheglobal,EEPROMInterruptareenabledandthestackisnotfull,asubroutinecalltotheEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEEPROMInterruptflagDEFwillbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

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Programming ConsiderationsCaremustbetakenthatdataisnotinadvertentlywrittentotheEEPROM.ProtectioncanbePeriodicbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrol register exist.Althoughcertainlynotnecessary, considerationmightbegiven in theapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedevicesshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples• Reading data from the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BPMOV A, EED ; move read data to registerMOV READ_DATA, A

• Writing Data to the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1MOV MP1, A ; MP1 points to EEC registerMOV A, 01H ; setup Bank PointerMOV BP, ACLR EMISET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bit– executed immediately after ; set WREN bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM writeCLR BP

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OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Twofullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillator.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thesedeviceshavetheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq.Inte�nal High Speed RC HIRC 8MHzInte�nal Low Speed RC LIRC ��kHz

Oscillator Types

System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillatoristheinternal8MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

HIRC P�es�ale�fH

LIRC

Low Speed Os�illato�

fH/�

fH/16

fH/6�

fH/8

fH/�

fH/��

HLCLKCKS�~CKS0 �its

fSYS

fL

High Speed Os�illato�

System Clock Configurations

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Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillator has a fixed frequency of8MHz.Device trimming during themanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethat theinfluenceof thepowersupplyvoltage, temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandattemperatureof25°Cdegrees,thefixedoscillationfrequencyoftheHIRCwillhaveatolerancewithin2%.

Internal 32kHz Oscillator – LIRCThe internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Supplementary OscillatorThelowspeedoscillator, inadditiontoprovidingasystemclocksource isalsousedtoprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThesedeviceshavetwodifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byproviding theuserwithclockoptionsusing registerprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,oralowfrequency,fL,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheinternalclockfL.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Thereisoneadditionalinternalclockfortheperipheralcircuits, theTimeBaseclock,fTBC.fTBCissourcedfromtheLIRCoscillators.ThefTBCclockisusedasasourcefortheTimeBaseinterruptfunctionsandfortheTMs.

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HIRC P�es�ale�fH

LIRC

Low Speed Os�illato�

fH/�

fH/16

fH/6�

fH/8

fH/�

fH/��

HLCLKCKS�~CKS0 �its

fSYS

fLIRC

High Speed Os�illato�

WDT

fSYS/�

fTB

Ti�e Base 0

Ti�e Base 1TBCK

fL

fTBC

IDLEN

System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillatorwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1modesareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

OperatingMode

DescriptionCPU fSYS fLIRC fTBC

NORMAL �ode On fH~fH/6� On OnSLOW �ode On fL On OnIDLE0 �ode Off Off On OnIDLE1 �ode Off On On On

SLEEP0 �ode Off Off Off OffSLEEP1 �ode Off Off On Off

NORMAL ModeAsthenamesuggests this isoneof themainoperatingmodeswhere themicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedthehighspeedoscillator.ThismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillatorHIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsintheSMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

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SLOW ModeThis isalsoamodewhere themicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromthelowspeedoscillatorLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisteris low.IntheSLEEP0modetheCPUwillbestopped,andthefLIRCclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.

SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefLIRCclockswillcontinuetooperateiftheWatchdogTimerfunctionisenabled.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.

IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheSMOD1registerishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1Mode,theWatchdogTimerclock,fLIRC,willbeon.

Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice.

SMOD RegisterBit 7 6 5 4 3 2 1 0

Na�e CKS� CKS1 CKS0 — LTO HTO IDLEN HLCLKR/W R/W R/W R/W — R R R/W R/WPOR 0 0 0 — 0 0 1 1

Bit7~5 CKS2 ~ CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fL(fLIRC)001:fL(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

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Bit4 Unimplemented,readas"0"Bit3 LTO:Lowspeedsystemoscillatorreadyflag

0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0mode,butafterawake-uphasoccurredtheflagwillchangetoahighlevelafter1~2cyclesiftheLIRCoscillatorisused.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.

Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfL1:fH

Thisbit isusedtoselectif thefHclockorthefH/2~fH/64orfLclockisusedasthesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

SMOD1 Register Bit 7 6 5 4 3 2 1 0

Na�e FSYSON — — — RSTF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0

“x” unknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

Bit6~4 Unimplemented,readas“0”Bit3 RSTF: ResetcausedbyRSTCsetting

0:Notactive1:Active

Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearedbySoftwareorPORreset.

Bit2 LVRF:LVRfunctionresetflag0:Notactive1:Active

Thisbitcanbeclearto“0”,butcannotbesetto“1”.

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Bit1 Unimplemented,readas“0”Bit0 WRF:WDTControlregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

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Operating Mode SwitchingThedevicescanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheSMOD1register.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMs.

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NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto“0”andsetting theCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.

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Entering the SLEEP0 ModeThereisonlyonewayforthedevicestoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDToff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstopped.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

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Entering the SLEEP1 ModeThereisonlyonewayforthedevicestoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefLIRCclock.


• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.



Entering the IDLE0 ModeThereisonlyonewayforthedevicestoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruc-tion,buttheTimeBaseclockwillbeon.





Entering the IDLE1 ModeThereisonlyonewayforthedevicestoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinSMOD1registerequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.





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Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinson thedevices.Allhigh-impedance inputpinsmustbeconnected toeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

If thesystemiswokenupbyanexternal reset, thedevicewillexperiencea full systemreset,however, If thesedevicesarewokenupbyaWDToverflow,aWatchdogTimer resetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

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Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalfLIRCclockwhichissuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWDTcanbeenabled/disabledusingtheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.TheWRFsoftwareresetflagwillbeindicatedintheSMOD1register.TheseregisterscontroltheoveralloperationoftheWatchdogTimer.

WDTC RegisterBit 7 6 5 4 3 2 1 0

Na�e WE� WE� WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4 ~ WE0:WDTfunctionsoftwarecontrol10101:WDTdisable01010:WDTenableOthervalues:ResetMCU

Whenthesebitsarechangedtoanyothervaluesbytheenvironmentalnoisetoresetthemicrocontroller,theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitwillbesetto1toindicatetheresetsource.

Bit2~0 WS2 ~ WS0:WDTTime-outperiodselection000:28/fLIRC001:29/fLIRC010:210/fLIRC011:211/fLIRC(default)100:212/fLIRC101:213/fLIRC110:214/fLIRC111:215/fLIRC

Thesethreebitsdeterminethedivisionratioof theWatchdogTimersourececlock,whichinturndeterminesthetimeoutperiod.

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SMOD1 RegisterBit 7 6 5 4 3 2 1 0

Na�e FSYSON — — — RSTF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0


0:Disable1:Enable

Bit6~4 Unimplemented,readas“0”Bit3 RSTF: ResetcausedbyRSTCsetting

0:Notactive1:Active

Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearbySoftwareorPORreset.


Thisbitcanbeclearto“0”,butcannotbesetto“1”.Bit1 Unimplemented,readas“0”Bit0 WRF:WDTControlregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit is set to1by theWDTControl register software resetandclearedby theapplicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearWDTinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertoadditionalenable/disableandresetcontroloftheWatchdogTimer.

WE4 ~ WE0 Bits WDT Function10101B Disa�le01010B Ena�le

Any othe� value Reset MCU

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.Fourmethodscanbeadoptedtoclear thecontentsof theWatchdogTimer.ThefirstisaWDTreset,whichmeansavalueotherthan01010Band10101BiswrittenintotheWE4~WE0bitlocations,thesecondisanexternalhardwarereset,whichmeansalowlevelontheexternalresetpin,thethirdisusingtheWatchdogTimersoftwareclearinstructionsandthefourthisviaaHALTinstruction.There isonlyonemethodofusingsoftware instruction toclear theWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

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Themaximumtime-outperiodiswhenthe215divisionratioisselected.Asanexample,witha32kHzLIRCoscillatoras itssourceclock, thiswillgiveamaximumwatchdogperiodofaround1secondforthe215divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Inst�u�tion

11-stage Divide�

7-stage Divide�

WE�~WE0 �itsWDTC Registe� Reset MCU

LIRCfLIRC

8-to-1 MUX

CLR

WS�~WS0(fLIRC/�1 ~ fLIRC/�11)

WDT Ti�e-out(�8/fLIRC ~ �15/fLIRC)

RES pin �eset

“HALT”Inst�u�tion

Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicescanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inaddition to thepower-onreset,situationsmayarisewhere it isnecessary toforcefullyapplyaresetconditionwhenthemicrocontroller isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof themicrocontrollerregistersremainunchangedallowing themicrocontroller toproceedwithnormaloperationafter thereset line isallowedtoreturnhigh.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

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Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur, througheventsoccurringbothinternallyandexternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart

RES Pin ResetAlthoughthemicrocontrollerhasaninternalRCresetfunction,if theVDDpowersupplyrisetimeisnot fastenoughordoesnotstabilisequicklyatpower-on, the internal reset functionmaybeincapableofprovidingproperresetoperation.Forthisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationof themicrocontrollerwillbe inhibited.After theRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.Anywiringconnectedto theRESpinshouldbekeptasshortaspossible tominimizeanystraynoiseinterference.Forapplicationsthatoperatewithinanenvironmentwheremorenoiseispresent theEnhancedResetCircuitshownisrecommended.

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External RES Circuit

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MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

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Note:tRSTDispower-ondelay,typicaltime=16.7msRES Reset Timing Chart

• RSTC External Reset Register – HT50F50

Bit 7 6 5 4 3 2 1 0Na�e RSTC7 RSTC6 RSTC5 RSTC� RSTC� RSTC� RSTC1 RSTC0R/W R/W R/W R/W R/W R R R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 RSTC7 ~ RSTC0:PA7/RESselection01010101:configuredasPA7pinorotherfunction10101010:configuredasRESpinOtherValues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)

AllresetwillresetthisregisterasPORvalueexceptWDTtimeoutHardwarewarmreset.

• RSTC External Reset Register – HT50F51

Bit 7 6 5 4 3 2 1 0Na�e RSTC7 RSTC6 RSTC5 RSTC� RSTC� RSTC� RSTC1 RSTC0R/W R/W R/W R/W R/W R R R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 RSTC7 ~ RSTC0:PC2/RESselection01010101:ConfiguredasPC2pinorotherfunction10101010:ConfiguredasRESpinOtherValues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)

AllresetwillresetthisregisterasPORvalueexceptWDTtimeoutHardwarewarmreset.

Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedeviceandprovideanMCUresetshouldthevaluefallbelowacertainpredefinedlevel.TheLVRfunctionisalwaysenabledduringthenormalandslowmodeswithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery, theLVRwillautomaticallyreset thedeviceinternallyandtheLVRFbitintheSMOD1registerwillalsobesetto1.ForavalidLVRsignal,alowvoltage,i.e.,avoltagein therangebetween0.9V~VLVRmustexistforgreater thanthevaluetLVRspecifiedin theA.C.characteristics. If the lowvoltagestatedoesnotexceedthisvalue, theLVRwill ignore the lowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRis2.1V,theLVRwillresetthedeviceafter2~3LIRCclockcycles.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceenterstheSLEEP/IDLEmode.

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Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

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• SMOD1 Register

Bit 7 6 5 4 3 2 1 0Na�e FSYSON — — — RSTF LVRF — WRFR/W R/W — — — R/W R/W — R/WPOR 0 — — — 0 x — 0


DescribeelsewhereBit6~4 Unimplemented,readas“0”Bit3 RSTF: ResetcausedbyRSTCsetting

0:Notactive1:Active

Thisbitcanbeclearto“0”,butcannotsetto“1”.Ifthisbitisset,onlyclearbySoftwareorPORreset.


Thisbitcanbeclearto“0”,butcannotbesetto“1”.Bit1 Unimplemented,readas“0”Bit0 WRF:WDTControlregistersoftwareresetflag

Describeelsewhere

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasanLVRresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

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Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

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WDT Time-out Reset during SLEEP or IDLE Timing Chart

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Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe�-on �esetu u LVR �eset du�ing NORMAL o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing NORMAL o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

Note:“u”standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins �ountingTi�e� Modules Ti�e� Modules will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputsSta�k Pointe� Sta�k Pointe� will point to the top of the sta�k

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Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs, it isimportanttoknowwhatconditionthemicrocontroller is inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.Notethatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Register

HT50F50

HT50F51

Reset(Power On)

WDT Time-out(Normal

Operation)

RES Reset(Normal

Operation)

RES Reset(HALT)

WDT Time-out(HALT)*

P�og�a� Counte� ● ● 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H

MP0 ● ● 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 u u u u u u uMP1 ● ● 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 x x x x x x x 1 u u u u u u uBP ● ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u uPCL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP ● ● x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u uTBLH ● ● - - x x x x x x - - u u u u u u - - u u u u u u - - u u u u u u - - u u u u u uSTATUS ● ● - - 0 0 x x x x - - 1 u u u u u - - u u u u u u - - 0 1 u u u u - - 1 1 u u u uSMOD ● ● 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 u u u - u u u uINTEG ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uINTC0 ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

INTC1● - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u u

● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

MFI0● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAPU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uIFS0 ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uWDTC ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u uTBC ● ● 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 u u u u – u u uSMOD1 ● ● 0 - - - 0 x - 0 0 - - - 0 x - 0 0 - - - 0 x - 0 0 - - - 0 x - 0 u - - - u u - uSCOMC ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uEEA ● ● - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u uEED ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSADOL(ADRFS=0) ● ● x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u u - - - -

SADOL(ADRFS=1) ● ● x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

SADOH(ADRFS=0) ● ● x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

SADOH(ADRFS=1) ● ● - - - - x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u u

SADC0● 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 u u u u - - u u

● 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 u u u u - u u uSADC1 ● ● 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 u u u - - u u uSADC� ● ● 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 u u - - u u u uRSTC ● ● 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u u

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Register

HT50F50

HT50F51

Reset(Power On)

WDT Time-out(Normal

Operation)

RES Reset(Normal

Operation)

RES Reset(HALT)

WDT Time-out(HALT)*

PASR ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPBSR ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uSTM0C0 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTM0C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTM0DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTM0DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSTM0AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uSTM0AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0C0 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM0RPL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM0RPH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1C0 ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -PTM1C1 ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1DL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1DH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1AL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1AH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPTM1RPL ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPTM1RPH ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uPB ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u uPBC ● - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - u u u u u u uPBPU ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uPC ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u uPCC ● - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u uPCPU ● - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uEEC ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

Note:"*"standsforwarmreset"-"notimplement"u"standsfor"unchanged""x"standsfor"unknown"

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Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedevicesprovidebidirectional input/output lines labeledwithportnamesPA~PC.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Control Register List• HT50F50

RegisterName

Bit7 6 5 4 3 2 1 0

PA D7 D6 D5 D� D� D� D1 D0PAC D7 D6 D5 D� D� D� D1 D0

PAPU D7 D6 D5 D� D� D� D1 D0PAWU D7 D6 D5 D� D� D� D1 D0PASR PAS7 PAS6 PAS5 PAS� PAS� PAS� PAS1 PAS0IFS0 — — STCK0PS STP0IPS — — INTPS1 INTPS0

• HT50F51

RegisterName

Bit7 6 5 4 3 2 1 0

PA D7 D6 D5 D� D� D� D1 D0PAC D7 D6 D5 D� D� D� D1 D0

PAPU D7 D6 D5 D� D� D� D1 D0PAWU D7 D6 D5 D� D� D� D1 D0

PB — D6 D5 D� D� D� D1 D0PBC — D6 D5 D� D� D� D1 D0

PBPU — D6 D5 D� D� D� D1 D0PC — — — — — D� D1 D0

PCC — — — — — D� D1 D0PCPU — — — — — D� D1 D0PASR PAS7 PAS6 PAS5 PAS� PAS� PAS� PAS1 PAS0PBSR — PBS6 PBS5 PBS� PBS� PBS� PBS1 PBS0

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Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternalresistor.Toeliminatetheneedfortheseexternalresistors,allI/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregisterPAPU~PCPU,andareimplementedusingweakPMOStransistors.

PAPU RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0Pull-HighControl0:Disable1:Enable

PBPU Register – HT50F51 Bit 7 6 5 4 3 2 1 0

Na�e — D6 D5 D� D� D� D1 D0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~0 I/OPortBbit6~bit0Pull-HighControl

0:Disable1:Enable

PCPU Register – HT50F51 Bit 7 6 5 4 3 2 1 0

Na�e — — — — — D� D1 D0R/W — — — — — R/W R/W R/WPOR — — — — — 0 0 0

Bit7~3 Unimplemented,readas“0”Bit2~0 I/OPortCbit2~bit0Pull-HighControl

0:Disable1:Enable

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

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PAWU RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable

I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PCC, to control the input/outputconfiguration.With thesecontrol registers, eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input

PBC Register – HT50F51

Bit 7 6 5 4 3 2 1 0

Na�e — D6 D5 D� D� D� D1 D0

R/W — R/W R/W R/W R/W R/W R/W R/W

POR — 1 1 1 1 1 1 1

Bit7 Unimplemented,readas“0”Bit6~0 I/OPortBbit6~bit0Input/OutputControl

0:Output1:Input

PCC Register – HT50F51

Bit 7 6 5 4 3 2 1 0

Na�e — — — — — D� D1 D0

R/W — — — — — R/W R/W R/W

POR — — — — — 1 1 1

Bit7~3 Unimplemented,readas“0”Bit2~0 I/OPortCbit2~bit0Input/OutputControl

0:Output1:Input

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Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyof thesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremore thanonepinfunction isselectedsimultaneously.Additionally thereareaPASRandaPBSRregister toestablishcertainpinfunctions.Generallyspeaking, theanalogfunctionhashigherprioritythanthedigitalfunction.However,ifmorethantwoanalogfunctionsareenabledandtheanalogsignalinputcomesfromthesameexternalpin,theanaloginputwillbeinternallyconnectedtoalloftheseactiveanalogfunctionalmodules.

Pin-shared RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.

• PASR Register – HT50F50

Bit 7 6 5 4 3 2 1 0Na�e PAS7 PAS6 PAS5 PAS� PAS� PAS� PAS1 PAS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PAS7~PAS6: Pin-SharedControlBits00:PA5/INT01:STP0B10:PA5/INT11:AN3

Bit5~4 PAS5~PAS4: Pin-SharedControlBits00:PA2/INT01:STP010:VREFO11:AN2

Bit3~2 PAS3~PAS2: Pin-SharedControlBits00:PA101:STP0B10:VREF11:AN1

Bit1~0 PAS1~PAS0: Pin-SharedControlBits00:PA0/STP0I01:STP010:PA0/STP0I11:AN0

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• PASR Register – HT50F51

Bit 7 6 5 4 3 2 1 0Na�e PAS7 PAS6 PAS5 PAS� PAS� PAS� PAS1 PAS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PAS7~PAS6:Pin-SharedControlBit00:PA701:PTP110:PA711:AN6

Bit5~4 PAS5~PAS4:Pin-SharedControlBit0X:PA610:VREFO11:AN5

Bit3~2 PAS3~ PAS2:Pin-SharedControlBit0X:PA510:VREF11:AN4

Bit1 PAS1:Pin-SharedControlBits0:PA4/PTCK11:AN3

Bit0 PAS0:Pin-SharedControlBit0:PA01:PTP0

• PBSR Register – HT50F51

Bit 7 6 5 4 3 2 1 0Na�e — PBS6 PBS5 PBS� PBS� PBS� PBS1 PBS0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 PBS6:Pin-SharedControlBit

0:PB61:PTP1B

Bit5 PBS5:Pin-SharedControlBit0:PB51:PTP0B

Bit4 PBS4:Pin-SharedControlBit0:PB41:CLO

Note:PBS4isvalidwhenCOM2EN=0Bit3 PBS3:Pin-SharedControlBit

0:PB31:AN7

Note:PBS3isvalidwhenCOM3EN=0Bit2 PBS2:Pin-SharedControlBit

0:PB2/PTCK01:AN2

Bit1 PBS1:Pin-SharedControlBits0:PB1/INT11:AN1

Bit0 PBS0:Pin-SharedControlBit0:PB0/INT01:AN0

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• IFS0 Register – HT50F50

Bit 7 6 5 4 3 2 1 0Na�e — — STCK0PS STP0IPS — — INTPS1 INTPS0R/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 STCK0PS:STCK0PinRemappingControl

0:STCK0onPA7(default)1:STCK0onPA6

Bit4 STP0IPS:STP0IPinRemappingControl0:STP0IonPA6(default)1:STP0IonPA0

Bit3~2 Unimplemented,readas"0"Bit1~0 INTPS1, INTPS0:INTPinRemappingControl

00:INTonPA5(default)01:INTonPA210:INTonPA311:INTonPA7

I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

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A/D Input/Output Structure

System Clock output pin CLOThedeviceHT50F51providesasystemclockoutputpinCLO.MCUsystemclockcanoutputtotheCLOpinbysettingpin-sharedcontrolregisterbitPBS4to1.Thehighestoutputfrequencyis8MHzinthisdevice.Pleasenotethatwhenthenoiseproblemisanimportantissue,itisbetternottouseCLOoutputfunction.

Programming ConsiderationsWithintheuserprogram,oneof thefirst thingstoconsider isport initialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoan inputstate, the levelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbits in theportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

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Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevices includeseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualStandardandPeriodicTMsections.

IntroductionThedevicescontainoneortwoTMsdependinguponwhichdeviceisselectedwitheachTMhavingareferencenameofTM0~TM1.EachindividualTMcanbecategorisedasacertaintype,namelyStandardTypeTMorPeriodicTypeTM.Althoughsimilarinnature,thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestotheStandardandPeriodicTMswillbedescribedin thissectionandthedetailedoperationwillbedescribedincorrespondingsections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMsaresummarisedintheaccompanyingtable.

Function STM PTMTi�e�/Counte� √ √I/P Captu�e √ √Co�pa�e Mat�h Output √ √PWM Channels 1 1Single Pulse Output 1 1PWM Align�ent Edge EdgePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod

TM Function Summary

Device TM0 TM1HT50F50 10-�it STM —HT50F51 10-�it PTM 10-�it PTM

TM Name/Type Reference

TM OperationThetwodifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingthexTnCK2~xTnCK0bitsinthexTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH, thefTBCclocksourceortheexternalxTCKnpin.ThexTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

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TM InterruptsTheStandardandPeriodic typeTMseachhas twointernal interrupts, the internalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachof theTMs, irrespectiveofwhat type,has twoTMinputpins,with the labelxTCKnandxTPnI.TheTMinputpinxTCKn,isessentiallyaclocksourcefortheTMandisselectedusingthexTnCK2~xTnCK0bitsinthexTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingthexTnCK2~xTnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheotherTMinputpin,xTPnI,isthecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingthexTnIO1andxTnIO0bitsinthexTMnC1register.

TheTMseachhave twooutputpinswith the labelxTPn andxTPnB.When theTMis in theCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalxTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.

Device TM0 TM1

HT50F50 STCK0� STP0ISTP0� STP0B —

HT50F51 PTCK0� PTP0IPTP0� PTP0B

PTCK1� PTP1IPTP1� PTP1B

TM Input/Output Pins

TM Input/Output Pin Control RegisterSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingone register,witha singlebit ineach registercorresponding toaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

STM

STP0

STCK0

Captu�e Input

TCK Input

Output

STP0I

STP0BInve�ting Output

STM Function Pin Control Block Diagram

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PTM

PTPn

PTCKn

Captu�e Input

TCK Input

Output

PTPnI

PTPnBInve�ting Output

PTM Function Pin Control Block Diagram

Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAregister,andCCRPregisterpairforPeriodicTimerModule,allhavea lowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.As theCCRAregisterandCCRPregistersare implemented in thewayshown in thefollowingdiagramandaccessing the register iscarriedoutCCRP lowbyte registerusing the followingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-�it Buffe�

STM0DHSTM0DL

STM0AHSTM0AL

STM CCRA Registe� (Read/W�ite)

STM Counte� Registe� (Read only)

Data Bus

8-�it Buffe�

PTMnDHPTMnDL

PTMnAHPTMnAL

PTM CCRA Registe� (Read/W�ite)

PTM Counte� Registe� (Read only)

PTMnRPHPTMnRPL

PTM CCRP Registe� (Read/W�ite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorPTMCCRP♦ Step1.WritedatatoLowByteSTM0ALPTMnALorPTMnRPL

– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteSTM0AHPTMnAHorPTMnRPH

– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorPTMCCRP♦ Step1.ReaddatafromtheHighByteSTM0DH,STM0AHPTMnDH,PTMnAHorPTMnRPH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteSTM0DL,STM0ALPTMnDL,PTMnALorPTMnRPL– thisstepreadsdatafromthe8-bitbuffer.

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Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanbecontrolledwithtwoexternalinputpinsandcandrivetwoexternaloutputpins.

Device TM Type TM Name TM Input Pin TM Output Pin

HT50F50 10-�it STM STM STCK0� STP0I STP0� STP0B

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Standard Type TM Block Diagram

Standard TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis3-bitwidewhosevalueiscomparedwiththehighest3bitsinthecounterwhiletheCCRAisthe10bitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclearthecounterbychangingtheST0ONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Standard Type TM Register DescriptionOveralloperationof theStandardTMiscontrolledusingseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0STM0C0 ST0PAU ST0CK� ST0CK1 ST0CK0 ST0ON ST0RP� ST0RP1 ST0RP0STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLRSTM0DL D7 D6 D5 D� D� D� D1 D0STM0DH — — — — — — D9 D8STM0AL D7 D6 D5 D� D� D� D1 D0STM0AH — — — — — — D9 D8

10-bit Standard TM Register List

STM0C0 RegisterBit 7 6 5 4 3 2 1 0

Na�e ST0PAU ST0CK� ST0CK1 ST0CK0 ST0ON ST0RP� ST0RP1 ST0RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

bit7 ST0PAU:STMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

bit6~4 ST0CK2~ST0CK0:SelectSTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:STCK0risingedgeclock111:STCK0fallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

bit3 ST0ON:STMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheST0OCbit,whentheST0ONbitchangesfromlowtohigh.

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bit2~0 ST0RP2~ ST0RP0:STMCCRP3-bitregister,comparedwiththeSTMCounterbit9~bit7ComparatorPMatchPeriod000:1024STM0clocks001:128STM0clocks010:256STM0clocks011:384STM0clocks100:512STM0clocks101:640STM0clocks110:768STM0clocks111:896STM0clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheST0CCLRbitissettozero.SettingtheST0CCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

STM0C1 RegisterBit 7 6 5 4 3 2 1 0

Na�e ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

bit7~6 ST0M1~ ST0M0:SelectSTM0OperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMoutputModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheSTM.ToensurereliableoperationtheSTMshouldbeswitchedoffbeforeanychangesaremade to theST0M1andST0M0bits.IntheTimer/CounterMode,theSTMoutputpinstateisundefined.

bit5~4 ST0IO1~ ST0IO0:SelectSTM0functionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMoutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofSTP0I01:InputcaptureatfallingedgeofSTP0I10:Inputcaptureatfalling/risingedgeofSTP0I11:Inputcapturedisabled

Timer/counterMode:Unused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

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IntheCompareMatchOutputMode,theST0IO1~ST0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheST0IO1~ST0IO0 bitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheST0OCbit.Notethat theoutput levelrequestedbytheST0IO1~ST0IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheST0OCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to itsinitiallevelbychangingtheleveloftheST0ONbitfromlowtohigh.InthePWMMode,theST0IO1andST0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheST0IO1andST0IO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheST0IO1andST0IO0bitsarechangedwhentheTMisrunning.

bit3 ST0OC:STM0OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMoutputMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theSTMoutputpin. ItsoperationdependsuponwhetherSTMisbeingusedintheCompareMatchOutputModeorinthePWMoutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheSTMoutputpinbeforeacomparematchoccurs.InthePWMoutputModeitdeterminesif thePWMsignal isactivehighoractivelow.IntheSinglePulseOutputModeitdeterminesthelogicleveloftheSTMoutputpinwhentheST0ONbitchangesfromlowtohigh.

bit2 ST0POL:STM0OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheSTM0outputpin.WhenthebitissethightheSTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMisintheTimer/CounterMode.

bit1 ST0DPX:STM0PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

bit0 ST0CCLR:SelectSTM0Counterclearcondition0:STM0ComparatorPmatch1:STM0ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardSTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththeST0CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheST0CCLRbitisnotusedinthePWMoutputmode,SinglePulseorInputCaptureMode.

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STM0DL Register Bit 7 6 5 4 3 2 1 0

Na�e D7 D6 D5 D� D� D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 STM0CounterLowByteRegisterbit7~bit0STM010-bitCounterbit7~bit0

STM0DH Register Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

bit7~2 Unimplemented,readas"0"bit1~0 STM0CounterHighByteRegisterbit1~bit0

STM010-bitCounterbit9~bit8

STM0AL RegisterBit 7 6 5 4 3 2 1 0


bit7~0 STM0CCRALowByteRegisterbit7~bit0STM010-bitCounterbit7~bit0

STM0AH RegisterBit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

bit7~2 Unimplemented,readas"0"bit1~0 STM0CCRAHighByteRegisterbit1~bit0

STM010-bitCounterbit9~bit8

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Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheST0M1andST0M0bitsintheSTM0C1register.

Compare Output ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheST0CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMA0FandSTMP0FinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheST0CCLRbitintheSTM0C1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly theSTMA0Finterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenST0CCLRishighnoSTMP0F interrupt request flagwillbegenerated. In theCompareMatchOutputMode,theCCRAcannotbesetto"0".IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheSTMA0Finterruptrequestflagwillnotbegenerated.

Asthenameofthemodesuggests,afteracomparisonismade,theSTMoutputpin,willchangestate.TheSTMoutputpinconditionhoweveronlychangesstatewhenanSTMA0FinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMP0Finterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMoutputpin.ThewayinwhichtheSTMoutputpinchangesstatearedeterminedbytheconditionoftheST0IO1andST0IO0bitsintheSTM0C1register.TheSTMoutputpincanbeselectedusingtheST0IO1andST0IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMoutputpin,whichissetupaftertheST0ONbitchangesfromlowtohigh,issetupusingtheST0OCbit.NotethatiftheST0IO1andST0IO0bitsarezerothennopinchangewilltakeplace.

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CCRA

CCRP

0x�FF

Counte� ove�flow

CCRA Int.Flag STMA0F

CCRP Int.Flag STMP0F

CCRP > 0Counte� �lea�ed �y CCRP value

STM O/P Pin

ST0ON

Pause

Counte�Reset

Output Pin set to Initial LevelLow if ST0OC= 0

Output Togglewith STMA0F flag

He�e ST0IO[1:0] = 11Toggle Output Sele�t

Now ST0IO[1:0] = 10 A�tive High Output Sele�t

Output not affe�ted �ySTMA0F flag. Re�ains Highuntil �eset �y ST0ON �it

ST0CCLR = 0; ST0M[1:0] = 00

ST0PAU

Resu�e

Stop

Ti�e

CCRP > 0

CCRP = 0

ST0POL

Output PinReset to initial value

Output inve�tswhen ST0POL is high

Output �ont�olled�y othe� pin - sha�ed fun�tion

Counte� Value

Compare Match Output Mode – ST0CCLR = 0Note:1.WithST0CCLR=0aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheSTMA0Fflag

3.TheoutputpinresettoinitialstatebyaST0ONbitrisingedge

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CCRA

CCRP

0x�FF

CCRA Int.Flag STMP0F

CCRP Int.Flag STMA0F

CCRA > 0 Counte� �lea�ed �y CCRA value

STM O/P Pin

ST0ON

Pause Counte� Reset

Output Pin set to Initial LevelLow if ST0OC= 0

Output Togglewith STMA0F flag

He�e ST0IO[1:0] = 11Toggle Output Sele�t

Now ST0IO[1:0] = 10 A�tive High Output Sele�t

Output not affe�ted �ySTMA0F flag. Re�ains Highuntil �eset �y ST0ON �it

ST0CCLR = 1; ST0M[1:0] = 00

ST0PAU

Resu�e

Stop

Ti�e

CCRA = 0

ST0POL

Output PinReset to initial value

Output inve�tswhen ST0POL is high

Output �ont�olled�y othe� pin-sha�ed fun�tion

Counte� Value

Output doesnot �hange

No STMA0F flaggene�ated on

CCRA ove�flow

CCRA = 0Counte� ove�flow

STMP0F notgene�ated

Compare Match Output Mode – ST0CCLR = 1Note:1.WithST0CCLR=1aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheSTMA0Fflag

3.TheoutputpinresettoinitialstatebyaST0ONrisingedge

4.TheSTMP0FflagisnotgeneratedwhenST0CCLR=1

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Timer/Counter ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheSTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunctionbysettingpin-sharefunctionregister.

PWM Output ModeToselectthismode,bitsST0M1andST0M0intheSTM0C1registershouldbesetto10respectivelyandalsotheST0IO1andST0IO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheSTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMoutputmode,theST0CCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycleisdeterminedusingtheST0DPXbit intheSTM0C1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheST0OCbitintheSTM0C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhiletheST0IO1andST0IO0bitsareusedtoenablethePWMoutputortoforcetheSTMoutputpintoafixedhighorlowlevel.TheST0POLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000b

Pe�iod 1�8 �56 �8� 51� 6�0 768 896 10��

Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000b

Pe�iod CCRA

Duty 1�8 �56 �8� 51� 6�0 768 896 10��

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.00 70 De�e��e� �0� �01� Rev. 1.00 71 De�e��e� �0� �01�



CCRP

CCRA

Counte�Value Counte� Clea�ed�y CCRP



STM O/P Pin(ST0OC=1)

ST0ON

PWM Duty Cy�leset �y CCRA

PWM Pe�iodset �y CCRP

Counte� Stop If ST0ON �it low

Counte� �eset when ST0ON �etu�ns high

PWM �esu�es ope�ationOutput �ont�olled �y

Othe� pin-sha�ed fun�tion

Ti�e

ST0DPX=0;ST0M[1:0]=10

ST0POL

Output Inve�tsWhen ST0POL = 1

ST0PAU

Resu�ePause


PWM Output Mode – ST0DPX = 0Note:1.HereST0DPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod

3.TheinternalPWMfunctioncontinuesrunningevenwhenST0IO[1:0]=00or01

4.TheST0CCLRbithasnoinfluenceonPWMoperation

Rev. 1.00 70 De�e��e� �0� �01� Rev. 1.00 71 De�e��e� �0� �01�



CCRA

CCRP

Counte�Value Counte� Clea�ed �y CCRA




ST0ON

PWM Duty Cy�leset �y CCRP

PWM Pe�iodset �y CCRA

Counte� Stop If ST0ON �it low

Counte� �eset when ST0ON �etu�ns high

PWM �esu�es ope�ationOutput �ont�olled �y

Othe� pin-sha�ed fun�tion

Ti�e

ST0DPX=1;ST0M[1:0]=10

ST0POL

Output Inve�tsWhen ST0POL = 1

ST0PAU

Resu�ePause


PWM Output Mode – ST0DPX = 1Note:1.HereST0DPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod

3.TheinternalPWMfunctioncontinuesevenwhenST0IO[1:0]=00or01

4.TheST0CCLRbithasnoinfluenceonPWMoperation

Rev. 1.00 7� De�e��e� �0� �01� Rev. 1.00 7� De�e��e� �0� �01�



Single Pulse ModeTo select thismode, bitsST0M1andST0M0 in theSTM0C1 register shouldbe set to 10respectivelyandalsotheST0IO1andST0IO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheST0ONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theST0ONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalSTCK0pin,whichwillinturninitiatetheSinglePulseoutput.WhentheST0ONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheST0ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheST0ONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

S/W Co��and SET“ST0ON”

o�STCK0 Pin

T�ansition

T�ailing Edge

S/W Co��and CLR“ST0ON”

o�CCRA Co�pa�e Mat�h

STP0/STP0B Output Pin

Pulse Width = CCRA Value

Leading Edge

ST0ON �it0 → 1

ST0ON �it1 → 0

Single Pulse Generation

Rev. 1.00 7� De�e��e� �0� �01� Rev. 1.00 7� De�e��e� �0� �01�



Counte� Value

CCRP

CCRA

ST0ON

ST0PAU

ST0POL

CCRP Int. Flag STMP0F

CCRA Int. Flag STMA0F


Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e

Counte� Reset when ST0ON �etu�ns high

ST0M [1:0] = 10 ; ST0IO [1:0] = 11

Pulse Width set �y CCRA

Output Inve�tswhen ST0POL = 1

No CCRP Inte��upts gene�ated


STCK0 pin

Softwa�e T�igge�

Clea�ed �y CCRA �at�h

STCK0 pin T�igge�

Auto. set �y STCK0 pin


Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse ModeNote:1.CounterstoppedbyCCRAmatch

2.CCRPisnotused

3.ThepulseistriggeredbysettingtheST0ONbithigh

4.IntheSinglePulseMode,ST0IO[1:0]mustbesetto“11”andcannotbechanged.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheST0ONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMinterrupt.ThecountercanonlyberesetbacktozerowhentheST0ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheST0CCLRandST0DPXbitsarenotusedinthisMode.

Rev. 1.00 7� De�e��e� �0� �01� Rev. 1.00 75 De�e��e� �0� �01�



Capture Input ModeToselectthismodebitsST0M1andST0M0intheSTM0C1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTP0I,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheST0IO1andST0IO0bitsintheSTM0C1register.ThecounterisstartedwhentheST0ONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.Whentherequirededge transitionappearson theSTP0I thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaSTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTP0IthecounterwillcontinuetofreerununtiltheST0ONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheST0IO1andST0IO0bitscanselecttheactivetriggeredgeontheSTP0Itobearisingedge,fallingedgeorbothedgetypes.IftheST0IO1andST0IO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTP0I,howeveritmustbenotedthatthecounterwillcontinuetorun.

TheST0CCLRandST0DPXbitsarenotusedinthisMode.

Counte� Value

YY

CCRP

ST0ON

ST0PAU

CCRP Int. Flag STMP0F

CCRA Int. Flag STMA0F

CCRA Value

Ti�e

Counte� �lea�ed �y CCRP

PauseResu�e

Counte� Reset

ST0M [1:0] = 01

STM �aptu�e pin STP0I

XX

Counte� Stop

ST0IO [1:0] Value

XX YY XX YY

A�tive edge A�tive

edgeA�tive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

Capture Input ModeNote:1.ST0M[1:0]=01andactiveedgesetbytheST0IO[1:0]bits

2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TheST0CCLRandST0DPXbitsarenotused4.Nooutputfunction–ST0OCandST0POLbitsarenotused5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

Rev. 1.00 7� De�e��e� �0� �01� Rev. 1.00 75 De�e��e� �0� �01�



Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanalsobecontrolledwithtwoexternalinputpinsandcandrivetwoexternaloutputpins.

Device Name TM Input Pin TM Output Pin

HT50F51 10-�it PTM PTCK0� PTP0IPTCK1� PTP1I

PTP0�PTP0BPTP1�PTP1B

Periodic TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearetwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRAandCCRPregisters.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclearthecounterbychangingthePTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

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Periodic Type TM Block Diagram (n=0 or 1)

Rev. 1.00 76 De�e��e� �0� �01� Rev. 1.00 77 De�e��e� �0� �01�



Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Register Name

Bit

7 6 5 4 3 2 1 0

PTMnC0 PTnPAU PTnCK� PTnCKn PTnCK0 PTnON — — —

PTMnCn PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCKS PTnCCLR

PTMnDL D7 D6 D5 D� D� D� D1 D0

PTMnDH — — — — — — D9 D8

PTMnAL D7 D6 D5 D� D� D� D1 D0

PTMnAH — — — — — — D9 D8

PTMnRPL D7 D6 D5 D� D� D� D1 D0

PTMnRPH — — — — — — D9 D8

10-bit Periodic TM Register List (n=0 or 1)

PTMnC0 Register

Bit 7 6 5 4 3 2 1 0

Na�e PTnPAU PTnCK� PTnCK1 PTnCK0 PTnON — — —

R/W R/W R/W R/W R/W R/W — — —

POR 0 0 0 0 0 — — —

Bit7 PTnPAU:PTMCounterPauseControl0:run1:pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 PTnCK2~PTnCK0:SelectPTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:PTCKnrisingedgeclock111:PTCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefTBCisanotherinternalclock,thedetailsofwhichcanbefoundintheoscillatorsection.

Rev. 1.00 76 De�e��e� �0� �01� Rev. 1.00 77 De�e��e� �0� �01�



Bit3 PTnON:PTMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTMOutputcontrolbit,whenthebitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

PTMnC1 Register

Bit 7 6 5 4 3 2 1 0

Na�e PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCKS PTnCCLR

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit7~6 PTnM1~ PTnM0:SelectPTMOperationMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to thePTnM1andPTnM0bits.IntheTimer/CounterMode,thePTMoutputpinstateisundefined.

Bit5~4 PTnIO1~ PTnIO0:SelectPTMoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofPTPnI01:InputcaptureatfallingedgeofPTPnI10:Inputcaptureatfalling/risingedgeofPTPnI11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

Rev. 1.00 78 De�e��e� �0� �01� Rev. 1.00 79 De�e��e� �0� �01�



In theCompareMatchOutputMode, thePTnIO1andPTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccurs fromtheComparatorA.When thesebitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingthePTnOCbit.NotethattheoutputlevelrequestedbythePT1IO1andPTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingthelevelofthePTnONbitfromlowtohigh.InthePWMMode,thePTnIO1andPTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesofthePTnIO1andPTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurifthePTnIO1andPTnIO0bitsarechangedwhentheTMisrunning.

Bit3 PTnOC:PTPn/PTPnBOutputcontrolbitCompareMatchOutputMode0:initiallow1:initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 PTnPOL:PTPn/PTPnBOutputpolarityControl0:non-invert1:invert

ThisbitcontrolsthepolarityofthePTPn/PTPnBoutputpin.WhenthebitissethightheTMoutputpinwillbe invertedandnot invertedwhenthebit iszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 PTnCKS:PTMcapturetriggersourceselect0:FromPTPnI1:FromPTCKnpin

Bit0 PTnCCLR:SelectPTMCounterclearcondition0:PTMComparatrorPmatch1:PTMComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththePTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTnCCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.00 78 De�e��e� �0� �01� Rev. 1.00 79 De�e��e� �0� �01�



PTMnDL Register

Bit 7 6 5 4 3 2 1 0

Na�e D7 D6 D5 D� D� D� D1 D0

R/W R R R R R R R R

POR 0 0 0 0 0 0 0 0

Bit7~0 PTMnDL:PTMCounterLowByteRegisterbit7~bit0PTM10-bitCounterbit7~bit0

PTMnDH Register

Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8

R/W — — — — — — R R

POR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 PTMnDH:PTMCounterHighByteRegisterbit1~bit0

PTM10-bitCounterbit9~bit8

PTMnAL Register

Bit 7 6 5 4 3 2 1 0

Na�e D7 D6 D5 D� D� D� D1 D0


POR 0 0 0 0 0 0 0 0

Bit7~0 PTMnAL:PTMCCRALowByteRegisterbit7~bit0PTM10-bitCCRAbit7~bit0

PTMnAH Register

Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8

R/W — — — — — — R/W R/W

POR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 PTMnAH:PTMCCRAHighByteRegisterbit1~bit0

PTM10-bitCCRAbit9~bit8

PTMnRPL Register

Bit 7 6 5 4 3 2 1 0

Na�e D7 D6 D5 D� D� D� D1 D0


POR 0 0 0 0 0 0 0 0

Bit7~0 PTMnRPL:PTMCCRPLowByteRegisterbit7~bit0PTM10-bitCCRPbit7~bit0

Rev. 1.00 80 De�e��e� �0� �01� Rev. 1.00 81 De�e��e� �0� �01�



PTMnRPH Register

Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — D9 D8

R/W — — — — — — R/W R/W

POR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 PTMnRPH:PTMCCRPHighByteRegisterbit1~bit0

PTM10-bitCCRPbit9~bit8

Periodic Type TM Operating ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTnM1andPTnM0bitsinthePTMnC1register.

Compare Match Output ModeToselect thismode,bitsPTnM1andPTnM0in thePTMnC1register, shouldbeallcleared to00respectively.In thismodeoncethecounter isenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththePTMAnFandPTMPnFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IfthePTnCCLRbitinthePTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly thePTMAnFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTnCCLRishighnoPTMPnF interrupt request flagwillbegenerated. In theCompareMatchOutputMode,theCCRAcannotbesetto“0”.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverherethePTMAnFinterruptrequestflagwillnotbegenerated.

Asthenameofthemodesuggests,afteracomparisonismade,theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaPTMAnFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPnFinterruptrequestflag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstatearedeterminedbytheconditionofthePTnIO1andPTnIO0bits in thePTMnC1register.TheTMoutputpincanbeselectedusing thePTnIO1andPTnIO0bits togohigh, togo lowor to togglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheTMoutputpin,whichissetupafterthePTnONbitchangesfromlowtohigh,issetupusingthePTnOCbit.Notethatif thePTnIO1,PTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.00 80 De�e��e� �0� �01� Rev. 1.00 81 De�e��e� �0� �01�



Counte� Value

0x�FF

CCRP

CCRA

PTnON

PTnPAU

PTnPOL

CCRP Int. Flag PTMPnF

CCRA Int. Flag PTMAnF

PTM O/P Pin

Ti�e

CCRP=0

CCRP > 0

Counte� ove�flowCCRP > 0Counte� �lea�ed �y CCRP value

Pause

Resu�e

Stop

Counte� Resta�t

PTnCCLR = 0; PTnM [1:0] = 00

Output pin set to initial Level Low if PTnOC=0

Output Toggle with PTMAnF flag

Note PTnIO [1:0] = 10 A�tive High Output sele�tHe�e PTnIO [1:0] = 11

Toggle Output sele�t

Output not affe�ted �y PTMAnF flag. Re�ains High until �eset �y PTnON �it

Output PinReset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�tswhen PTnPOL is high

Compare Match Output Mode – PTnCCLR = 0 (n=0 or 1)Note:1.WithPTnCCLR=0–aComparatorPmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybythePTMAnFflag

3.TheoutputpinisresettoinitialstatebyaPTnONbitrisingedge

Rev. 1.00 8� De�e��e� �0� �01� Rev. 1.00 8� De�e��e� �0� �01�



Counte� Value

0x�FF

CCRP

CCRA

PTnON

PTnPAU

PTnPOL



PTM O/P Pin

Ti�e

CCRA=0

CCRA = 0Counte� ove�flowCCRA > 0 Counte� �lea�ed �y CCRA value

Pause

Resu�e

Stop Counte� Resta�t

PTnCCLR = 1; PTnM [1:0] = 00

Output pin set to initial Level Low if PTnOC=0

Output Toggle with PTMAnF flag

Note PTnIO [1:0] = 10 A�tive High Output sele�tHe�e PTnIO [1:0] = 11

Toggle Output sele�t

Output not affe�ted �y TnAF flag. Re�ains High until �eset �y PTnON �it

Output PinReset to Initial value

Output �ont�olled �y othe� pin-sha�ed fun�tion

Output Inve�tswhen PTnPOL is high

PTMPnF not gene�ated

No PTMAnF flag gene�ated on CCRA ove�flow

Output does not �hange

Compare Match Output Mode – PTnCCLR = 1 (n=0 or 1)Note:1.WithPTnCCLR=1–aComparatorAmatchwillclearthecounter

2.TheTMoutputpiniscontrolledonlybythePTMAnFflag

3.TheoutputpinisresettoinitialstatebyaPTnONrisingedge

4.ThePTMPnFflagisnotgeneratedwhenPTnCCLR=1

Rev. 1.00 8� De�e��e� �0� �01� Rev. 1.00 8� De�e��e� �0� �01�



Timer/Counter ModeToselect thismode,bitsPTnM1andPTnM0 in thePTMnC1register shouldallbe set to11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsPTnM1andPTnM0inthePTMnC1registershouldbesetto10respectivelyandalsothePTnIO1andPTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,thePTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTnOCbitinthePTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTnIO1andPTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.ThePTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit PWM Mode, Edge-aligned ModeCCRP CCRP = 0~1024

Pe�iod CCRP=0 : pe�iod= 10�� lo�ksCCRP=1~10��: pe�iod=1~10�� lo�ks

Duty CCRA

IffSYS=16MHz,PTMclocksourceselectfSYS/4,CCRP=100bandCCRA=128,

ThePTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

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Counte� Value

CCRP

CCRA

PTnON

PTnPAU

PTnPOL



PTM O/P Pin(PTnOC=1)

Ti�e


Pause Resu�e Counte� Stop if PTnON �it low

Counte� Reset when PTnON �etu�ns high

PTnDPX = 0; PTnM [1:0] = 10

PWM Duty Cy�le set �y CCRA

PWM �esu�es ope�ation

Output �ont�olled �y othe� pin-sha�ed fun�tion Output Inve�ts

When PTnPOL = 1PWM Pe�iod set �y CCRP


PWM Output Mode (n=0 or 1)Note:1.HereCounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod

3.TheinternalPWMfunctioncontinuesrunningevenwhenPTnIO[1:0]=00or01

4.ThePTnCCLRbithasnoinfluenceonPWMoperation

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Single Pulse Output ModeToselectthismode,therequiredbitpairs,PTnM1andPTnM0shouldbesetto10respectivelyandalsothecorrespondingPTnIO1andPTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalPTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhenthePTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTnCCLRbitisalsonotused.

S/W Co��and SET“PTnON”

o�PTCKn Pin

T�ansition

T�ailing Edge

S/W Co��and CLR“PTnON”

o�CCRA Co�pa�e Mat�h

PTPn/PTPnB Output Pin

Pulse Width = CCRA Value

Leading Edge

PTnON �it0 → 1

PTnON �it1 → 0

Single Pulse Generation (n=0 or 1)

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Counte� Value

CCRP

CCRA

PTnON

PTnPAU

PTnPOL




Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e

Counte� Reset when PTnON �etu�ns high

PTnM [1:0] = 10 ; PTnIO [1:0] = 11

Pulse Width set �y CCRA

Output Inve�tswhen PTnPOL = 1

No CCRP Inte��upts gene�ated


PTCKn pin


Clea�ed �y CCRA �at�h

PTCKn pin T�igge�

Auto. set �y PTCKn pin


Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

Single Pulse Mode Note:1.CounterstoppedbyCCRA

2.CCRPisnotused

3.ThepulseistriggeredbythePTCKnpinorbysettingthePTnONbithigh

4.APTCKnpinactiveedgewillautomaticallysetthePTnONbithigh

5.IntheSinglePulseMode,PTnIO[1:0]mustbesetto“11”andcannotbechanged.

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Capture Input ModeToselectthismodebitsPTnM1andPTnM0inthePTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPnIorPTCKnpin,selectedbythePTnCKSbitinthePTMnC1register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTnIO1andPTnIO0bitsinthePTMnC1register.ThecounterisstartedwhenthePTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsonthePTPnIorPTCKnpin thepresentvalue in thecounterwillbelatchedintotheCCRAregisterandaTMinterruptgenerated.IrrespectiveofwhateventsoccuronthePTPnIorPTCKnpinthecounterwillcontinuetofreerununtilthePTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTnIO1andPTnIO0bitscanselecttheactivetriggeredgeonthePTPnIorPTCKnpintobearisingedge,fallingedgeorbothedgetypes.IfthePTnIO1andPTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPnIorPTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AsthePTPnIorPTCKnpinispinsharedwithotherfunctions,caremustbetakenifthePTMisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTnCCLR,PTnOCandPTnPOLbitsarenotusedinthisMode.

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Counte� Value

YY

CCRP

PTnON

PTnPAU



CCRA Value

Ti�e


PauseResu�e

Counte� Reset

PTnM [1:0] = 01

PTM �aptu�e pin PTPnIo� PTCKn

XX

Counte� Stop

PTnIO [1:0] Value

XX YY XX YY

A�tive edge A�tive

edgeA�tive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

Capture Input Mode (n=0 or 1)Note:1.PTnM[1:0]=01andactiveedgesetbythePTnIO[1:0]bits

2.ATMCaptureinputpinactiveedgetransferscountervaluetoCCRA

3.ThePTnCCLRbitisnotused

4.Nooutputfunction–PTnOCandPTnPOLbitsarenotused

5.CCRPdetermines thecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero

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Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicescontainamulti-channelanalog todigital converterwhichcandirectly interfacetoexternalanalogsignals, suchas that fromsensorsorothercontrolsignalsandconvert thesesignalsdirectlyintoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINSandSACSbitfields.Notethatwhentheinternalanalogsignalistobeconverted, thepin-sharedcontrolbitsshouldalsobeproperlyconfiguredexcept theSAINSandSACSbit fields.Moredetailedinformationabout theA/Dinputsignal isdescribedin the“A/DConverterControlRegisters”and“A/DConverterInputSignal”sectionsrespectively.

Part No. Input Channels A/D Channel Select Bits Input Pins

HT50F50 � SAINS�~SAINS0�SACS1~SACS0 AN0~AN�

HT50F51 8 SAINS�~SAINS0�SACS�~SACS0 AN0~AN7

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

AN0AN5AN6AN7

1�-�it SAR ADC

ENADC

SADOH[7:0]SADOL[7:0]

ADBZ

SAINT

SACS[�:0]

VBG(1.0�V)

VREFVRI

Divide� fSYS

SACKS[�:0]

AVDD

SAVRS[�:0]

VR

VREFO

SAINS[�:0]

SAPIN

VREFO

ENOPAPASR

OPA

MUX

Pin-sha�ed sele�tion

AVDD

VR

A/D Converter Structure

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A/D Converter Register DescriptionOveralloperationoftheA/Dconverter iscontrolledusingfiveregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingthreeregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

NameBit

7 6 5 4 3 2 1 0SADOL (ADRFS=0) D� D� D1 D0 — — — —

SADOL (ADRFS=1) D7 D6 D5 D� D� D� D1 D0

SADOH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D�

SADOH (ADRFS=1) — — — — D11 D10 D9 D8

SADC0 START ADBZ ENADC ADRFS — — SACS1 SACS0SADC1 SAINS� SAINS1 SAINS0 — — SACK� SACK1 SACK0SADC� ENOPA VBGEN — — SAVRS� SAVRS� SAVRS1 SAVRS0

A/D Converter Register List – HT50F50

NameBit

7 6 5 4 3 2 1 0SADOL (ADRFS=0) D� D� D1 D0 — — — —

SADOL (ADRFS=1) D7 D6 D5 D� D� D� D1 D0

SADOH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D�

SADOH (ADRFS=1) — — — — D11 D10 D9 D8

SADC0 START ADBZ ENADC ADRFS — SACS� SACS1 SACS0SADC1 SAINS� SAINS1 SAINS0 — — SACKS� SACKS1 SACKS0SADC� ENOPA VBGEN — — SAVRS� SAVRS� SAVRS1 SAVRS0

A/D Converter Register List – HT50F51

A/D Converter Data Registers – SADOL, SADOHAsthedevicescontainaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.NotethattheA/DconverterdataregistercontentswillbeclearedtozeroiftheA/Dconverterisdisabled.

ADRFSSADOH SADOL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D7 D6 D5 D� D� D� D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D� D� D� D1 D0

A/D Data Registers

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A/D Converter Control Registers – SADC0, SADC1, SADC2, PASR, PBSRTocontrol thefunctionandoperationof theA/Dconverter,severalcontrol registersknownasSADC0,SADC1andSADC2areprovided.These8-bit registersdefine functionssuchas theselectionofwhichanalogchannel isconnected to the internalA/Dconverter, thedigitiseddataformat, theA/Dclocksourceaswellascontrolling thestart functionandmonitoring theA/Dconverterbusystatus.TheSACS2~SACS0bitsintheSADC0registerareusedtodeterminewhichexternalchannelinputisselectedtobeconverted.TheSAINS2~SAINS0bitsintheSADC1registerareusedtodeterminethattheanalogsignaltobeconvertedcomesfromtheinternalanalogsignalorexternalanalogchannelinput.IftheSAINS2~SAINS0bitsaresetto“000”,theexternalanalogchannelinputisselectedtobeconvertedandtheSACS2~SACS0bitscandeterminewhichexternalchannelisselectedtobeconverted.If theSAINS2~SAINS0bitsareset to“001~011”, theAVDDvoltage isselected tobeconverted. If theSAINS2~SAINS0bitsareset to“101~111”, theOPAoutputvoltageisselectedtobeconverted.WhenVREForVBG isselectedasADCinputorADCreferencevoltage,theOPAneedstobeenabledbysettingENOPAto1.

Note thatwhen theprogramsselectexternalsignaland internalsignalasanADCinputsignalsimultaneously,thenthehardwarewillonlychoosetheinternalsignalasanADCinput.Inaddition,iftheprogramsselectexternalreferencevoltageVREFandtheinternalreferencevoltageVBGasADCreferencevoltage,thenthehardwarewillonlychoosetheinternalreferencevoltageVBGasanADCreferencevoltageinput.

Caremustbetakenwhentheinternalanalogsignalisselectedtobeconverted.Iftheinternalanalogsignalisselectedtobeconverted,theselectedexternalinputpindeterminedbytheSACS2~SACS0bitsmustneverbeconfiguredasA/Dinputfunctionbyproperlysetting therelevantpin-sharedcontrolbits.Otherwise, theexternalchannel inputwillbeconnected togetherwith the internalanalogsignal.Thiswillresultinunpredictablesituationssuchasanirreversibledamage.

Thepin-sharedfunctioncontrolregisters,namedPASRandPBSR,containthecorrespondingpin-sharedselectionbitswhichdeterminewhichpinsonPortAandPortBareusedasanaloginputsfor theA/Dconverterinputandwhichpinsarenot tobeusedastheA/Dconverterinput.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

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SADC0 Register – HT50F50Bit 7 6 5 4 3 2 1 0

Na�e START ADBZ ENADC ADRFS — — SACS1 SACS0R/W R/W R R/W R/W — — R/W R/WPOR 0 0 0 0 — — 0 0

Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion0→1:ResettheA/DconverterandsetADBZto01→0:StartA/DconversionandsetADBZto1

Bit6 ADBZ:ADCbusyflag0:A/Dconversionendedornoconversion1:A/Disbusy

Bit5 ENADC:ADCenable/disablecontrolregister0:ADCdisable1:ADCenable

Bit4 ADRFS:A/Doutputdataformatselectionbit0:ADCoutputdataformat→SADOH=D[11:4];SADOL=D[3:0]1:ADCoutputdataformat→SADOH=D[11:8];SADOL=D[7:0]

Bit3~2 Unimplemented,readas"0"Bit1~0 SACS1~SACS0:ADCinputchannelsselection

00:ADCinputchannelcomesfromAN001:ADCinputchannelcomesfromAN110:ADCinputchannelcomesfromAN211:ADCinputchannelcomesfromAN3

SADC0 Register – HT50F51Bit 7 6 5 4 3 2 1 0

Na�e START ADBZ ENADC ADRFS — SACS� SACS1 SACS0R/W R/W R R/W R/W — R/W R/W R/WPOR 0 0 0 0 — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion0→1:ResettheA/DconverterandsetADBZto01→0:StartA/DconversionandsetADBZto1

Bit6 ADBZ:ADCbusyflag0:A/Dconversionendedornoconversion1:A/Disbusy

Bit5 ENADC:ADCenable/disablecontrolregister0:ADCdisable1:ADCenable

Bit4 ADRFS:A/Doutputdataformatselectionbit0:ADCoutputdataformat→SADOH=D[11:4];SADOL=D[3:0]1:ADCoutputdataformat→SADOH=D[11:8];SADOL=D[7:0]

Bit3~2 Unimplemented,readas“0”Bit1~0 SACS2~SACS0:ADCinputchannelsselection

000:ADCinputchannelcomesfromAN0001:ADCinputchannelcomesfromAN1010:ADCinputchannelcomesfromAN2011:ADCinputchannelcomesfromAN3100:ADCinputchannelcomesfromAN4101:ADCinputchannelcomesfromAN5110:ADCinputchannelcomesfromAN6111:ADCinputchannelcomesfromAN7

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SADC1 RegisterBit 7 6 5 4 3 2 1 0

Na�e SAINS� SAINS1 SAINS0 — — SACKS� SACKS1 SACKS0R/W R/W R/W R/W — — R/W R/W R/WPOR 0 0 0 — — 0 0 0

Bit7~5 SAINS2~SAINS0:InternalADCinputchannelselectionbit000:ADCinputonlycomesfromexternalpin001:ADCinputalsocomesfromAVDD

010:ADCinputalsocomesfromAVDD/2011:ADCinputalsocomesfromAVDD/4101:ADCinputalsocomesfromVR

110:ADCinputalsocomesfromVR/2111:ADCinputalsocomesfromVR/4OtherValues:thesameas“000”

Note:VRisOPAoutputvoltage.VRcanbeoneofVREF/VREF×2/VREF×3/VREF×4/VBG×2/VBG×3/VBG×4.

Bit4~3 Unimplemented,readas"0"Bit2~0 SACKS2~SACKS0:ADCclockrateselectionbit

000:SACLK=fSYS

001:SACLK=fSYS/2010:SACLK=fSYS/4011:SACLK=fSYS/8100:SACLK=fSYS/16101:SACLK=fSYS/32110:SACLK=fSYS/64111:SACLK=fSYS/128

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SADC2 RegisterBit 7 6 5 4 3 2 1 0

Na�e ENOPA VBGEN — — SAVRS� SAVRS� SAVRS1 SAVRS0R/W R/W R/W — — R/W R/W R/W R/WPOR 0 0 — — 0 0 0 0

Bit7 ENOPA:OPAenable/disablecontrolregister0:OPAdisable1:OPAenable

Bit6 VBGEN:Bandgapbufferdisable/enablecontrolbit0:Bandgapbufferdisable1:Bandgapbufferenable

Bit5~4 Unimplemented,readas“0”Bit3~0 SAVRS3~SAVRS0:ADCreferencevoltageselectionbit

0000:ADCreferencevoltagecomesfromAVDD

0001:ADCreferencevoltagecomesfromVREF

0010:ADCreferencevoltagecomesfromVREF×20011:ADCreferencevoltagecomesfromVREF×30100:ADCreferencevoltagecomesfromVREF×41001:Inhibittouse1010:ADCreferencevoltagecomesfromVBG×21011:ADCreferencevoltagecomesfromVBG×31100:ADCreferencevoltagecomesfromVBG×4OtherValues:sameas“0000”

Note:(1)WhenSelectVREForVREF×2orVREF×3orVREF×4asADCreferencevoltage,HT50F50:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput.HT50F51:pinsharecontrolbits(PAS3,PAS2)is(1,0)toselectVREFasinput

(2)VBG=1.04V(3)WhenSAVRS3=1,OPAselectsVBGasinput.(4) If theprogramsselectexternal referencevoltageVREFand the internal

referencevoltageVBGasADCreferencevoltage,thenthehardwarewillonlychoosetheinternalreferencevoltageVBGasanADCreferencevoltageinput.

A/D OperationTheSTARTbitisusedtostartandresettheA/Dconverter.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,theADBZbitintheSADC0registerwillbeclearedtozeroandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.

TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocess is inprocessornot.When theA/Dconverter is resetbysetting theSTARTbit fromlowtohigh, theADBZflagwillbeclearedto0.Thisbitwillbeautomaticallyset to“1”bythemicrocontrollerafteranA/Dconversion issuccessfully initiated.When theA/Dconversion iscomplete,theADBZwillbeclearedto0.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

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AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsSACK2~SACK0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedvalueofpermissibleA/Dclockperiod, tADCK, isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample, if thesystemclockoperatesatafrequencyof4MHz,theSACK2~SACK0bitsshouldnotbesetto000Bor11xB.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theENADCbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheENADCbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/Dinputsbyconfiguringthecorrespondingpin-sharedcontrolbits,iftheENADCbitishighthensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheENADCissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeithertheinternalADCpowerorfromanexternalreferencesourcessuppliedonpinVREForVBGvoltage.ThedesiredselectionismadeusingtheSAVRS3~SAVRS0bits.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFpinisselectedasthereferencevoltagesupplypin,theVREFpin-sharedfunctioncontrolbitsshouldbeproperlyconfiguredtodisableotherpinfunctions.WhenVREForVBGisselectedbyADCinputorADCreferencevoltage,theOPAneedstobeenabledbysettingENOPA=1.

Reference SAVRS[3:0] Description

AVDD 0000 ADC Refe�en�e Voltage �o�es f�o� AVDD

VREF 0001 ADC Refe�en�e Voltage �o�es f�o� Exte�nal VREF

VREF×� 0010 ADC Refe�en�e Voltage �o�es f�o� Exte�nal VREF×�VREF×� 0011 ADC Refe�en�e Voltage �o�es f�o� Exte�nal VREF×�VREF×� 0100 ADC Refe�en�e Voltage �o�es f�o� Exte�nal VREF×�VBG×� 1010 ADC Refe�en�e Voltage �o�es f�o� VBG×�VBG×� 1011 ADC Refe�en�e Voltage �o�es f�o� VBG×�VBG×� 1100 ADC Refe�en�e Voltage �o�es f�o� VBG×�

A/D Converter Reference Voltage Selection

A/D Converter Input SignalAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortAandPortBaswellasotherfunctions.ThecorredpondingselectionbitsforeachI/OpininthePASRandPBSRregisters,determinewhether theinputpinsaresetupasA/Dconverteranaloginputsorwhether theyhaveotherfunctions.If thepin-sharedfunctioncontrolbitsconfigureitscorrespondingpinasanA/Danalogchannelinput, thepinwillbesetuptobeanA/Dconverterexternalchannelinputandtheoriginalpinfunctionsdisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheir functionbetweenA/Dinputsandother functions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnected if thepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePACandPBCportcontrolregistertoenabletheA/Dinputaswhenthepin-sharedfunctioncontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheSAVRS[3:0]intheSADC2register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

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Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanA/DconversionwhichisdefinedastADCarenecessary.

MaximumsingleA/Dconversionrate=A/Dclockperiod/16

However, there isausagelimitationonthenextA/Dconversionafter thecurrentconversioniscomplete.WhenthecurrentA/Dconversioniscomplete, theconverteddigitaldatawillbestoredintheA/DdataregisterpairandthenlatchedafterhalfanA/Dclockcycle.IftheSTARTbitissetto1inhalfanA/DclockcycleaftertheendofA/Dconversion,theconverteddigitaldatastoredintheA/Ddataregisterpairwillbechanged.Therefore,it isrecommendedtoinitiatethenextA/DconversionafteracertainperiodgreaterthanhalfanA/DclockcycleattheendofcurrentA/Dconversion.

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A/D Conversion Timing

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Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionfrequencybySACKS2~SACKS0

• Step2EnabletheADCbysetENADC=1

• Step3SelectwhichpinswillbeconfigureasADCanaloginputs

• Step4IfinputcomesfromI/O,setSAINS[2:0]=000andthensetSACSbitfieldstocorrespondingPADinputIfinputcomesfrominternalinput,setSAINS[2:0]tocorrespondinginternalinputsource

• Step5SelectreferencevoltagecomesfromexternalVREF,AVDDorVBGbySAVRS[3:0]Note:IfselectVREFasreferencevoltage,(PAS3,PAS2)=(1,0)

• Step6SelectADCoutputdataformatbyADRFS

• Step7IfADCinterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbits,ADE,mustbothsethighinadvance.

• Step8TheA/DconvertprocedurecannowbeinitializedbysetSTARTfromlowtohighandthenlowagain

• Step9IfADCisunderconversion,ADBZ=1.AfterA/Dconversionprocessiscompleted,theADBZflagwillgolow,andthenoutputdatacanbereadfromSADOHandSADOLregisters.If theADCinterrupt isenabledandthestack isnotfull,datacanbeacquiredby interruptserviceprogram.AnotherwaytogettheA/DoutputdataispollingtheADBZflag.

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Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,byclearing theENADCbit in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.

1LSB=(AVDDorVREF)/4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(AVDDorVREF)/4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

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Ideal A/D Transfer Function

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A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,0BHmov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference voltageset ENADCmov a,03h ; setup PASR to configure pin AN0mov PASR,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converter:start_conversion:clr START ; high pulse on start bit to initiate conversionset START ; reset A/Dclr START ; start A/Dpolling_EOC:sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversionjmp polling_EOC ; continue pollingmov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register::jmp start_conversion ; start next a/d conversion

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Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,0BHmov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference voltageset ENADCmov a,03h ; setup PASR to configure pin AN0mov PASR,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converterStart_conversion:clr START ; high pulse on START bit to initiate conversionset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset ADE ; enable ADC interruptset EMI ; enable global interrupt::; ADC interrupt service routineADC_ISR:mov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory::mov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryreti

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InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicescontainseveralexternalinterruptsandinternal interruptsfunctions.Theexternal interruptsaregeneratedbytheactionoftheexternalINT0~INT1andINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,TimeBase,EEPROMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0registerwhichsetuptheMulti-functioninterrupt.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlo�al EMI — —INT Pin INTE INTF —

A/D Conve�te� ADE ADF —Multi-fun�tion MF0E MF0F —

Ti�e Base TBnE TBnF n=0 o� 1EEPROM DEE DEF —

TMSTMA0E STMA0F

—STMP0E STMP0F

Interrupt Register Bit Naming Conventions – HT50F50

Function Enable Bit Request Flag NotesGlo�al EMI — —

INTn Pin INTnE INTnF n=0 o� 1A/D Conve�te� ADE ADF —Multi-fun�tion MF0E MF0F —

Ti�e Base TBnE TBnF n=0 o� 1EEPROM DEE DEF —

TMPTMAnE PTMAnF

n=0 o� 1PTMPnE PTMPnF

Interrupt Register Bit Naming Conventions – HT50F51

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Interrupt Register Contents• HT50F50

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — — — INT0S1 INT0S0INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMIINTC1 — ADF DEF MF0F — ADE DEE MF0EMFI0 — — STMA0F STMP0F — — STMA0E STMP0E

• HT50F51

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — TB1F TB0F INT0F TB1E TB0E INT0E EMIINTC1 INT1F ADF DEF MF0F INT1E ADE DEE MF0EMFI0 PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0E

INTEG Register – HT50F50Bit 7 6 5 4 3 2 1 0

Na�e — — — — — — INT0S1 INT0S0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 INT0S1, INT0S0:DefinesINTinterruptactiveedge

00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

INTEG Register – HT50F51Bit 7 6 5 4 3 2 1 0

Na�e — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1, INT1S0:DefinesINT1interruptactiveedge

00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

Bit1~0 INT0S1, INT0S0:DefinesINT0interruptactiveedge00:DisableInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

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INTC0 Register – HT50F50Bit 7 6 5 4 3 2 1 0

Na�e — TB1F TB0F INTF TB1E TB0E INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 TB1F :TimeBase1InterruptRequestFlag

0:Norequest1:Interruptrequest

Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INTF:INTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 TB1E :TimeBase1InterruptControl0:Disable1:Enable

Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable

Bit1 INTE:INTInterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

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Na�e — TB1F TB0F INT0F TB1E TB0E INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 TB1F:TimeBase1InterruptRequestFlag


Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 TB1E :TimeBase1InterruptControl0:Disable1:Enable

Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable

Bit1 INT0E:INT0InterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable


Na�e — ADF DEF MF0F — ADE DEE MF0ER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas"0"Bit6 ADF:A/DConverterInterruptRequestFlag


Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 Unimplemented,readas"0"Bit2 ADE:A/DConverterInterruptControl

0:Disable1:Enable

Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable

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Na�e INT1F ADF DEF MF0F INT1E ADE DEE MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 INT1F:INT1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 MF0F:Multi-function0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 INT1E:INT1InterruptControl0:Disable1:Enable

Bit2 ADE:A/DConverterInterruptControl0:Disable1:Enable

Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit0 MF0E:Multi-function0InterruptControl0:Disable1:Enable

MFI0 Register – HT50F50Bit 7 6 5 4 3 2 1 0

Na�e — — STMA0F STMP0F — — STMA0E STMP0ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 STMA0F:STMComparatorAmatchinterruptrequestflag


Bit4 STMP0F:STMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 STMA0E:STMComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 STMP0E:STMComparatorPmatchinterruptcontrol0:Disable1:Enable

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MFI0 Register – HT50F51Bit 7 6 5 4 3 2 1 0

Na�e PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 PTMA1F:TM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 PTMP1F:TM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 PTMA0F:TM0ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 PTMP0F:TM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 PTMA1E:TM1ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit2 PTMP1E:TM1ComparatorPmatchinterruptcontrol0:Disable1:Enable

Bit1 PTMA0E:TM0ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit0 PTMP0E:TM0ComparatorPmatchinterruptcontrol0:Disable1:Enable

Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchorA/Dconversioncompletionetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

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Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

INT Pin

Ti�e Base 0

INTF

TB0F

INTE

TB0E

EMI 0�H

EMI 08H

EEPROM DEF DEE

0CH

10H

1�H

18H

Inte��upt Na�e Request Flags Ena�le Bits Maste�

Ena�le Vector

EMI auto disa�led in ISR

P�io�ity

High

Low

xxE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

EMI

EMI

STM P STMP0F STMP0E

STM A STMA0F STMA0EEMI

EMITi�e Base 1 TB1F TB1E

M. Fun�t. 0 MF0F MF0E

A/D ADF ADE

Inte��uptNa�e

RequestFlags

Ena�leBits

Inte��upts �ontained within Multi-Fun�tion Inte��upt

Interrupt Structure – HT50F50

INT0 Pin

Ti�e Base 0

INT0F

TB0F

INT0E

TB0E

EMI 0�H

EMI 08H

EEPROM DEF DEE

0CH

10H

1�H

18H

1CH

Inte��upt Na�e Request Flags Ena�le Bits Maste�

Ena�le Vector

EMI auto disa�led in ISR

P�io�ity

High

LowINT1 Pin INT1F INT1E

Inte��upts �ontained within Multi-Fun�tion Inte��upts

xxE Ena�le Bits

xxF Request Flag� auto �eset in ISR

LegendxxF Request Flag� no auto �eset in ISR

EMI

EMI

EMI

PTM0 P PTMP0F PTMP0E

PTM0 A PTMA0F PTMA0E EMI

EMITi�e Base 1 TB1F TB1E

M. Fun�t. 0 MF0F MF0E

A/D ADF ADE

PTM1 P PTMP1F PTMP1E

PTM1 A PTMA1F PTMA1E

Inte��uptNa�e

RequestFlags

Ena�leBits

Interrupt Structure – HT50F51

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External InterruptTheexternal interrupt iscontrolledbysignal transitionson thepins INTandINT0~INT1.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag,INTnF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtotheinterruptvectoraddress, theglobalinterruptenablebit,EMI,andtheexternalinterruptenablebit,INTnE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwith I/Opins, theycanonlybeconfiguredasexternal interruptpinsbysetting thepin-sharedregisters.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whenthe interrupt isserviced, theexternal interrupt request flag, INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableother interrupts.Notethat thepull-highresistorselectionontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Multi-function InterruptWithinthesedevicesthereisMulti-functioninterrupt.Unliketheotherindependentinterrupts,thisinterrupthavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflag,MF0F.TheMulti-function interrupt flagwillbesetwhenanyof their includedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecall tooneoftheMulti-functioninterruptvectorwill takeplace.Whentheinterruptisserviced, therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenoted that,althoughtheMulti-functionInterruptflagwillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupt,namelytheTMInterrupts,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

A/D Converter InterruptThedevicescontainanA/Dconverterwhichhasitsownindependentinterrupt.TheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwill takeplacewhentheA/DConverterInterruptrequestflag,ADF, isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

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Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

TBC RegisterBit 7 6 5 4 3 2 1 0

Na�e TBON TBCK TB11 TB10 — TB0� TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1

Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11 ~ TB10:SelectTimeBase1Time-outPeriod00:4096/fTB

01:8192/fTB

10:16384/fTB

11:32768/fTB

Bit3 Unimplemented,readas"0"Bit2~0 TB02 ~ TB00:SelectTimeBase0Time-outPeriod

000:256/fTB

001:512/fTB

010:1024/fTB

011:2048/fTB

100:4096/fTB

101:8192/fTB

110:16384/fTB

111:32768/fTB

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EEPROM InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,andtheEEPROMinterruptrequestflag,DEF,willalsobeautomaticallycleared.

TM InterruptsTheTMseachhastwointerrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupt.ForeachoftheTMstherearetwointerruptrequestflagsxTMPnFandxTMAnFandtwoenablebitsxTMPnEandxTMAnE.ATMinterruptrequestwill takeplacewhenanyof theTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MF0E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMF0Fflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Interrupt Wake-up FunctionEachoftheinterruptfunctionshasthecapabilityofwakingupthemicrocontrollerwhenintheSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpin,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine is executed, asonly theMulti-function interrupt request flag,MF0F,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

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Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

SCOM Function for LCDTheHT50F51devicehasthecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM3,arepinsharedwithcertainpinontheI/Oports.TheLCDsignalsaregeneratedusingtheapplicationprogram.

LCD OperationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguringtheI/Opinsascommonpins.TheLCDdriverfunctioniscontrolledusingtheSCOMCregisterwhichinadditiontocontrollingtheoverallon/offfunctionalsocontrolsthebiasvoltagesetupfunction.ThisenablestheLCDCOMdrivertogeneratethenecessaryVDD/2voltagelevelsforLCD1/2biasoperation.

TheSCOMENbit in theSCOMCregister is theoverallmastercontrol for theLCDdriver.TheLCDSCOMnpinisselectedtobeusedforLCDdrivingbythecorrespondingpin-sharedfunctionselectionbits.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.

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LCD COM Bias

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LCD Bias Current ControlTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhicharebeingused.Thebiasresistorchoice is implementedusingtheISEL1andISEL0bitsintheSCOMCregister.

SCOMCBit 7 6 5 4 3 2 1 0

Na�e — ISEL1 ISEL0 SCOMEN COM�EN COM�EN COM1EN COM0ENR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~5 ISEL1~ISEL0:SelectresistorforRtypeLCDbiascurrent(VDD=5V)

00:2×100kΩ(1/2Bias),IBIAS=25μA01:2×50kΩ(1/2Bias),IBIAS=50μA10:2×25kΩ(1/2Bias),IBIAS=100μA11:2×12.5kΩ(1/2Bias),IBIAS=200μA

Bit4 SCOMEN:LCDcontrolbit0:Disable1:Enable

WhenSCOMENisset,itwillturnontheDCpathofresistortogenerate1/2VDDbiasvoltage.

Bit3 COM3EN:PB3/AN7orSCOM3selection0:PB3/AN71:SCOM3

Bit2 COM2EN:PB4/CLOorSCOM2selection0:PB4/CLO1:SCOM2

Bit1 COM1EN:PC1orSCOM1selection0:PC11:SCOM1

Bit0 COM0EN:PC0orSCOM0selection0:PC01:SCOM0

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Application Circuits

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HT50F50

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HT50F51Note:"*"RecommendedcomponentforaddedESDprotection.

"**"Recommendedcomponentinenvironmentswherepowerlinenoiseissignificant.

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Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OVADDM A�[�] Add ACC to Data Me�o�y 1Note Z� C� AC� OVADD A�x Add i��ediate data to ACC 1 Z� C� AC� OVADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OVADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1Note Z� C� AC� OVSUB A�x Su�t�a�t i��ediate data f�o� the ACC 1 Z� C� AC� OVSUB A�[�] Su�t�a�t Data Me�o�y f�o� ACC 1 Z� C� AC� OVSUBM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1Note Z� C� AC� OVSBC A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OVSBCM A�[�] Su�t�a�t Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1Note Z� C� AC� OVDAA [�] De�i�al adjust ACC fo� Addition with �esult in Data Me�o�y 1Note CLogic OperationAND A�[�] Logi�al AND Data Me�o�y to ACC 1 ZOR A�[�] Logi�al OR Data Me�o�y to ACC 1 ZXOR A�[�] Logi�al XOR Data Me�o�y to ACC 1 ZANDM A�[�] Logi�al AND ACC to Data Me�o�y 1Note ZORM A�[�] Logi�al OR ACC to Data Me�o�y 1Note ZXORM A�[�] Logi�al XOR ACC to Data Me�o�y 1Note ZAND A�x Logi�al AND i��ediate Data to ACC 1 ZOR A�x Logi�al OR i��ediate Data to ACC 1 ZXOR A�x Logi�al XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1Note ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementINCA [�] In��e�ent Data Me�o�y with �esult in ACC 1 ZINC [�] In��e�ent Data Me�o�y 1Note ZDECA [�] De��e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] De��e�ent Data Me�o�y 1Note ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 NoneRR [�] Rotate Data Me�o�y �ight 1Note NoneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1Note CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 NoneRL [�] Rotate Data Me�o�y left 1Note NoneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 NoneMOV [�]�A Move ACC to Data Me�o�y 1Note NoneMOV A�x Move i��ediate data to ACC 1 NoneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1Note NoneSET [�].i Set �it of Data Me�o�y 1Note NoneBranchJMP add� Ju�p un�onditionally � NoneSZ [�] Skip if Data Me�o�y is ze�o 1Note NoneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1Note NoneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1Note NoneSNZ [�].i Skip if �it i of Data Me�o�y is not ze�o 1Note NoneSIZ [�] Skip if in��e�ent Data Me�o�y is ze�o 1Note NoneSDZ [�] Skip if de��e�ent Data Me�o�y is ze�o 1Note NoneSIZA [�] Skip if in��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneSDZA [�] Skip if de��e�ent Data Me�o�y is ze�o with �esult in ACC 1Note NoneCALL add� Su��outine �all � NoneRET Retu�n f�o� su��outine � NoneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � NoneRETI Retu�n f�o� inte��upt � NoneTable ReadTABRD [�] Read table (specific page) to TBLH and Data Memory �Note NoneTABRDC [�] Read ta�le (�u��ent page) to TBLH and Data Me�o�y �Note NoneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y �Note NoneMiscellaneousNOP No ope�ation 1 NoneCLR [�] Clea� Data Me�o�y 1Note NoneSET [�] Set Data Me�o�y 1Note NoneCLR WDT Clea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT1 P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFCLR WDT� P�e-�lea� Wat�hdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1Note NoneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 NoneHALT Ente� powe� down �ode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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8-pin SOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.��6 BSC —

B — 0.15� BSC —

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SymbolDimensions in mm

Min. Nom. Max.A — 6.00 BSC —B — �.90 BSC —C 0.�1 — 0.51C’ — �.90 BSC —D — — 1.75E — 1.�7 BSC —F 0.10 — 0.�5G 0.�0 — 1.�7H 0.10 — 0.�5α 0° — 8°

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16-pin NSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 6.0 BSC —B — �.9 BSC —C 0.�1 — 0.51C’ — 9.9 BSC —D — — 1.75E — 1.�7 BSC —F 0.10 — 0.�5G 0.�0 — 1.�7H 0.10 — 0.�5α 0° — 8°

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20-pin SSOP (150mil) Outline Dimensions

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B — 0.155 BSC —

C 0.008 — 0.01�

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F 0.00� — 0.0098

G 0.016 — 0.05

H 0.00� — 0.01

α 0° ― 8°


Min. Nom. Max.A — 6.00 BSC —

B — �.90 BSC —

C 0.�0 — 0.�0

C‘ — 8.66 BSC —

D — — 1.75

E — 0.6�5 BSC —

F 0.10 — 0.�5

G 0.�1 — 1.�7

H 0.10 — 0.�5

α 0° ― 8°

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