Copyright by Arnab Kumar Dutta 2010
86
Copyright by Arnab Kumar Dutta 2010
Transcript of Copyright by Arnab Kumar Dutta 2010
Copyright
by
Arnab Kumar Dutta
2010
The Thesis Committee for Arnab Kumar Dutta certifies that this is the
approved version of the following thesis:
Design of a Time-based Sigma-Delta Modulator
Committee:
Arjang Hassibi, Supervisor
Eric Swanson
Design of a Time-based Sigma-Delta Modulator
by
Arnab Kumar Dutta, B.Tech
Thesis
Presented to the Faculty of the Graduate School of
The University of Texas at Austin
in Partial Fulfillment
of the Requirements
for the Degree of
MASTER OF SCIENCE IN ENGINEERING
The University of Texas at Austin
August 2010
To ...
My parents for their love and support, my beloved wife and all my
friends
Abstract
Design of a Time-based Sigma-Delta Modulator
Arnab Kumar Dutta, M.S.E
The University of Texas at Austin, 2010
Supervisor: Arjang Hassibi
In this thesis, a time-based oversampling sigma-delta analog-to-digital
converter(ADC) architecture is introduced. This system uses time,
instead of voltage, as the analog variable for its quantizer, where the
noise shaping process is realized by modulating the width of a variable-
width digital pulse. The sigma-delta loop integrator, comparator,
and subtractor are all time-based circuits and implemented by using
only digital gates. The only voltage-based circuit is voltage-to-time
Converter(VTC) which requires only a current source. No amplifier
is required in the entire circuit. As a proof of concept, the simulation
results for a prototype ADC incorporating this time-based sigma-delta
ADC architecture is presented.
v
Contents
List of Figures ix
List of Tables xii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Structure of thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Analog-to-Digital Converter Fundamentals 4
2.1 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Signal Bandwidth or Sampling Rate . . . . . . . . . . . . . 5
2.1.2 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Signal-to-Noise and Distortion Ratio (SNDR) . . . . . . . 5
2.1.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.5 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Conventional ADC Topologies . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Nyquist-Rate Converters . . . . . . . . . . . . . . . . . . . 8
2.3.1.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . 8
2.3.1.2 Integrating ADC . . . . . . . . . . . . . . . . . . 8
2.3.1.3 Pipeline ADC . . . . . . . . . . . . . . . . . . . . 10
2.3.1.4 Successive approximation ADC . . . . . . . . . . 12
2.3.2 Oversampling Converters . . . . . . . . . . . . . . . . . . . 13
2.3.2.1 Sigma-Delta ADC . . . . . . . . . . . . . . . . . 13
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
vi
CONTENTS
3 Time-Based ADC Architectures 19
3.1 VTC-TDC Architectures . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Voltage-to-Time Converters (VTC) . . . . . . . . . . . . . 20
3.1.1.1 Voltage-Controlled Delay Units (VCDU) . . . . . 20
3.1.1.2 Integrator-Based VTC . . . . . . . . . . . . . . . 20
3.1.2 Time-to-Digital Converters(TDC) . . . . . . . . . . . . . . 22
3.1.2.1 Delay-Line Based TDC . . . . . . . . . . . . . . 22
3.1.2.2 Hybrid TDC . . . . . . . . . . . . . . . . . . . . 24
3.1.2.3 Gated Ring Oscillator(GRO)-Based TDC . . . . 25
3.2 VCO-Based Architectures . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Level Crossing/Asynchronous ADC . . . . . . . . . . . . . . . . . 32
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Time-Based Sigma Delta: Concept and Architecture 35
4.1 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.1 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.2 Block Diagram and Descriprion . . . . . . . . . . . . . . . 37
4.1.2.1 Adder and Subtractor . . . . . . . . . . . . . . . 37
4.1.2.2 Delay Component . . . . . . . . . . . . . . . . . 38
4.1.2.3 Comparator . . . . . . . . . . . . . . . . . . . . . 40
4.1.2.4 VTC . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.2.5 Starter . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.3 Representation in MATLAB . . . . . . . . . . . . . . . . . 41
4.2 Timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5 Time-Based Sigma Delta: Circuit Implementation and Simula-
tion 47
5.1 Circuit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.1.1 Voltage-Time Converter and Pulse-adder . . . . . . . . . . 47
5.1.2 Pulse-Subtractor . . . . . . . . . . . . . . . . . . . . . . . 50
5.1.3 Pulse-comparator . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.4 Trip-detector . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.5 Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . 52
vii
CONTENTS
5.1.6 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1.7 Delay-Element . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6 Discussion and Conclusion 64
6.1 Contribution of this work . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Fundamental power limits comparison . . . . . . . . . . . . . . . . 64
6.2.1 Conventional Sigma-Delta Power Limit . . . . . . . . . . . 64
6.2.2 Time-Based Sigma Delta Power Limit . . . . . . . . . . . . 69
6.3 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
References 71
viii
List of Figures
1.1 Trends in ADC performance vs power . . . . . . . . . . . . . . . . 2
2.1 Block diagram of ADC . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Single-slope integrating ADC . . . . . . . . . . . . . . . . . . . . 9
2.4 Dual-slope integrating ADC . . . . . . . . . . . . . . . . . . . . . 10
2.5 12-bit Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Algorithmic ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 Oversampling with ideal low-pass filter . . . . . . . . . . . . . . . 14
2.9 First order noise shaping . . . . . . . . . . . . . . . . . . . . . . . 15
2.10 Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 1st order 1-bit Sigma-Delta Modulator . . . . . . . . . . . . . . . 17
3.1 VTC-TDC architecture . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 A ’linearized’ voltage-controlled delay unit . . . . . . . . . . . . . 21
3.3 Integrator-Based VTC schemes(Timing) . . . . . . . . . . . . . . 21
3.4 Integrator-Based VTC schemes(Block Diagram) . . . . . . . . . . 21
3.5 Buffer-based TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Inverter-based TDC . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 Vernier Delay-line TDC) . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9 Hybrid TDC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 Hybrid TDC block diagram . . . . . . . . . . . . . . . . . . . . . 27
3.11 Gated Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 28
ix
LIST OF FIGURES
3.12 GRO-based TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.13 Basic VCO based architecture . . . . . . . . . . . . . . . . . . . . 29
3.14 VCO-based architecture using phase outputs . . . . . . . . . . . . 30
3.15 First order noise shaping in VCO . . . . . . . . . . . . . . . . . . 31
3.16 VCO in Sigma-Delta loop . . . . . . . . . . . . . . . . . . . . . . 32
3.17 Asynchronous ADC Block Diagram . . . . . . . . . . . . . . . . . 33
3.18 Asynchronous ADC Timing . . . . . . . . . . . . . . . . . . . . . 33
4.1 (A) Conventional sigma delta (B) Time-mode sigma-delta . . . . 36
4.2 (A) Pulse addition (B) Pulse subtraction . . . . . . . . . . . . . . 37
4.3 Pulse width evolution with cycle . . . . . . . . . . . . . . . . . . . 39
4.4 Voltage-Time Converter . . . . . . . . . . . . . . . . . . . . . . . 41
4.5 Matlab Output(Timing) . . . . . . . . . . . . . . . . . . . . . . . 43
4.6 Matlab Output(FFT) . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7 Borderline case for maximum pulse width . . . . . . . . . . . . . . 45
4.8 Maximum separation of pulse positive edge from negative clock edge 46
5.1 Actual circuit implementation of Voltage-Time Converter . . . . . 48
5.2 Pulse-adder using VTC . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3 Pulse-adder timing diagram . . . . . . . . . . . . . . . . . . . . . 49
5.4 Pulse-adder characteristics . . . . . . . . . . . . . . . . . . . . . . 50
5.5 Pulse-Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.6 Pulse-Subtractor timing diagram . . . . . . . . . . . . . . . . . . 51
5.7 Pulse-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.8 Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.9 Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.10 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.11 Starter Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 54
5.12 Insertion of starting pulse in main loop . . . . . . . . . . . . . . . 55
5.13 Delay Element 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.14 Delay Element 2(actually used) . . . . . . . . . . . . . . . . . . . 57
5.15 Detailed block diagram of proposed sigma-delta . . . . . . . . . . 58
5.16 Simulation results for Power Spectral Density . . . . . . . . . . . 59
5.17 Simulation results for Input and Output Waveform . . . . . . . . 60
x
LIST OF FIGURES
6.1 Class-A Sample Hold . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 (A) Simplified switch-capacitor integrator (B) Model for redistri-
bution phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3 Simplified model of delay element . . . . . . . . . . . . . . . . . . 69
xi
List of Tables
1.1 EADC vs ENAND . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.1 Nominal timing paramaters . . . . . . . . . . . . . . . . . . . . . 61
5.2 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3 Comparison with other implementations . . . . . . . . . . . . . . 62
xii
1
Introduction
1.1 Motivation
The advances in VLSI technology has made it possible to build very complex
digital circuits. The task of signal processing has progressively moved towards
digital domain as digital circuits have lots of advantage over their analog coun-
terparts - lower noise sensitivity, better repeatability, ability to perform complex
processing task with lesser die area and power and also availability of tools for
automatic synthesis and testing. However, real world signals are always in analog
form and there has to be an interface to convert it to an equivalent digital rep-
resentation. Analog-to-Digital converters(ADC) are one of the major component
of that interface.
The ADC is traditionally built using analog components such as amplifiers.
While the advances in VLSI fabrication is beneficial for digital circuits, it has
created many fundamental challenges for analog designers - lower voltage head-
room, smaller signal dynamic range, and less transistor gain due to short channel
effects (8). These impediments particularly effect the performance and power con-
sumption requirements of high precision analog/mixed-signal circuits including
analog-to-digital converters (ADCs).
But despite that, we can see in fig 1.1 that the power efficiency of ADCs
is constantly improving (14). This can be attributed to the following trends in
architecture that has evolved with scaling -
1
1.1 Motivation
Figure 1.1: Trends in ADC performance vs power
Minimalistic Design - The goal of minimalistic design is to improve power
efficiency by simplifying the analog subcircuits of the ADCs. As an example, the
inherent inefficiency of op-amps has encouraged many ADC designers to remove
this building block or to simplify it. An example of this approach is op-amp-
less implementation of pipeline ADCs (15) in which the op-amp is replaced with
open-loop amplifiers. This simplification of the analog circuit block can sacrifice
precision for performance and therefore, it is very also attractive to consider
digital techniques to recover accuracy in minimalistic designs (14).
Digitally-assisted analog - As the power consumption of digital gates is
reducing with scaling, it makes sense to transfer the burden of maintaining accu-
racy to digital domain to reduce overall power consumption. In (14), a compar-
ison was made between energy consumption trends for an ADC having certain
SNDR(EADC) and a NAND gate(ENAND) in a 130nm process which is shown in
1.1. It is obvious from the data that higher the resolution of the converter, the
more justifiable it is to use digital correction.
Time mode signal processing - The fundamental improvements that tech-
nology scaling brings about is time resolution which is due to the reduction of gate
delay. Therefore, it has been suggested recently that time-domain, as opposed to
voltage-domain analog processing in nanometer-scale VLSI fabrication processes
2
1.2 Structure of thesis
SNDR(dB) EADC(nJ) EADC/ENAND
30 21 4700
50 168 38000
70 1350 300000
90 10800 2400000
Table 1.1: EADC vs ENAND
might offer a better (and more process-compatible) solution (2; 4; 10; 13; 18; 21).
Sigma-delta ADCs (11; 20) are used for its achievable high resolution that is
enabled by oversampling and noise shaping and is the topology of choice for low-
frequency signals such as sensor outputs. It is traditionally built using op-amp
based integrators, subtractors and comparators. This thesis aims at eliminating
the use of op-amp in sigma-delta by creating time domain equivalents of integra-
tion, comparison and subtraction operations and thereby making it more friendly
for technology scaling.
1.2 Structure of thesis
Chapter 2 describes the fundamentals of Analog-to-Digital conversion - speci-
fications, figure of merits and non-idealities. It also introduces different types
of ADC architectures (integrating, flash, pipelined, SAR, sigma-delta) and their
trade-offs with a special emphasis on sigma-delta.
Chapter 3 provides an overview of various time-based ADC architectures
found in literature.
Chapter 4 gives a conceptual view of the proposed Sigma-Delta architecture
and describes the functionality of various blocks at architectural level.
Chapter 5 presents the detailed circuit level implementation of the blocks and
the simulation results.
Chapter 6 summarizes the work of this thesis and discusses the plan of future
work.
3
2
Analog-to-Digital Converter
Fundamentals
An analog to digital converter (ADC) is responsible for conversion of a continuous-
time and continuous amplitude analog signal to a digital signal which is discrete
in time and amplitude so that it can be processed by digital signal processors
(DSPs). The process can be broken into three steps - sampling (conversion to
discrete time), quantization (conversion to discrete amplitude) and encoding (con-
version of discrete amplitude to a digital code). A block diagram is shown in Fig
2.1. Since the sampling process introduces aliasing, an anti-aliasing filter is re-
quired to band-limit the signal to fs/2.
ADC
Figure 2.1: Block diagram of ADC
4
2.1 ADC specifications
2.1 ADC specifications
2.1.1 Signal Bandwidth or Sampling Rate
The signal bandwidth of an ADC is typically defined as the frequency range
over which the ADC will maintain its quoted performance. Signal bandwidth
and clock sampling rate of an ADC are related by the Nyquist criterion - The
sampling rate should be at-least twice the band of interest.
2.1.2 Resolution
Resolution of an ADC is a measure of how accurately the digital output will
represent the analog input. It may be defined as the smallest analog input change
(∆) that will results in an LSB change in the digital output code. Resolution is
often expressed in number of bits B in the digital output. Hence, there are 2B
digital output possibilities. The difference between actual signal and quantized
value is called quantization error and it generates a quantization noise floor. It
can be shown that its power is ∆2/12 assuming that it is uncorrelated with the
signal.
The accuracy of the conversion (closeness to the original analog signal) de-
pends on both on the sampling rate and resolution. The choice of sampling
frequency and resolution is highly application-dependent and constitute one of
the many trade-offs of ADC design.
2.1.3 Signal-to-Noise and Distortion Ratio (SNDR)
The sampling and quantization process is not as perfect as described above. All
real world circuits will have associated distortion. So the actual transfer char-
acteristic from analog voltage to digital code will have some non-linearity. The
quantization steps are non-uniform. Moreover, all components add their own
thermal and flicker noise. SNDR is defined as the ratio of signal power to noise
and distortion power.
SNDR(dB) = 10 · logVin
2
Vdis2 + Vnoise
2(2.1)
5
2.1 ADC specifications
SNDR is a function of both amplitude and frequency of the input sinusoid.
For lower signal amplitudes, the noise dominates while for higher amplitudes,
harmonics appear due to non-linearity of transfer curve. In data sheets, the
amplitude and frequency of sinusoid applied for calculating SNDR is mentioned.
SNDR in dB can also be expressed in terms of effective no of bits(ENOB) where,
ENOB =SNDR(dB) − 1.76
6.02(2.2)
Some other related metrics are given here
SNR - Signal-to-Noise Ratio.
SNR(dB) = 10 · logVin
2
Vnoise2
(2.3)
SQNR - Signal-to-quantization noise ratio. This is used to distinguish quan-
tization noise from other noise sources such as thermal and flicker noise.
SQNR(dB) = 10 · logVin
2
Vnoise(quant.)2
(2.4)
THD - Total Harmonic Distortion.
THD(dB) = 10 · logVin
2
Vdis2
(2.5)
2.1.4 Power
All data conversion requires power and the design goal is to minimize power
consumed. It not only improves the life of battery but also increases the reliability
of the circuit (3).
2.1.5 Area
The area of the circuit should be minimized not only to reduce cost but also the
probability that the circuit fails due to defects. Power and Area can be viewed
as the cost associated with a given bandwidth and SNDR performance.
6
2.2 Figures of Merit
2.2 Figures of Merit
ADCs vary a lot in terms of speed, resolution, power, area. In order to compare
them, different types of Figures-of-Merit(FOM) were defined by designers some
of which are described below.
FOM1 = 2ENOB · Bandwidth (2.6)
This figure of merit evaluates ADCs on performance alone and not the cost
associated with it. It suggests that increasing bandwidth by 2 is as difficult
as increasing ENOB by one bit.
While it might be useful for military purposes, consumer products are rated
also on size and battery life. The following FOMs capture this .
FOM2 =2ENOB · Bandwidth
Power(2.7)
FOM3 =2ENOB · Bandwidth
Power · Area(2.8)
2.3 Conventional ADC Topologies
The choice of ADC topology is highly application-dependent and all the factors
of section 2.1 must be considered. An additional factor to consider is component
matching requirement. Mismatched components will give rise to nonlinearity
and hence poor SNDR performance. A lot of design time is required for good
component matching.
The ADCs described here can be categorized based on the ratio of sampling
frequency to band of interest. Its has already been stated that sampling frequency
should be at least twice the band of interest to satisfy Nyquist criterion. The
ADCs that use a sampling rate close to nyquist criterion (around 5-10 times
7
2.3 Conventional ADC Topologies
band of interest) are called Nyquist rate converters. If the sampling rate is much
higher than band of interest (around 100X), its called Oversampling converter.
It is to be noted that any of the topology described as Nyquist rate can be used
in oversampling mode depending on application.
2.3.1 Nyquist-Rate Converters
2.3.1.1 Flash ADC
Flash ADC (also known as prallel ADC) performs conversion using 2B − 1 com-
parators(Fig 2.2. The output of the array of comparators is a thermometer code
which can be resolved into binary code using priority encoder. It requires very
good component matching for the comparator array. If they are not matched
properly, we might get an output of 0 between two comparator outputs of 1
which is not a valid thermometer code. This is known as bubble error and can
be corrected easily by digital means. So, the block following comparator outputs
also performs digital correction in addition to encoding.
This is the fastest way for analog to digital conversion and so used for large
bandwidths.However, number of comparators and hence power and area grows
exponentially with B. So it is suitable only for low resolution (typically upto 8
bits). It is usually used for high-speed data acquisitions or may be used as a
sub-block in pipelined and sigma-delta architectures.
2.3.1.2 Integrating ADC
An integrating ADC converts input voltage to digital code by use of an integrator.
The simplest form is the single-slope architecture as shown in Fig 2.3.
Here the input voltage is integrated until it reaches a reference voltage Vref .
The time Ti required for the integrator output to reach Vref is related to Vin
according to the following equation.
Vin =Ti × Vref
R × C(2.9)
8
2.3 Conventional ADC Topologies
Prio
rity
En
code
r
Vref Vin
2B-1
1
B
DigitalOutput
2B-2
Figure 2.2: Flash ADC
R
C
Vin
Vref
Vint
ti
Vint
Time
Vref
Figure 2.3: Single-slope integrating ADC
9
2.3 Conventional ADC Topologies
The problem with this implementation is the dependency on the absolute
values of R and C which can have lots of PVT variations. A more robust way is
to use Dual-slope architecture as shown in Fig 2.4.
R
C
Vin
-VrefVint
t1 t2
Vint
Time
Figure 2.4: Dual-slope integrating ADC
Here we first have constant-time integration (Tref ) followed by a constant-
slope integration (Ti). Vin can be found using the following equation
Vin =Tref × Vref
Ti
(2.10)
It is to be noted that the dependency on the values of R and C is completely
eliminated.
The times are measured using counters, which has to be of much higher fre-
quency than signals for good resolution. So, the signal bandwidth must be low.
However because of integration, it provides good noise rejection and if the inte-
gration frequency is chosen properly, it can provide line-frequency rejection as
well.This architecture is a simple(very little component matching required) and
low-cost(area and power) for low-bandwidth signals and are used in applications
like digital multimeters.
2.3.1.3 Pipeline ADC
The idea of pipeline ADC is to combine flash ADCs in multiple stages to reduce
power and area at the expense of latency. In fig 2.5 we can see a pipeline
10
2.3 Conventional ADC Topologies
ADC consisting of four stages each resolving three bits. Each stage amplifies its
residual error for the current input. This error is transferred to the next stage in
the subsequent clock cycle while it itself works on the next input sample. Thus, at
any point of time, the ADC would be working on four consecutive input samples.
This action is known as pipelining. Each of the stage outputs need time alignment
using shift registers and the final output is obtained after four cycles of latency.
The stages have one-bit of redundancy in order to allow the digital correction
logic to take care of offset errors. However, gain and linearity errors cannot be
corrected by this method and would require calibration schemes.
Stage 1 Stage 2 Stage 3
4 4 4 3
3-bit Flash
ADC
Time-Alignment and Digital Error Correction
12
4-bit FlashADC
4-bit FlashDAC
8X
Vin
DigitalCode
Figure 2.5: 12-bit Pipelined ADC
The gain and subtraction blocks need to be very precise-especially for the
first stage implying that high degree of component matching required. The DAC
needs much higher level of accuracy than number of bits resolved.
This architecture can provide a wide-range of bandwidth and resolution trade-
offs depending on the number of stages and bits per stage. Its usually used for
applications where latency is not a concern such as imaging and video.
A variation of pipelined ADC is algorithmic ADC (Fig 2.6) where each stage
is re-used(the amplified residual error is fed back to the input) in order to save
11
2.3 Conventional ADC Topologies
area and power at the cost of bandwidth. Also, as only one stage is present, the
calibration scheme is highly simplified.
3-bit FlashADC
3-bit FlashDAC
8XS/H
Di
Vin
Figure 2.6: Algorithmic ADC
2.3.1.4 Successive approximation ADC
SAR
Logic
N
N-bit
DAC
N
Digital
Output
EOC
Vin
Figure 2.7: SAR ADC
Successive-approximation(SAR) ADCs perform conversion using a binary search
algorithm. The SAR logic (fig 2.6) produces a code with MSB high and rest of
the bits zero(This is the midscale value) at the beginning of conversion cycle. The
DAC produces the analog equivalent which is compared against the input signal.
If output is high, the bit remains 1 otherwise it resets to zero. Same procedure
12
2.3 Conventional ADC Topologies
is followed for subsequent bits until LSB is reached. This architecture needs a
DAC with very good accuracy and settling time (should settle before next clock
cycle). It is slower than pipelined but saves a lot on area and power. So, it is
good for portable applications requiring small area and power.
2.3.2 Oversampling Converters
2.3.2.1 Sigma-Delta ADC
Sigma-delta ADCs use oversampling and noise-shaping techniques to move the
quantization noise out of band of interest. They provide the highest resolution
among all architectures.
Oversampling is a process of sampling a signal at a frequency significantly
higher than the Nyquist rate i.e. - twice the bandwidth. There can be various
motivations for oversampling but in this context, it is used to improve the reso-
lution of the ADC. It is based on the assumption that the quantization noise is
uniformly distributed over frequencies 0 to fs/2 (which is the case if it is com-
pletely uncorrelated with the signal). If the signal of interest is band-limited to
fb with fb << fs/2, then a significant amount of quantization noise can be elim-
inated by using a digital low-pass filter. The simplest way is to average the past
N samples where N = fs
2×fb.
If we assume an ideal low-pass filter with brick-wall response (Fig 2.8), the
noise power decreases by 10 log N dB. Thus, for every octave of oversampling,
the quantization noise power is decreased by 3 dB which indicates 0.5 bits of
improvement.
The improvement of 0.5 db per octave of oversampling is not enough for very
high resolution. Let us say we have a 8-bit ADC and we want to get 16 bits of
resolution out of it for a 1 MHz signal. The sampling frequency required is given
by
fs = 2 × 216 × 1MHz = 131GHz (2.11)
which is completely impractical. The idea of noise shaping is to move quan-
tization noise outside the frequency of interest. In this section, we will consider
13
2.3 Conventional ADC Topologies
N(f)
IdealLow-PassFilter
2
12
∆
2
12 / 2
b
s
f
f
∆×
bf / 2sf
Figure 2.8: Oversampling with ideal low-pass filter
the case where signal of interest is near DC such that quantization noise has to
be moved to higher frequencies.
The simplest way of noise-shaping for a low-pass signal of interest is to add the
previous quantization error to the current signal. Thus the signal to be quantized
is given by
Yn = Xn + en−1 (2.12)
Where Xn and en are input signal and quantization error respectively for
sample n.
The quantized signal is given by-
Yqn= Yn − en
= Xn + en − en−1 (2.13)
If we convert this equation to z-domain, the quantization error has a transfer
function of 1 − z−1
If we replace z by ejωT , we get
14
2.3 Conventional ADC Topologies
1 − z−1 = e−jωT
2 (ejωT
2 − e−jωT
2 )
= e−jωT
2 (−2j sinωT
2) (2.14)
The magnitude is given by
sinωT
2= sin
πf
fs
(2.15)
The power spectral density of quantization noise after noise shaping is shown
in fig 2.9
N(f)
bf / 2sf
IdealLow-PassFilter
Figure 2.9: First order noise shaping
If we integrate till the bandwidth of interest(assuming an ideal low-pass filter)
fb and assume fb << fs, it can be shown that-
NoisePower(in − band) =∆2
12
π2
3(
1
N)3 (2.16)
In this case, SQNR is given by
15
2.3 Conventional ADC Topologies
SQNR =12
(2B−1)∆2
2
∆2
12π2
3( 1
N)3
= 1.5 × (2B − 1)2 × 3
π2× N3
≈ 1.76 + 6.02B − 5.2 + 30 log N [dB] (2.17)
This is 8x decrease in quantization noise (1.5 bits) for 2x increase in N. We
can go back to the previous example and show that we need N=60 for getting
16-bit resolution out of 8-bit ADC.
H(z)Y(z)X(z)
N(z)
E(z)
Figure 2.10: Sigma-Delta Modulator
A general block-diagram for sigma-delta modulator is shown in fig 2.10. Here,
X(z) is the input signal while Y (z) is the quantized output. N(z) is the quanti-
zation noise and E(z) is the error in DAC. Ignoring E(z), we can calculate the
transfer functions as follows-
Y (z)
N(z)=
1
1 + H(z)(2.18)
Y (z)
X(z)=
H(z)
1 + H(z)(2.19)
16
2.4 Summary
If we choose H(z) to be very large in the band of interest, we see that Y (z)N(z)
≈ 0
and Y (z)X(z)
≈ 1
For a first-order sigma delta modulator, H(z) = 1z−1
which gives
Y (z)
N(z)= 1 − z−1 (2.20)
Y (z)
X(z)= z−1 (2.21)
This is similar to what we saw earlier.
X(z)for i=1 to N
{
vsum = vin(i) - d
v1 = v1 + vsum
if v1 > 1
d = 1;
else
d=0;
v(i) = v1;
dout(i) = d;
}
Figure 2.11: 1st order 1-bit Sigma-Delta Modulator
One major difficulty in this structure is that the DAC needs to be very accu-
rate as the DAC error E(z) has same transfer function as the signal X(z). So,
the ADC+DAC is often replaced by a single comparator (fig 2.11). This acts as
a 1-bit ADC+DAC. The output of integrator is compared against a known refer-
ence Vref . The output of the comparator is either 0 or Vref The only errors that
can be present in a 1-bit ADC/DAC are offset errors which has little effect for
most applications (discussed in next section). The behaviour of this modulator
is easily described by the pseudocode given in fig 3.4. In the pseudocode, Vref is
normalized to 1.
2.4 Summary
In this chapter, the fundamentals of A/D conversion were introduced. The spec-
ifications and different figures of merits were explained which provides a basis
17
2.4 Summary
for comparing the converter presented in this thesis with other existing ones. Fi-
nally the conventional ADC topologies were described with special emphasis on
Sigma-Delta ADC.
18
3
Time-Based ADC Architectures
In a time-based ADC, time is used as an analog variable instead of voltage. It may
be used either as frequency or as delay between two signals. The basic premise
is that - in modern VLSI technogies, the resolution in time is much better than
resolution in voltage.
The single-slope integrating ADC described in section 2.3.1.2 can be con-
sidered the most preliminary form of time-based ADC. The integrator followed
by comaparator can be considered as a Voltage-to-Time Converter (VTC) since
it converts the input voltage to an equivalent delay between start of cycle an
comparator output switching. The counter can be considered a Time-to-Digital
Converter (TDC) since it quantizes the time delay. However, using counter is
inefficient since it has to be of much higher frequency than sampling rate. Since
time-resolution has improved in emerging technologies, more advanced TDC ar-
chitectures have evolved.
This chapter provides an overview of various time-based ADC topologies found
in literature including the VTC-TDC based architectures.
3.1 VTC-TDC Architectures
In this architecture, the VTC converts Vin into an equivalent delay between the
edges of start and stop pulses. The TDC converts the delay to an equivalent
digital code. The basic structure is shown in 3.1. In the following sections, we
would explore various implementations of these blocks.
19
3.1 VTC-TDC Architectures
BCLK
Start
Stop
DIGITALOUTPUT
VIN VIN
CLK
VTC TDC
Start
Stop
Figure 3.1: VTC-TDC architecture
3.1.1 Voltage-to-Time Converters (VTC)
3.1.1.1 Voltage-Controlled Delay Units (VCDU)
The simplest way to convert voltage to an equivalent delay is using a VCDU
as seen in section 3.1. However, this method has limited linearity since the
relation between voltage and time is inherently non linear. A more ’linearized’
version can be found in (9). The circuit is shown in fig 3.2 Let us consider
the half-circuit consisting of M1, M2, M5, M7, M9, Mll, and M13. The main
current starving device, M5 is linearized because of source degeneration device
M7 whenever M1/M2 makes a high-to-low transition. The devices M11 and M13
are normally biased in subthreshold region and enter inversion region when Vin is
very high. This mitigates the compression of delay vs voltage characteristics for
high voltage. The additional device M9 improves voltage-sensitive. Though not
linear as the ramp-based implementations discussed later, it has been reported
to work at frequencies higher than 1 GHz.
3.1.1.2 Integrator-Based VTC
This architecture follows the same principle that was used in single slope inte-
grating ADCs. A constant slope ramp is compared against a reference signal.
There are two ways to go about it.
A) The ramp is started at 0 and compared against Vin
B) The ramp is started at Vin and compared against a fixed reference Vref
The timing and block diagram of these schemes is shown in 3.3 and 3.4
respectively.
The advantage of scheme A is that its possible to completely eliminate the
sample-hold circuitry. In that case, the samples collected will be non-uniform
in time. However, its possible to recover the actual samples using the algorithm
20
3.1 VTC-TDC Architectures
M1
M2
M3
M4
Vclk
Vclkd Vclkd
Vclk
VDD
M5
M7
M9M13 M11
M6
M8
M10M14M12
Vin
Vb Vb
Vin
Figure 3.2: A ’linearized’ voltage-controlled delay unit
Ram
p V
oltage
Ram
p V
oltage
Time Time
Tin
Tin
Vin Vin
Vref
(A) (B)
Figure 3.3: Integrator-Based VTC schemes(Timing)
Φ1
Φ2
VinVin
Vref
Φ2 Φ1
(A) (B)
Figure 3.4: Integrator-Based VTC schemes(Block Diagram)
21
3.1 VTC-TDC Architectures
proposed in (7).Also the ramp generator can be shared among multiple VTCs
if we are building a multi-channel ADC (7). Since it is usually the most power
hungry unit in this architecture, sharing it saves overall power per conversion.
However, at the point of switching, the comparator in this architecture has to
operate at a wide range of common modes depending on Vin and the compara-
tor delay is usually a function of common mode. As we go to higher sampling
frequencies (close to 100 MHz), the timing window becomes smaller. If we don’t
want the comparator delay variations to degrade SNR, we either need matched
delays or the delay has to be so small that variations do not matter. Both of these
come at the cost of power and area. But in scheme B, comparator has to operate
only at a single common mode while switching - Vref . The design becomes much
simpler and it can even be done with an inverter which can potentially save lot
of static power. The choice of one of these topologies is highly dependent on the
frequency range required.
3.1.2 Time-to-Digital Converters(TDC)
TDC systems have application in a large number of time measurement systems
and subsequently have a variety of industrial and research applications. They
are widely used in digital storage oscilloscopes, logic analyzers and high-energy
particle physics experiments. The simplest form of a TDC is a digital counter.
However, to achieve a high resolution TDC, one needs to use a very high frequency
counter for a wide dynamic range, and this is not necessarily energy efficient. This
section explores some of the more efficient methods of implementing TDCs.
3.1.2.1 Delay-Line Based TDC
TDC can be built by using a combination of D-flip-flops and buffers as shown
in Fig 3.5. It measures the time difference between the positive edges of start
and stop (assuming postive edge of start occurs before stop). start propagates
through the delay line consising of buffers and each of the buffer output is con-
nected to the inputs of D-Flip-Flops. stop is connected to the clock and latches
the current state of delay-line. It produces a thermometer code similar to flash
22
3.1 VTC-TDC Architectures
ADC which is resolved using priority encoders. The time resolution is limited by
the minimum delay of the buffer(td) that can be built in that technology.
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Priority Encoder
1 2 2B-1
B
td td tdStart
Stop
Figure 3.5: Buffer-based TDC
The buffers can be made of VCDUs and the total delay can be stabilized over
process and temperature using a delay-locked-loop(DLL). However, there would
still be mismatches between individial buffers which will produce DNL errors.
This errors would accumulate and produce maximum INL error somewhere in
the middle of the line. INL at the end of line will be zero because of the synchro-
nization using DLL. The maximum INL is related to length of buffer chain (n)
according to the following equation
INL ∝√
n (3.1)
It is to be noted that in most technologies, the most efficient way of creating
buffer is using two inverters. So in the architecture used in fig 3.5, the resolution
is effectively twice the minimum possible delay in the technology. We can try to
replace it with an inverter based delay line. The simplest implementation would
be to replace the buffers in the path of start with inverters and invert every
alternate output. However, the DNL characteristics would get corrupted because
of possibly uneven rise and fall transition times of inverters as well as uneven
23
3.1 VTC-TDC Architectures
metastability resolution of flip-flops and it actually provides very little advantage
over buffer-based approach.
So, a pseudo-differential approach was proposed in (6) to avoid mismatches in
rise and fall transitions. As shown in fig 3.6, this architecture requires differential
flip-flops and two different delay lines for start and start. An edge aligner is used
to align the edges of start and start as closely as possible.
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Priority Encoder
1 2 2B-1
B
tdSt
Stop
td td
td td td
D D D
START
START
Figure 3.6: Inverter-based TDC
If we want even better resolution we can use a parallel delay chain in the path
of ’stop’. If that delay chain has a unit delay of tc each such as tc < td, the new
resolution is td − tc. This architecture is known as ’Vernier Delay-line TDC’ and
the basic configuration is shown in fig 3.7. The maximum resolution achievable in
this configuration depends on the meta-stability window of the flip-flops. These
flip-flops are usually built using sense-amplifiers as shown in fig 3.8
3.1.2.2 Hybrid TDC
While the architectures in section 3.1.2.1 are good for measuring small time
intervals, its hard to increase the dynamic range not only because number of
delay elements required increases exponentially with number of bits in output
but also because INL is degraded with longer delay chains as shown in equation
3.1. In order to implement a TDC with high dynamic range, we can use a counter
24
3.1 VTC-TDC Architectures
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Priority Encoder
1 2 2B-1
B
td td tdStart
Stop tc tc tc
Figure 3.7: Vernier Delay-line TDC)
as coarse quantizer to resolve the MSBs while using a delay-line TDC to resolve
the LSBs. The timing diagram is shown in fig 3.9.
It is assumed that the start signal is aligned with the positive edge of the
counter. The counter resolves the time interval tc while the delay-line TDC
resolves tr which is the time difference between rising edge of stop and the next
rising edge of counter. The actual time is given by
tm = tc − tr (3.2)
A block diagram for hybrid TDC is shown in fig 3.10.
The buffer delay in TDC should be an exact fraction of counter clock period.
E.g - If the TDC resolves 5 bits, the delay should be 1/32 of clock period. This
synchronization can be done using a DLL.
3.1.2.3 Gated Ring Oscillator(GRO)-Based TDC
A GRO consists of a ring oscillator structure with the ability to freeze its current
state (12). A simple diagram shown in fig 3.11. When enable is high, the switches
are closed and it behaves like a normal ring oscillator. When switches are open,
the charges stored in the output capacitors would have nowhere to go and current
state its maintained. When switches are closed again, oscillation would resume
from the previous stored state.
25
3.1 VTC-TDC Architectures
trtm
tc
Clk
Start
Stop
Enable
Figure 3.9: Hybrid TDC Timing
Q
QSET
CLR
DVDD
Stop Clk
Q
QSET
CLR
S
R
Start
Q
QSET
CLR
D Clk
En
Out
Counter
Stop
Start
Out
MSBs
LSBs
Delay-lineTDC
Enable
Figure 3.10: Hybrid TDC block diagram
27
3.1 VTC-TDC Architectures
VDD
Enable
O1 O2 O3 O4 O5
Figure 3.11: Gated Ring Oscillator
GROEnable
Counters
Registers
OUT
Figure 3.12: GRO-based TDC
28
3.2 VCO-Based Architectures
Fig 3.12 shows the conceptual implementation of TDC using a GRO. The
GRO is enabled during the time interval to be measured and a counter counts
number of transitions. The residual phase gets stored and added to the next
cycle. So, it provides first-order noise shaping. Also, the mismatches in the
delay elements of ring-oscillator gets first-order shaped as for a given input, the
selection of delay elements is equivalent to barrel-shift algorithm for dynamic
element matching.
3.2 VCO-Based Architectures
In this architecture, a Voltage-controlled oscillator(VCO) followed by a counter
act as a voltage-time converter and quantizer at the same time. As shown in fig
3.13 gets incremented on the rising edge of the VCO output. It is reset by the
rising edge of Clk and the last value is stored in some register (not shown). If we
assume that the phase of VCO output is given by the equation -
Φ =
∫
K · Vindt + ffr (3.3)
B
VCO CounterVIN
CLK
Digital
Output
Figure 3.13: Basic VCO based architecture
Where ffr is the free running frequency. The counter increments each time
the phase is incremented by 2π. Thus, the digital output is a measure of average
value of Vin over a sampling clock period(tsample).
VCOs are inherently non-linear and the linear relationship of equation 3.3 is
valid only for a limited range of Vin. Let fmin and fmax be the frequencies corre-
sponding to the input voltage range for which the conversion can be considered
’linear’. Then the maximum resolution of this architecture is given by-
29
3.2 VCO-Based Architectures
Resolution = log2
fmax − fmin
fsample
(3.4)
where fsample is inverse of tsample.
If the VCO is implemented using ring-oscillator consisting of Voltage Con-
trolled delay units (VCDU), we can tap the individual phase outputs for finer
resolution as shown in Fig 3.14 (10). The VCDUs are usually made of current-
starved inverters. Though the figure shows the VCO with three stages, it can be
extended to multiple stages(Nd). In that case, the resolution is given by-
Resolution = log2
fmax − fmin
fsample
· 2 · N (3.5)
B
VCO CounterVIN
CLK
DigitalOutput
Vx
Vy
Vz
VIN
Vx Vy Vz
Figure 3.14: VCO-based architecture using phase outputs
However, the timing resolution is limited to delay in each stage. If we assume
that the minimum delay of each stage is td, then for a N-stage VCO-
fmax =1
2 · N · td(3.6)
If we assume fmax >> fmin, and substitute the value of fmax given by 3.6
in 3.5 maximum achievable resolution is a function of td which is a technology
dependant parameter.
30
3.2 VCO-Based Architectures
Resolution = log2
1
2 · fsample · td(3.7)
The main advantage of VCO based architecture is that the VCO (along with
pulse counter) act as a voltage-time converter and quantizer at the same time.
Also, as the residual phase in one conversion cycle is carried over to the next
cycle it provides first-order quantization noise shaping. From fig 3.15, we can
see that-
Φ(n) = G · x(n) + p(n) − e(n)
= G · x(n) + e(n − 1) − e(n) (3.8)
which is equivalent equation 2.16 for first order noise shaping.
e(n-1)VCOPhase
0
2
4
6
8
p(n)Φ(n)Φ(n-1)
e(n)
Φ(n+1)
Timen-1 n n+1
K.x(n)
Figure 3.15: First order noise shaping in VCO
The biggest disadvantage is that it involves lot more switching than VTC-TDC
architectures and hence consume lot of power. Also, voltage-time conversion is
inherently non-linear. However, this can be overcome by including the VCO in a
sigma-delta loop as shown in Fig 3.16.
31
3.3 Level Crossing/Asynchronous ADC
FilterVCO and
Pulse Counter
DAC
In Out
Figure 3.16: VCO in Sigma-Delta loop
3.3 Level Crossing/Asynchronous ADC
A block diagram for asynchronous ADC is shown in fig 3.17. It consists an array
of reference levels, comparators and digital asynchronous processing element and
a ’MERGE’ block to combine the individual outputs. Whenever the input signal
crosses one of the comparator thresholds, its corresponding digital processing
element outputs a 1 or 0 on a dual-rail channel depending on whether the crossing
has taken place from above or below(Fig 3.18). Thus comparator activity takes
place only when there is a significant change in signal unlike Flash ADCs. In order
to prevent multiple transitions due to noise when a threshold is being crossed, the
comparators have some amount of hysterisis (shown by dotted lines in fig 3.18).
As the system is asynchronous, the individual elements have a handshaking
protocol between them in the form of a token. Only the element that has token
can produce output. If a crossing has taken place for one of the element and it
does not have the token, it has to request it from the element either above or
below it, whicheves is appropriate before producing the output. In theory, only
two comparators need to be active at a given time(the ones with threshold levels
just above and below the current signal level). This fact can be exploited to save
power by turning off the remaining comparators.
The final output is a string of 1’s and 0’s non-uniformly spaced in time which
indicate the relative change of input signal over time. Both the bit sequence and
their timing information is required to reconstruct the signal. The maximum
bandwidth of the signal that can be processed depends on the rate at which the
asynchronous ADC can produce output samples.
32
3.3 Level Crossing/Asynchronous ADC
Vin
token
ME
RGE
Asynchronous
Processing
ElementComparator
Vref1
Vref2
Vref3
Vref4
Figure 3.17: Asynchronous ADC Block Diagram
Dual rail
digital output
t1 t2 t3t1 t2 t3
AnalogInput
Time Time
Vref(i)
Vref(i+1)0
1
Figure 3.18: Asynchronous ADC Timing
33
3.4 Summary
3.4 Summary
In this chapter, some of the existing time-based ADC architectures are explored.
We saw how these architectures exploit the advantage of better resolution in
time in order to overcome the challenges faced by conventional voltage-based
architectures. In the following two chapters which form the core of the thesis, a
time-based implementation of sigma-delta architecture is presented.
34
4
Time-Based Sigma Delta:
Concept and Architecture
In this chapter, the concept behind the proposed Time-Based Sigma-Delta is
presented and its architecture is described. The system is fully digital consist-
ing of logic gates except for the VTC. What differentiates this architecture from
the previous time-based Sigma-Delta ADCs (5; 17; 19) is that the analog infor-
mation stored in the width of a pulse rather than phase of voltage-controlled
oscillators(VCOs).
4.1 Theory of operation
Let us define a few notations before explaining the operation of time-based sigma-
delta.
4.1.1 Notations
Tmin - The minimum pulse length that must be maintained so that it can prop-
agate through the delay line without distortion of pulse length(see 5.2.6). The
starter should produce an output pulse with length > Tmin.
Tin - The pulse length corresponding to the input voltage Vin.
Tmax - The pulse length corresponding to the maximum input voltage.
35
4.1 Theory of operation
Tref - If the length of pulse is greater than Tref , Vout must be asserted high.
It should ideally be equal to Tsub + Tmin.
Tsub - The pulse length that must be subtracted when Vout is asserted. For
stable operation, Tmax <= Tsub
Tsamp - Time taken to sample the input. This corresponds to the positive
phase of clock
Teval - Time window within which the new pulse length(output of pulse adder)
is evaluated. This corresponds to the negative phase of clock.
Tc - Clock period = Tsamp + Teval.
Tdelay - Delay in ’Delay line’
Ttrip - The maximum delay allowed between -ve edge of clock to positive edge
of subtractor output(and vice-versa). If this is exceeded, Vtrip is asserted.
VoutComp.
VinVTC Adder
Tref
Tadd
Delay
Vout
Trip
Detector
1
3
4
Subtractor
2
(A)
(B)
z-1Vref
1-bit
DAC
VinVout
12
2
3
4
Starter
Figure 4.1: (A) Conventional sigma delta (B) Time-mode sigma-delta
36
4.1 Theory of operation
4.1.2 Block Diagram and Descriprion
In fig 4.1, we show the correspondence between a conventional(A) and the pro-
posed time-based sigma-delta modulator(B). The objective here is to replace the
voltage analog variable of conventional system with time. More specifically, we
intend to use pulse width as the analog variable, where its duration is shortened
or extended during the Sigma-Delta loop operation and is compared to a refer-
ence pulse width to generate the output. In the subsequent sections, we describe
the functionality of individual blocks. The actual circuit implementations would
be described in chapter 5.
4.1.2.1 Adder and Subtractor
Input
Pulse
Output
Pulse
Tin
Tadd
Tout
Tin
Tsub
Tout
Trigger Trigger
(A) (B)
Figure 4.2: (A) Pulse addition (B) Pulse subtraction
The foremost blocks that are necessary for the operation of any feedback sys-
tem (including Sigma-Delta ADCs) are the analog-domain adder and subtractor
(blocks 1 and 2 in Fig 4.1). In the time-domain system, addition and subtraction
are equivalent to extending and reducing the pulse width, respectively. Generally
speaking, if we are dealing with asynchronous digital signals, pulse width exten-
sion can be done only at the falling edge, while reducing the pulse width can be
done only at the rising edge of the pulse. This is due to the fact that the system
37
4.1 Theory of operation
is causal, and hence we cannot predict when the pulse is arriving and when it
ends.
In Fig. 4.2, we show the timing diagram for both the time-based adder and
the subtractor. On important issue in both cases is that the added and subtracted
widths (Tin and Tsub) should be triggered by the incoming pulse, i.e., rising edge
starts the subtraction while the falling edge starts the addition. The important
implication of this on the Sigma-Delta modulator is that we need to be able to
trigger both the input signal (for addition) and the output signal of the 1-bit
DAC (for subtraction) at any given point in time.
4.1.2.2 Delay Component
The delay component (z−1 block of Fig. 4.1) can be created using a digital delay
line (e.g., cascade of inverters). In an ideal case, this delay (Tdelay) needs to be
exactly equal to the oversampling period of the Sigma-Delta modulator, denoted
by Tc . However, due to the pulse width subtraction and addition processes
of the Sigma-Delta loop, the pulse will drift gradually toward end of the clock
window(Teval) as cycles progress. This eventually results in unwanted frame shift
(see Fig. 5.17).
By carefully examining the operation of a time-based Sigma-Delta modulator,
we can prove that it is not necessary to have in each cycle and what is really
required is that places both edges of the processed pulse within the next clock
window. This relaxes the acceptable range of Tdelay and furthermore suggests
that we can use different delays for different cycle without causing any problem.
What we propose here is to make Tdelay not constant, but controllable. What
we propose is to check the rising edge of the pulse in each cycle. Then, depending
on its relative location in that clock window, choose a proper Tdelay to ensure
that the pulse remains in the clock window in the next cycle. In Fig. 4.1, this
operation is carried out by trip detector circuit, where its output, i.e., Vtrip signal,
along with the comparators output, Vout, set the Tdelay of the next cycle. In Fig.
5.17, we illustrate an example pulse width evolution as cycles progress in the
Sigma-Delta modulator. As shown, Tdelay is altered when either the trip circuit
is activated(T2), or when the 1-bit DAC and the subtractor are activated(T3).
38
4.1 Theory of operation
CYCLE
0
1
2
3
4
5
Tc
T1T2
T3
Tsub
Tin
DELAY
T1
T1
T1
T2
T3
Vtrip=
1
Vout=
1
After
addition
After
subtraction
Ttrip
Figure 4.3: Pulse width evolution with cycle
39
4.1 Theory of operation
4.1.2.3 Comparator
Comparing the width of two pulses is similar to detecting racing and if the rising
edges are aligned only depends on their falling edges. In the 1-bit time-based
Sigma-Delta modulator, we use the rising edge of the incoming pulse to initiate
a predefined reference pulse with fixed duration of Tref . Hence, the output of
the time-based comparator is ”0” if the Tref is larger than the pulse width, and
”1” otherwise. As illustrated in Fig. 1B, this output (Vout) can then activate
the subtraction process and effectively create the 1-bit DAC of the Sigma-Delta
modulator.
4.1.2.4 VTC
VTC as discussed in previous chapter is responsible for converting a signal in
voltage domain to time domain. In the topology used here(fig 4.4, the input
signal is sampled on the capacitor (Cs) and when triggered, a current source
discharges the capacitor. The delay between the trigger time and the capacitance
voltage reaching the reference voltage Vref is then proportional to the input value
Vin and, in our Sigma-Delta modulator constitutes the input pulse of width Tin.
This is similar to scheme B in section 3.2.1.2. Here, Tin is given by
Tin =Cs · (Vin − Vref )
Idis
= K · (Vin − Vref ) (4.1)
where,
K =Cs
Idis
(4.2)
(It is to be noted that our zero reference with respect to input voltage is Vin
is Vref .)
4.1.2.5 Starter
The role of starter is to provide the initial pulse of width Tmin to make the system
start working. The pulse-width Tmin is the zero reference for the system.
40
4.1 Theory of operation
Vref
Vin
V0
ISCS
clk Vdis
clk
V0
Vcap
Vcap
VrefVin
Vdis
Figure 4.4: Voltage-Time Converter
4.1.3 Representation in MATLAB
The following matlab code corresponds to the operations described here. Here,
’output’ represents the input for the comparator block.
clear all;
N=2^3;
clock = 0:1:N*2;
pulsemin=0.1;
perioderror=0.1; %Represents mismatch between Tc and Tdelay
vinmax=0.3;
vtripmax=0.3; %Represents Ttrip
pulsep=0; %Positive edge position with respect to clock
pulsen=pulsemin; %Negative edge position with respect to clock
fx = 17e4;
fs = 1e8;
vin = 0.1*sin(2*3.14*(fx/fs)*[0:N-1])+0.1;
flag=0;
for i=1:N
%Pull back pulse if its too far away from clock edge
if pulsep>vtripmax
pulsep = pulsep-vtripmax;
pulsen = pulsen-vtripmax;
end
%Subtraction
if flag==1
pulsep = pulsep + vinmax;
end
41
4.1 Theory of operation
% Modulate pulse length by vin. Contains adjustment when subtraction
% takes place
pulsep = pulsep -(flag*vinmax) + perioderror;
pulsen = pulsen -(flag*vinmax)+vin(i) + perioderror;
% Detect pulse length
if (pulsen-pulsep>=vinmax+pulsemin)
flag=1;
else
flag=0;
end
dout(i) = flag;
output(i*2-1) = clock(i*2-1)+pulsep;
output(i*2) = clock(i*2-1)+pulsen;
end
The code for formatting output is not shown for clarity. The final output is
shown in fig 4.5. Fig 4.6 shows the 10000-point fft for the output obtained in
this model for a 50 KHz sine wave sampled at 100 MHz. It just shows the noise
shaping as no distortion model is present here.
42
4.1 Theory of operation
100
101
102
103
104
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Figure 4.6: Matlab Output(FFT)
44
4.2 Timing constraints
4.2 Timing constraints
Let us now state a few timing constraints that must be met for the circuit to
function correctly:
1) The pulse-adder circuit, being asynchronous in nature, is designed to detect
negative edge of incoming pulse and add Tin to it. Since it operates only during
the negative clock phase(i.e. - during ’Teval’), the negative edge(to pulse-adder
input) has to appear within the Teval window.
2) The pulse-comparator compares the length of incoming pulse to Tref . Even
though its asynchronous in nature, the final output Vout must be synchronized
with the clock for correct Sigma-Delta operation.
We would now examine the implications of these constraints in some extreme
cases. In all these cases, we consider that the only delay in the circuit is the
’delay-block’ and rest of the circuit has no delay.
Clk
Adder Input
Adder Output/
Subtractor Input
Tref - ε
Tmax
This would have
not triggered Vout in previous cycle.
Figure 4.7: Borderline case for maximum pulse width
Maximum pulse width: Let the pulse width at the input of comparator be
Tref − ǫ in one cycle such that Vout is not asserted. If we have maximum possible
Vin at input, we would be adding Tmax in the next cycle(See Fig 4.7). So the
maximum pulse width is
Max.pulsewidth = Tmax + Tref
= Tmax + Tsub + Tmin (4.3)
As Tsub ≥ Tmax is required for correct sigma-delta operation, the maximum
pulse width is
45
4.3 Summary
Clk
Adder Input
Vtrip
Ttrip - ε
Tdelay
~Ttrip+Tdelay-
Tc
Figure 4.8: Maximum separation of pulse positive edge from negative clock edge
Max.pulsewidth = 2 × Tmax + Tmin (4.4)
Minimum Teval: Let the positive edge of pulse-adder input is ahead of neg-
ative edge of clock in a particular cycle by Ttrip − ǫ, where ǫ is a small positive
quantity. Vtrip is not asserted in this cycle but it would be definitely asserted in
next cycle if Tdelay > Tc. In the next cycle, the difference between the two edges
would be Ttrip − Tdelay + Tc (See Fig 4.8).
If we add max. pulse width to this quantity, minimum Teval required becomes
Teval ≥ 2 × Tmax + Tmin + Ttrip + Tdelay − Tc (4.5)
In real circuit, it has to be even more as the pulse-adder and pulse-subtractor
blocks would have delays of their own.
4.3 Summary
In this chapter, The various blocks of Time-Based Sigma Delta like adder, sub-
tractor, comparator were described at functional level and the overall timing
diagram was explained. The bounds for various timing parameters were also de-
rived. With this conceptual background in mind, we would look at the circuit
implementation of the blocks in the next chapter.
46
5
Time-Based Sigma Delta: Circuit
Implementation and Simulation
5.1 Circuit Descriptions
5.1.1 Voltage-Time Converter and Pulse-adder
The circuit implementation of VTC is shown in Fig 5.1. The current source has
cascode configuration in order to minimize dependency of Idis on Vcap. It is to be
noted that when Vdis becomes high, there is an initial transient in Idis before it
settles to a final value. However, this transient is repeatable and independent of
Vin. It only affects the offset term. The transistors M2 and M4 has been added
to cancel clock feed-through due to overlap capacitance.
One concern in this design is the leakage current through M7 when Vdis is
low. It will discharge the capacitor between the interval of CLK going low and
Vdis going high. As the interval is not fixed, it will be like a random noise signal
added to the input.
This VTC is included in the circuit of Fig 5.2 to work like a pulse-adder
(corresponding to integrator of conventional architecture). As said in section
4.1.2.1, the pulse-width can be extended only at negative edge of incoming pulse.
As we can see in the circuit, negative edge of the pulse makes Vdis go high and
activates the current source connected to Cs. Output of gate 1 is a pulse of length
equal to Tin which gets ’added’ to the incoming pulse as shown in Fig 5.3. Since
47
5.1 Circuit Descriptions
Vb1
Vb2 Cs
Vcap
Vin
CLK
CLKc
CLKc
M1 M2
M4M3
M5
M6
M7
CLK
Vdis
Wn
Wp
Wn/2
Wp/2
This inverterdetermines Vref
Vout
100 fF
35 uA
Figure 5.1: Actual circuit implementation of Voltage-Time Converter
48
5.1 Circuit Descriptions
Vdis
Vout
CLK
Vin
VTC
Q
QSET
CLR
DVDD
IN
CLKc
CLK
Vin
CLK
IN
Figure 5.2: Pulse-adder using VTC
Tin
CLK
IN
Vdis
Vout
X
OUT
Figure 5.3: Pulse-adder timing diagram
49
5.1 Circuit Descriptions
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.80
0.5
1
1.5
2
2.5
3
Voltage(V)
Tim
e(ns
)
actualideal
Figure 5.4: Pulse-adder characteristics
the positive phase of clock is used for sampling, the signal ’Pulse-out’ is held low
at this point. So, the negative edge must appear only at negative phase of clock
(i.e - during Teval) as stated in section 4.2.
The simulated result for the transfer curve of this system (VTC + Pulse adder)
is shown in fig 5.4. An input pulse of 2ns width was applied and the width of
output pulse is measured for voltage range 0.9V-1.7V in steps of 100 mV. The
width of the resultant output pulse was measures and the difference in width
between input and output pulses corresponds to the input voltage. The values
were linearly interpolated to obtain the final characteristics. Ideally, 0.9-1.7 V
must correspond to 0-3 ns. The linearity of this system was checked by applying
a sine-wave of 0.8V p-p centred at 1.3V to the obtained transfer characteristics.
The biggest harmonic was ≈ 50 dB below fundamental.
5.1.2 Pulse-Subtractor
As discussed previously, the pulse-subtractor subtracts a fixed width Tref from
pulse whenever Vout is asserted. Due to its asynchronous nature, subtraction (or
pulse-width reduction) can take place only at positive edge (section 4.1.2.1). Fig
50
5.1 Circuit Descriptions
5.5 shows the gate level implementation. The input Vsub would be connected to
the complement of Vout. When Vsub is high (Vout is low), node X is also high. So,
the AND gate just acts as a buffer for the pulse. But when Vsub is low, subtraction
takes place i.e.- pulse width gets reduced by a fixed quantity Tsub as shown in Fig
5.6.
Delay
=TsubVsub
In
X
Y
Figure 5.5: Pulse-Subtractor
Tsub
IN
X
Y
OUT
Figure 5.6: Pulse-Subtractor timing diagram
51
5.1 Circuit Descriptions
5.1.3 Pulse-comparator
The gate level implementation of Pulse-Comparator is shown if Fig 5.7. The
incoming pulse was delayed by a preset duration Tref and fed to the D-input of
DFF1. The DFF is triggered by the negative edge of IN. If the pulse duration is
longer than Tref , a high logic is sampled by DFF1 (and vice versa). This output is
sampled by the clock for synchronization using DFF2 and forms the final output
of the system Vout. This can be considered as a 1-bit Delay-line TDC with ’start’
and ’stop’ being rising and falling edges of same pulse.
D QR
D QR
ClkDelay
=Tref
In
Out
Figure 5.7: Pulse-Comparator
5.1.4 Trip-detector
The trip detector is responsible for detecting whether the positive edge of the
pulse that goes to the input of adder has drifted too much away from negative
clock edge due to difference in Tc and Tdelay. This drift can happen on either
side depending on which one among Tc and Tdelay is greater. So, it produces
two outputs - Vtrippand Vtripn
. These outputs along with Vout are inputs to the
delay-control block. The implementation is quite straightforward as we just need
a D-flip-flop and a delay element as shown in Fig 5.8.
5.1.5 Delay Control
The delay line has a constant component and a variable component controlled
by Vtrip/Vout The scheme for delay control is shown in 5.9. Its mostly self ex-
planatory. The expression inside boxes show their nominal delay. Ideally, the
pulse-width should not change after going through the delay line. If there is a
52
5.1 Circuit Descriptions
Q
QSET
CLR
D
Q
QSET
CLR
D
Ttrip
Ttrip
CLKc
CLKc
IN
IN
Vtripp
Vtripn
Figure 5.8: Trip Detector
distortion of fixed width every cycle, its like an additional offset term. However,
the major concern here is that there are six permutations (23) of possible delay
paths in the delay-control block depending on Vtrip/Vout. If all of them don’t have
same offset, a random noise term will get added.
Vtrippc.Vtripnc
Vtripn
Vtripp
Vcomp
Vcompc
Ttrip
2 * Ttrip
Tsub
IN
OUT
ConstantDelay
Total delay of the dotted path should be nominally equal to T c
Figure 5.9: Delay Control
53
5.1 Circuit Descriptions
5.1.6 Starter
The combination of DFF1 and DFF2 (Fig 5.10) makes X high for one clock
period when ’START’ makes a transition from low to high. When X is high, a
pulse of length Tmin is produced at OUT(Fig 5.11). Fig 5.12 shows how this
pulse is inserted in the loop. The minimum length requirement is determined
by the characteristics of delay elements. We must ensure that the pulse reaches
full scale logic levels(Vdd or ground) at every node of delay-line. If the pulse is
too narrow, it may not reach full scale and the final delay would deviate from its
nominal value.
Q
QSET
CLR
D
Q
QSET
CLR
D
TminX
XSTART
CLK
CLKc
CLK
OUT
Figure 5.10: Starter
Tmin
CLK
START
X
OUT
Figure 5.11: Starter Timing Diagram
54
5.1 Circuit Descriptions
Other
Blocks
CLKCLK
STARTSTART
X
OUT
EN
ENc
MAIN
LOOP
STARTER
Figure 5.12: Insertion of starting pulse in main loop
5.1.7 Delay-Element
The delay elements are building blocks of delay-control block. The role of the
delay element is to provide a finite delay to the pulse with as little distortion to its
width as possible. While distortion by a small fixed width is acceptable as it just
adds an offset term, random variation of the amount of distortion with respect to
time will add noise to the final output spectrum. The delay of the structure should
be controllable so that overall delay of the loop can be brought as close to Tc as
possible. This is required to negate changes in delay due to process variations.
A secondary objective is to reduce power in the delay-line as far as possible. A
potential circuit for providig distortion-free delay is shown in Fig 5.13 (7). It uses
a current-starved inverter structure. The control voltage Vctl sets the maximum
current through MN1 which is the pull-down current. Using MN2 and MP2, a
voltage is set at the gate of MP1 which determines the maximum pull-up current.
Because of the mirroring action, they would be roughly equal. We can use smallest
possible sizes for MN3 and MP3 to save dynamic power. However the tracking
between pull-up and pull-down current is hard to maintain over process corners
since its a single-transistor current mirror. Also, the MN2-MP2 pair consumes
55
5.1 Circuit Descriptions
static power. Even though they can be shared among multiple elements, the
power spec takes a huge hit if multiple control voltages are required(which would
usually be the case).
IN
VCTL
OUT
VDD
MP1MP2
MP3
MN2 MN1
MN3
Figure 5.13: Delay Element 1
Instead of trying to make the pull-up and pull-down currents equal, a better
strategy is to have two slow transitions in the path which can potentially track
each other over process variations with an odd number of transitions in between.
56
5.2 Simulation Results
One of them will produce delay for the rising edge while the other will produce
the same delay for falling edge. Thus, we should have an overall delay without
distortion of pulse width. This is achieved using the circuit in Fig 5.14. As
we can see, inverters 3 and 6 have a current-starved pull-down part contolled
by VCTL. These gates along with the capacitors at output should be carefully
matched by proper layout. It is to be noted that as gates 4 and 7 will see a slow
transition at input, they should be built with longer channel lengths in order
to reduce shoot-through current. We can also see that if two or more of these
elements are cascaded together, we see path containing similar types of elements
between two slow transitions. This further helps in cancelling any pulse-width
distortion.
1 2 6543
VCTL VCTL
OUT
LongChannel
LongChannel
2X 2XCurrent-
Starved
Current-
Starved20 fF 20 fF
Figure 5.14: Delay Element 2(actually used)
5.2 Simulation Results
The detailed block diagram of proposed sigma-delta modulator is given in fig
5.15. The proposed circuit was designed and simulated in TSMC 0.18µm CMOS
process as a proof of concept. A SNDR of 39.4 dB was achieved for an input
frequency of 70Khz and 200mV(p-p) centred at 1.3V. The FFT plot(with log
scale applied to frequency axis) is shown in fig 5.16. It was taken using 6670
sample points. The reason for choosing such unusual number of sampling points
was that it would theoretically place the signal at bin 7(Sampling freq ≈ 66.7
MHz). This reduces spreading of signal energy to other bins and makes SNDR
calculations easier. Fig 5.17 shows the actual input and output waveforms of
sigma-delta modulator. The power consumption of the system was 212 µW . This
does not include the static power consumed by references.
57
5.2 Simulation Results
Vtrippc.Vtripnc
Vtripn
Vtripp
Vcomp
Vcompc
Delay=
Ttrip
VTC
Q
QSET
CLR
DVDDCLKc
CLK
Vin
CLK
IN
CLKCLK
STARTSTART
X
OUT
EN
STARTER
ENB
SUBTRACTOR
Q
QSET
CLR
D
Q
QSET
CLR
D
CLKc
CLKc
Vtripp
Vtripn
Ttrip
Ttrip
Vcomp = Vout
Delay=
Tsub
Delay=
2*Ttrip
VTC+PULSE-ADDER
TRIP-DETECTOR
IN OUT
VSUB
IN OUT
CLK
CLK
COMPARATOR
Vcomp
Vdis
Vout
CLK
Vin
IN
Constant
Delay
DELAY CONTROL
Figure 5.15: Detailed block diagram of proposed sigma-delta
58
5.2 Simulation Results
Figure 5.16: Simulation results for Power Spectral Density
59
5.2 Simulation Results
Figure 5.17: Simulation results for Input and Output Waveform
The nominal timing parameters are defined in Table 5.1. Table 5.2 summarizes
the simulation results
In table 5.3, the present implementation of time-based sigma delta is compared
against other implementations.
60
5.2 Simulation Results
Tmin 1ns
Tin 0-3ns
Tsub 3ns
Tref 5ns
Ttrip 300ps
Tdelay 15ns
Tsamp 5ns
Teval 10ns
Table 5.1: Nominal timing paramaters
Technology TSMC 0.18µm CMOS (CM0180)
Power Consumption VTC+Pulse-adder: 114µW
Delay Line: 72µW
Total: 211µW
Performance Vin: 0.9-1.7 V
BW: 500Khz
Sampling frequency: 67MHz
OSR: 134
ENOB: 6.2
Table 5.2: Performance Summary
61
5.2 Simulation Results
This Thesis (19) (17)
Samplingfrequency 67 MHz 140 MHz 800 MHz
SNDR 39.4 dB @ 500 KHz 42.2 dB @ 400 KHz 39 dB @ 1 MHz
Power 211µW 475µW 150 mW
Technology 0.18µm 0.18µm 0.18µm
Table 5.3: Comparison with other implementations
62
5.3 Summary
5.3 Summary
In this chapter the circuit implementation of various components of sigma-delta
modulator was described with their corresponding waveforms. Lastly, the simu-
lation results were presented and compared against an existing implementation.
63
6
Discussion and Conclusion
6.1 Contribution of this work
An architecture for implementing a Time-Based Sigma-Delta ADC was presented
and the simulation results were shown as a proof of concept. However, this circuit
needs to be qualified on silicon in order to catch potential hazards not apparent
by simulations alone. While the performance is currently a bit inferior in terms
of ENOB, it certainly saves lot of power compared to (19).
One of the most significant contribution of this thesis are the novel architec-
tures and circuits for performing pulse-width based addition/integration, subtrac-
tion and comparison. If the implementation of the delay line is further enhanced
in terms of maintaining consistent pulse widths(and potentially with less power),
the performance of the overall ADC would be significantly improved.
6.2 Fundamental power limits comparison
In this section, we present a comparison between power limits of conventional
and time-based sigma delta architectures for a given SNR specification.
6.2.1 Conventional Sigma-Delta Power Limit
The power consumption of a Conventional sigma-delta is dominated by that of
first stage integrator. Before deriving the power vs SNR tradeoff for the inte-
64
6.2 Fundamental power limits comparison
grator, let us first consider the tradeoff for a simple class-A sample-hold circuit
shown in fig. 6.1. Most of the analysis presented in this section can be found in
(16)
S/H Class-A
Vsig
Vsig
1 2 3
1
2
3
Slewing
Linear Settling
Figure 6.1: Class-A Sample Hold
Let us first assume the case where the output slews from a reset state to the
final value within 1/2 sampling period. The quiescent current is given by.
Ibias = CdV
dt= 2CVsigfs (6.1)
If the entire supply voltage is used for signal swing, the power dissipation is
65
6.2 Fundamental power limits comparison
P = 2 · Vsig · Ibias (6.2)
The SNR is given by
SNR =(2 · Vsig)
2
12 · 22n(6.3)
If this is equated to KT/C noise, C is given by.
C =12 · K · T · 22n
Vsig2 (6.4)
Combining 6.2 and 6.4, we get
P = 12 · k · T · 22n · fs (6.5)
Let us consider a second case where the amplifier does not slew at all. The
minimum bias current is given by
Ibias = C · VFS · 1
τ(6.6)
where τ is the time constant.
If n bits of precision is required, the signal has to settle within 2−n of full scale
within half sample period.
τ =1
2 · fs · n · ln2(6.7)
So, the power is given by
P = 12 · k · T · 22n · fs · n · ln2 (6.8)
Using a similar approach, we would derive the fundamental power limits of
sigma-delta. The power dissipation of a sigma-delta will be dominated by its first
66
6.2 Fundamental power limits comparison
Φ1
Φ1Φ2
Ib
gm
C1
C2
C3
VDD
Vi
Vo
Ib
gmC3
VDD
Vi
Vo
G.β
β
(A)
(B)
Figure 6.2: (A) Simplified switch-capacitor integrator (B) Model for redistribu-
tion phase
67
6.2 Fundamental power limits comparison
stage integrator. Figure 6.2(A) shows a simple model of a switched capacitor
integrator while 6.2(B) shows the model for charge redistribution phase(φ2 is
high). In this configuration, gain(G) = −C1/C2 while Feedbackfactor(β) =
C2/(C1 +C2), if we consider open loop gain of the common source amplifier to be
high enough. The capacior C3 represents explicit load capacitance plus loading
from feedback network.
In feedback configuration, output resistance(R) is given by
R =1
β · gm
=1 + |G|
gm
(6.9)
So, the total integrated noise at the output is given by
vo2 = 4KTγgmR2 · 1
4RC3
=kT
C3
· γ · (1 + |G|) (6.10)
If we refer this noise to input and set it equal to the quantization noise of a
n-bit converter,
C3(min) = 12kTγ · 1 + |G|G2
· 22n
VFS2 (6.11)
The power(or the minimum Ib) required can be calculated similar to section
5.2.1.
For slew settling
Ib(sl) = C3VFS · 2fs (6.12)
The power is given by
Power(lin) = 24kTγ · 22n · fs ·1 + |G|
G2(6.13)
68
6.2 Fundamental power limits comparison
For linear settling, we first need to find the minimum gm required. The time
constant of the circuit(τ) is given by
τ =1 + |G|
gm
· C3 (6.14)
Ib is given by gmVeff where Veff = Vgs−Vth
2
Combining it with eq. 6.14 and the value of τ we get in ??, we get
Ib(lin) = C3Veff · nln2 · 2fs · (1 + |G|) (6.15)
The power is given by
Power(sl) = 24kTγ · 22n · fs · nln2 · (1 + |G|)2
G2(6.16)
6.2.2 Time-Based Sigma Delta Power Limit
C C
IN OUT
x K
Figure 6.3: Simplified model of delay element
The primary source of noise in this design is the delay line shown in 5.14.
We can use a simple model as shown in 6.3 and consider k of them in cascade.
Total delay produced is Tdelay. So, delay in each of them must be Tdelay/k. The
thermal noise in the delay elements will manifest as jitter in time domain. So,
there would be an uncertainty in the time of arrival of the edges. An analysis for
69
6.3 Future work
a similar case was done in (1). According to that, jitter noise for an edge is given
by.
σjitter2 =
(
8kTγ
CVDD(VDD − Vth)+
4kT
CVDD2
)
·(
Tdelay
k
)2
· k (6.17)
Since we are concerned about the actual pulse width, we have two edges(rising
and falling) to deal width. So, the total noise in pulse width is obtained by
multiplying a factor of 2.
The time corresponding to maximum voltage is Tmax. So, the jitter noise
target for n bits of accuracy is Tmax
12·22n .
So, the capacitance is given by
C = 24 ·(
8kTγ
CVDD(VDD − Vth)+
4kT
CVDD2
)
·(
Tdelay
Tmax
)2
· 1
k· 22n (6.18)
Total power is given by
Power = k · C · VDD2 · f (6.19)
= 24 ·(
8kTγ · VDD
VDD − Vth
+ 4kT
)
·(
Tdelay
Tmax
)2
· 22n · f
This equation tells that power consumption of this design will be higher than
conventional topology. So, this will make sense only when the supply voltage is
too low to allow design of conventional modulators.
6.3 Future work
The immediate work is to tape-out the circuit and test its performance on real
silicon which unfortunately couldn’t be included in thesis due to time constraints.
Further work will involve trying to improve the performance of VTC and
making some more power-efficient architecture for delay elements or finding other
ways of storing pulse width of previous cycle. One possibility might be dumping
charge on a capacitor with a constant current source during the duration of the
pulse. However, the efficiency of that method needs to be carefully evaluated.
70
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73
Vita
Arnab Kumar Dutta was born on July 11, 1984, in the city of Kolkata, West
Bengal, India. He completed his Btech. in Electrical Engineering from the Indian
Institute of Technology Kharagpur in May 2007 and has been pursuing Masters in
Electrical and Computer Engineering at The University of Texas at Austin since
August 2008. He was employed one year at Nvidia Graphics, Bangalore during
the period July 2007-July 2008 as a Hardware Engineer. His research interests
include Analog and Mixed-Signal Circuit Design Design.
centerThisthesiswastypedbytheauthor.
Permanent Address:
306 E. 30th Street, Apt 3
Austin, TX 78705
Email:
74
