Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II...
-
Upload
sherilyn-barnett -
Category
Documents
-
view
228 -
download
0
Transcript of Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II...
![Page 1: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/1.jpg)
Copyright © 2005 Altera Corporation
Accelerating Design Cycles Using Quartus II
Accelerating Design Cycles Using Quartus II
SignalTap II Embedded Logic AnalyzerSignalTap II Embedded Logic Analyzer
![Page 2: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/2.jpg)
2
Copyright © 2005 Altera Corporation
SignalTap II AgendaSignalTap II Agenda SignalTap II Overview & Features Using SignalTap II Interface Advanced Triggering
![Page 3: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/3.jpg)
3
Copyright © 2005 Altera Corporation
SignalTap II ELASignalTap II ELASignalTap II ELASignalTap II ELA Captures the Logic State of FPGA Internal
Signals Using a Defined Clock Signal Gives Designers Ability to Monitor Buried Signals Connects to Quartus II through FPGA JTAG Pins Captures Real-Time Data
Up to 200 Mhz Is Available for Free
Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer
![Page 4: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/4.jpg)
4
Copyright © 2005 Altera Corporation
SignalTap II Device SupportSignalTap II Device Support
Stratix & Stratix II Stratix GX Cyclone & Cyclone II Excalibur Mercury APEX II APEX 20K/E/C
![Page 5: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/5.jpg)
5
Copyright © 2005 Altera Corporation
How Does It Work?How Does It Work?How Does It Work?How Does It Work?
1. Configure ELA2. Download ELA into
FPGA along with Design
3. ELA Samples Internal Signals
4. Quartus II Communicates with ELA through JTAG
![Page 6: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/6.jpg)
6
Copyright © 2005 Altera Corporation
ELA Resource UtilizationELA Resource Utilization ELA Uses Device Resources for Implementation
ALMs/LEs for ELA Megafunction & Routing Memory for Sample Storage
LE Count Is a Function of the Number of Channels & Trigger Levels
Memory Block Count Is a Function of Number of Channels & Sample Depth Selectable Trade-off Between Depth & Number of
Channels 128K Sample Depth with 1024 Channels Is Not
Practical – 32,768 M4K Blocks
![Page 7: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/7.jpg)
7
Copyright © 2005 Altera Corporation
Stratix/Cyclone Sample Resource UsageStratix/Cyclone Sample Resource Usage
Number of Channels
Logic Elements
Trigger Level 1 Trigger Level 2 Trigger Level 3
8 316 371 426
32 566 773 981
256 2900 4528 6156
Number of Channels
M4Ks Based on Sample Depth
256 512 2K 8K 32K
8 < 1 1 4 16 64
32 2 4 16 64 256
256 16 32 128 512
![Page 8: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/8.jpg)
8
Copyright © 2005 Altera Corporation
Modes of OperationModes of OperationModes of OperationModes of Operation
Three Different Configurations Internal RAM ELA Configuration Debug Port ELA Configuration Hybrid Approach
Provides Flexibility Based on Available Device Resources Memory Resources Are Limited
Use Debug Port Configuration Pin Resources Are Limited
Use Internal RAM Configuration
![Page 9: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/9.jpg)
9
Copyright © 2005 Altera Corporation
Internal RAM ConfigurationInternal RAM ConfigurationInternal RAM ConfigurationInternal RAM Configuration Acquired Data Saved in Device Internal RAM Streamed Off-device through JTAG Port LEs Required to Implement ELA Core Logic
ELACore Logic
ELAMemory
Signals FromInternal Nodes
JTAG Port To JTAGConnector
![Page 10: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/10.jpg)
10
Copyright © 2005 Altera Corporation
Debug Port ConfigurationDebug Port ConfigurationDebug Port ConfigurationDebug Port Configuration
Acquired Data Routed to Unused Device I/O Pins Captured by External Logic Analyzer or Oscilloscope
LEs Required to Implement ELA Core Logic I/O Pins Required for External Analysis
Signals FromInternal Nodes
To UnusedI/O Pins
Signals toDebug Ports
ELACore Logic
![Page 11: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/11.jpg)
11
Copyright © 2005 Altera Corporation
Supported Download CablesSupported Download Cables
USB Blaster USB Port Cable
ByteBlaster™ II Parallel Port Cable
ByteBlasterMV™
Parallel Port MasterBlaster™
USB / Serial Port Cable
![Page 12: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/12.jpg)
12
Copyright © 2005 Altera Corporation
SignalTap II Key FeaturesSignalTap II Key Features
Setup Data Triggering Data Capture Data Analysis
![Page 13: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/13.jpg)
13
Copyright © 2005 Altera Corporation
Setup FeaturesSetup Features Up to 1024 Data Channels Multiple Analyzers in One Device
Supports Analysis of Multiple Clock Domains
Each Analyzer Can Run Simultaneously
Resource Usage Estimation Incrementally Routes New Signals
Setup
Data Triggering
Data Capture
Data Analysis
![Page 14: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/14.jpg)
14
Copyright © 2005 Altera Corporation
Data Triggering FeaturesData Triggering Features Up to 10 Trigger Levels Per Channel
Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes
Defines a Sequential Pattern of Logic Conditions
Each Trigger Level is Logically ANDED If (L1 & L2 ... & L10) == TRUE Data Capture
Setup
Data Triggering
Data Capture
Data Analysis
![Page 15: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/15.jpg)
15
Copyright © 2005 Altera Corporation
Data Triggering Features (Cont.)Data Triggering Features (Cont.) Three Main Trigger Positions
Trigger Input Setup External Trigger to Trigger the Analyzer
Trigger Output Signifies Trigger Event Occurred with SignalTap II
Use One ELA’s Trigger Output as Trigger Input for Another
Data Triggering
Setup
Data Triggering
Data Capture
Data Analysis
TIME
Old Samples New Samples
trigger
Samples CapturedSamples Captured
![Page 16: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/16.jpg)
16
Copyright © 2005 Altera Corporation
Data Capture FeaturesData Capture Features Up to 128K Samples Per Channel
Increases Chance of Catching Target Event
Two Methods of Data Acquisition
1. Circular 2. Segmented
Mnemonic Tables Create User-Defined Labels for Bit Sequences
(Ex. State Machine)
Setup
Data Triggering
Data Capture
Data Analysis
![Page 17: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/17.jpg)
17
Copyright © 2005 Altera Corporation
Data Analysis FeaturesData Analysis Features Data Export
Save Real Time Data & Apply Data as Stimulus to Simulation
Data Log Keep a a Log of Captured Data Compare Old Data Vs. New Data
Setup
Data Triggering
Data Capture
Data Analysis
![Page 18: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/18.jpg)
18
Copyright © 2005 Altera Corporation
SignalTap II AgendaSignalTap II Agenda SignalTap II Overview & Features Using SignalTap II Interface Advanced Triggering
![Page 19: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/19.jpg)
19
Copyright © 2005 Altera Corporation
SignalTap II Design FlowSignalTap II Design Flow
1) Use SignalTap II File (.STP) Use Quartus II GUI STP Separate from Design Files
2) Use Quartus II MegaWizard Instantiate Directly into HDL
![Page 20: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/20.jpg)
20
Copyright © 2005 Altera Corporation
Using STP FileUsing STP File
1. Create .STP File• Assign Sample Clock• Specify Sample Depth• Assign Signals to STP File• Specify Triggering• Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
![Page 21: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/21.jpg)
21
Copyright © 2005 Altera Corporation
1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File1) Creating a New .STP File To Create a .STP File
Method 1 Select the in Quartus II
Method 2 Select New (File Menu) Other Files SignalTap II File
Default File Name Will Be STP1.stp
![Page 22: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/22.jpg)
22
Copyright © 2005 Altera Corporation
Main .STP File ComponentsMain .STP File Components
Signal Configuration
JTAG Chain Configuration
Waveform Viewer
.STP FileInstance Manager
![Page 23: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/23.jpg)
23
Copyright © 2005 Altera Corporation
Instance ManagerInstance Manager
Instance Manager Selects Current ELA to Setup/View Displays the Current Status of each Instance Displays Size (Resource Usage) of ELA
![Page 24: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/24.jpg)
24
Copyright © 2005 Altera Corporation
Signal ConfigurationSignal Configuration
Manages Data Capture & Signal Configuration Sample Clock Sample Depth Trigger Position Trigger-In & Trigger-Out
![Page 25: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/25.jpg)
25
Copyright © 2005 Altera Corporation
Assign Sample ClockAssign Sample Clock Use Global Clock for Best
Results Data Written to Memory on
Every Sample Clock Rising Edge
Clock Signal Cannot Be Monitored as Data
External Clock Pin Created Automatically if Clock Unassigned auto_stp_external_clock ELA Expects External Signal to
be Connected to Clock Pin
![Page 26: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/26.jpg)
26
Copyright © 2005 Altera Corporation
Specify Sample DepthSpecify Sample Depth Sample Depth
Set Number of Samples Stored for each Data Signal
0 to 128K Sample Depth 0 Selected When External
Analyzer Is Used
Select RAM Type for Stratix & Stratix II Devices Useful when Preserving a
Specific Memory Type is Necessary
![Page 27: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/27.jpg)
27
Copyright © 2005 Altera Corporation
Data CaptureData Capture Circular
Specify Trigger Position Pre Center Post Continuous
Segmented Specify Segment Depth
![Page 28: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/28.jpg)
28
Copyright © 2005 Altera Corporation
Circular BufferCircular Buffer
1. Data is Circled through the Acquisition Buffer until the Trigger Event Occurs
2. After the Trigger Event Occurs, Post-Trigger Data is Collected until the Buffer Fills up
![Page 29: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/29.jpg)
29
Copyright © 2005 Altera Corporation
Example: Circular BufferExample: Circular Buffer
![Page 30: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/30.jpg)
30
Copyright © 2005 Altera Corporation
Segmented BufferSegmented Buffer
Acquisition Buffer is Segmented into a Smaller, User Defined Blocks Example: 4K is segmented into 4-1K segments
1. Data is Circled through the Acquisition Buffer until the Trigger Event Occurs
2. When the Trigger Event Occurs, Post-Trigger Data is Collected until the Segment Fills up
3. Process Repeats until all Segments are Filled
Segment 1 Segment 2 Segment 3Trigger Event
![Page 31: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/31.jpg)
31
Copyright © 2005 Altera Corporation
Example: Segmented BufferExample: Segmented Buffer
![Page 32: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/32.jpg)
32
Copyright © 2005 Altera Corporation
TriggeringTriggering Trigger Levels
Indicate up to 10 Trigger Conditions
Trigger-In Any I/O Pin Can Trigger the
SignalTap II Analyzer Generates auto_stp_trigger_in_n Pin
Trigger-Out Indicates When a Trigger Pattern
Occurs Generates auto_stp_trigger_out_n
Pin Delayed 4 Clock Cycles after Actual
Trigger Event
![Page 33: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/33.jpg)
33
Copyright © 2005 Altera Corporation
Waveform ViewerWaveform Viewer
Setup Tab Describes the Signal Settings Data Signals vs. Trigger Signals Sets up Each Triggering Level (L1 – L10)
Data Tab Displays Captured Data
![Page 34: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/34.jpg)
34
Copyright © 2005 Altera Corporation
STP File Waveform ViewerSTP File Waveform Viewer
Setup Tab
Data Tab
![Page 35: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/35.jpg)
35
Copyright © 2005 Altera Corporation
Set up Waveform ViewerSet up Waveform Viewer Add Signals to Viewer Window
Use Node Finder Main Menu, Toolbar, or Right-Click Click Only Signals that Are Found Using the SignalTap II Filter in the Node
Finder Can Be Captured
Important: Not All Signals Are Available
Data Enable Column Check Box Controls Whether Signal Is Captured As Data Ex. Removing Reduces Sample Memory Size
Trigger Enable Column Check Box Controls Whether Signal Is Disregarded as a Trigger Pattern Ex. Signal Used Only for Data Collection
![Page 36: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/36.jpg)
36
Copyright © 2005 Altera Corporation
Basic TriggeringBasic Triggering
Right-Click to Set Value
All Signals Must Be True for Level to Cause Data Capture
![Page 37: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/37.jpg)
37
Copyright © 2005 Altera Corporation
Debug PortDebug Port Routes Data Signals to Spare I/O Pins for
Capture by External Logic Analyzer Quartus II Automatically Generates
auto_stp_debug_out_m_n Pin m Represents the Instance Number of the Analyzer n Represents the Order the Debug Port Pin Occurs
in the Signal List
![Page 38: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/38.jpg)
38
Copyright © 2005 Altera Corporation
Mnemonic TableMnemonic Table Allows a Set of Bit Patterns
to Be Assigned User-Defined Names Right-Click in the Setup View
of an STP File & Select Mnemonic Setup
Select Add Table Select Add Entry
Ex. State Machines or Decoders/Encoders
![Page 39: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/39.jpg)
39
Copyright © 2005 Altera Corporation
JTAG Chain ConfigurationJTAG Chain Configuration
Select Programming Hardware Scan Chan Button Automatically
Determines Devices Physically Connected to the Chain
Detects Non-Altera Devices & Displays Them as Unknown
![Page 40: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/40.jpg)
40
Copyright © 2005 Altera Corporation
2) Save .STP File & Compile2) Save .STP File & Compile
SignalTap II Logic Analyzer Control in Compiler Settings Assignments Settings Specify the STP File to Compile with Project
![Page 41: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/41.jpg)
41
Copyright © 2005 Altera Corporation
3) Program Device(s)3) Program Device(s) Use Quartus II Programmer or STP File
Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain
Use Quartus II Programmer to Program Multiple Devices
Can Create a STP File for each Device in the JTAG Chain
![Page 42: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/42.jpg)
42
Copyright © 2005 Altera Corporation
4) Acquire Data4) Acquire Data
SignalTap II Toolbar & STP File Controls
Run Autorun Stop Read Data (Reads in Data from Last Analysis)
![Page 43: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/43.jpg)
43
Copyright © 2005 Altera Corporation
Displaying Acquired DataDisplaying Acquired Data
Display Signal as Bar or Line Chart Export to Other Tools for Viewing or Analysis
(File Menu) Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File
Format in Time or Sample Number
![Page 44: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/44.jpg)
44
Copyright © 2005 Altera Corporation
Using STP File ReviewUsing STP File Review
1. Create .STP File• Assign Sample Clock• Specify Sample Depth• Assign Signals to STP File• Specify Triggering• Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
![Page 45: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/45.jpg)
45
Copyright © 2005 Altera Corporation
Using MegaWizardUsing MegaWizard
1. Create Instantiation Using MegaWizard• Number of Data Channels• Sample Depth• Number of Triggers Inputs• Number of Trigger Levels (Advanced/Basic)
2. Instantiate into Design
3. Synthesize Design
4. Create STP File Based on Instances & Edit
5. Acquire Data
![Page 46: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/46.jpg)
46
Copyright © 2005 Altera Corporation
1) Create Instantiation1) Create InstantiationSize SignalTap II Instance
Basic or Advanced Triggering?
![Page 47: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/47.jpg)
47
Copyright © 2005 Altera Corporation
2 & 3) Instantiate & Synthesize2 & 3) Instantiate & Synthesize
![Page 48: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/48.jpg)
48
Copyright © 2005 Altera Corporation
4) Create STP File (File Menu) & Edit4) Create STP File (File Menu) & Edit
Generates New STP File Based on Number Design Instances
![Page 49: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/49.jpg)
49
Copyright © 2005 Altera Corporation
RecompilationRecompilation Recompilation Required
Addition/Removal of Instance, Data or Trigger Modifying the Sample Clock or Buffer Depth Enabling/Modifying Trigger-In/Trigger-Out Enabling the Debug Port
Lock Mode Prevents Changes Requiring Recompilation
![Page 50: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/50.jpg)
50
Copyright © 2005 Altera Corporation
Incremental RoutingIncremental Routing
Switches between Nodes without Full Recompilation
Maximizes Effectiveness
![Page 51: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/51.jpg)
51
Copyright © 2005 Altera Corporation
SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing Switches between Nodes without Full Recompilation
1) Enable Smart Recompilation
2) Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers
![Page 52: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/52.jpg)
52
Copyright © 2005 Altera Corporation
SignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental RoutingSignalTap II Incremental Routing
Step 3: Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed SignalTap II: Pre-Synthesis Nodes Always Cause a Full
Recompilation if Added Later Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is
that They Can Be Removed & Replaced with Post-fitting Nodes without a Total Recompilation
Pre-Synthesis Nodes
Post-fitting Nodes
![Page 53: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/53.jpg)
53
Copyright © 2005 Altera Corporation
Quartus II Netlist OptimizationQuartus II Netlist Optimization New Synthesis Optimization Features Do Not
Work Well with SignalTap II SignalTap II Nodes may Disappear Register Re-timing & WYSIWYG Re-Synthesis Should
be Disabled if SignalTap II is Used
Set the Netlist Optimizations Logic Option to Never Allow on Entities Which Have SignalTap II Nodes
![Page 54: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/54.jpg)
54
Copyright © 2005 Altera Corporation
SignalTap II & LogicLockSignalTap II & LogicLock
SignalTap II can Potentially Effect the Performance of a Design Routing and/or Placement Can Change
Possible Solution: LogicLock Use LogicLock to Place Design Blocks within
Specific Regions Place the SignalTap II Block in its Own
LogicLock Region
See Appendix for Example of Using LogicLock with SignalTap II
![Page 55: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/55.jpg)
55
Copyright © 2005 Altera Corporation
Exercise
![Page 56: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/56.jpg)
56
Copyright © 2005 Altera Corporation
SignalTap II AgendaSignalTap II Agenda SignalTap II Overview & Features Using SignalTap II Interface Advanced Triggering
![Page 57: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/57.jpg)
57
Copyright © 2005 Altera Corporation
Advanced TriggeringAdvanced Triggering
Create Advanced Boolean Functions Using Pre-Synthesis Nodes
Trigger Result
SignalTap II Nodes
Boolean Function Composed of Multiple Objects
![Page 58: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/58.jpg)
58
Copyright © 2005 Altera Corporation
Enabling Advanced TriggeringEnabling Advanced Triggering
1. Change the Trigger Level Type from Basic to Advanced Triggering
2. A New Advanced Trigger Tab & Window Will Appear
![Page 59: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/59.jpg)
59
Copyright © 2005 Altera Corporation
Advanced Trigger WindowAdvanced Trigger Window
![Page 60: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/60.jpg)
60
Copyright © 2005 Altera Corporation
Advanced Trigger WindowAdvanced Trigger Window
Node List Lists Available Nodes for Advanced Triggering
Pre-Synthesis Nodes Only
Object Library Lists Functions Necessary to Build Equations
Advanced Trigger Condition Editor Graphic Tool to Build Equation
![Page 61: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/61.jpg)
61
Copyright © 2005 Altera Corporation
Object LibraryObject Library
Object Type SettingsEdge & Level Detector Pos/Neg Edge, Levels
Input Objects Bit & Bus Values
Comparison Operators <, <=, =, !=, >, >=
Bitwise Operators Bitwise AND, OR, XOR, Complement
Logical Operators Logical NOT, AND , OR, XOR
Reduction Operators Reduction AND, OR, XOR
Shift Operators Left/Right Shift
![Page 62: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/62.jpg)
62
Copyright © 2005 Altera Corporation
Advance Trigger Condition EditorAdvance Trigger Condition Editor
1. Click & Drag from Node List/Object Library into Editor
![Page 63: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/63.jpg)
63
Copyright © 2005 Altera Corporation
Advance Trigger Condition EditorAdvance Trigger Condition Editor2. Connect Nodes & Objects
Use Automatic Connection by Positioning Click & Drag Output Ports to Draw Wires
![Page 64: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/64.jpg)
64
Copyright © 2005 Altera Corporation
Advance Trigger Condition EditorAdvance Trigger Condition Editor
3. Connect to Result Block
![Page 65: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/65.jpg)
65
Copyright © 2005 Altera Corporation
Object PropertiesObject Properties General Tab
Change the Object Type Add Your Own Object
Name
Parameter Tab Set Bus or Bit Value Switch Between
Operators of the Same Object Type
Insert Pipelining
Double-Click on an Object to Open Object Properties
![Page 66: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/66.jpg)
66
Copyright © 2005 Altera Corporation
Post-Fitting NodesPost-Fitting Nodes Results of Basic Triggering Conditions Can Be
Used For Advanced Triggering
![Page 67: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/67.jpg)
67
Copyright © 2005 Altera Corporation
Example (1)Example (1) Trigger on the Following Condition
If (Control =1) OR (d = F0h) AND (result = 10Fh)
Pre-synthesis Nodes: Control d[7:0]
Post-synthesis Node: result[11:0]
![Page 68: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/68.jpg)
68
Copyright © 2005 Altera Corporation
Example (2)Example (2)
Edit Basic Trigger Conditions - result
![Page 69: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/69.jpg)
69
Copyright © 2005 Altera Corporation
Example (3)Example (3)
Change to Advance Trigger Condition
![Page 70: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/70.jpg)
70
Copyright © 2005 Altera Corporation
Example (4)Example (4)
Add Rest of Pre-Synthesis Nodes
![Page 71: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/71.jpg)
71
Copyright © 2005 Altera Corporation
Example (5)Example (5)
![Page 72: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/72.jpg)
72
Copyright © 2005 Altera Corporation
Compiling with SignalTap IICompiling with SignalTap II Any Object Parameter with a White Background
is Runtime Configurable Change Does Not Require a Full Compilation
Any Other Changes Require a Full Compilation
The User Entered Bus Value Constant is
Runtime Configurable
The Comparator Setting is also Run Time
Configurable
![Page 73: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/73.jpg)
73
Copyright © 2005 Altera Corporation
Data DelayData Delay Delays a SignalTap II
Node by a User Specified Number of Sampling Clock Cycles
Object Properties Dialog Box
![Page 74: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/74.jpg)
74
Copyright © 2005 Altera Corporation
Data Delay ExampleData Delay Example
Trigger Out Latency: 6 Clock Cycles
Clock
Instruction Register 0x02 0x030x01
Trigger Condition 1
If (Opcode = 0x01) followed by (Opcode = 0x02) followed by (Opcode = 0x03)
![Page 75: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/75.jpg)
75
Copyright © 2005 Altera Corporation
Allows User to Debug Logic Design Problems during Circuit Operation at System Speed
Provides Easy Setup & Visibility of Internal Nodes without External Analyzer
SignalTap II ELA SummarySignalTap II ELA Summary
![Page 76: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/76.jpg)
Copyright © 2005 Altera Corporation
Accelerating Design Cycles Using Quartus II
Accelerating Design Cycles Using Quartus II
SignalProbe Incremental RoutingSignalProbe Incremental Routing
![Page 77: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/77.jpg)
77
Copyright © 2005 Altera Corporation
SignalProbe Incremental RoutingSignalProbe Incremental Routing
Fast Incremental Routing of Debugging Signals (Test Points) to Spare/Reserved I/O Pins Uses Any Available Routing without Full Recompilation
JTAG
Logic
Available Routing
Unused I/O
Debugging Cell
Used Routing
![Page 78: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/78.jpg)
78
Copyright © 2005 Altera Corporation
SignalProbe AdvantagesSignalProbe Advantages
Simple to Use Quartus II Handles Signal Routing
User Only Specifies Source Node & Destination Pin Quartus II Reports Delay Times from Node to Pin
User Can Test Output of Any Hard Node Placement of Compiled Design Remains
Unaffected fMAX of Signal Being Debugged Unchanged
SignalProbe Uses Incremental Routing Compilation Time Typically <10% of Full Compilation
Time
![Page 79: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/79.jpg)
79
Copyright © 2005 Altera Corporation
SignalProbe Supported DevicesSignalProbe Supported Devices
Stratix II Stratix Stratix GX Cyclone MAX II Excalibur APEX II APEX 20K/E/C
![Page 80: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/80.jpg)
80
Copyright © 2005 Altera Corporation
1. Enable Smart Compilation Assignments Settings Compiler Process
2. Reserve SignalProbe Output Pins
3. Compile Design (Optional)
4. Assign SignalProbe Source (Debugging Nodes)
5. Add Pipeline Registers & Clock, if Needed
Using SignalProbeUsing SignalProbe
![Page 81: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/81.jpg)
81
Copyright © 2005 Altera Corporation
6. Perform SignalProbe Compilation Processing Start Start SignalProbe Compilation
7. Program Device
8. Repeat Steps 4-7 to Change SignalProbe Sources
Using SignalProbe (cont.)Using SignalProbe (cont.)
![Page 82: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/82.jpg)
82
Copyright © 2005 Altera Corporation
Assign SignalProbe Dialog BoxAssign SignalProbe Dialog Box
![Page 83: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/83.jpg)
83
Copyright © 2005 Altera Corporation
Reserve SignalProbe PinsReserve SignalProbe Pins
Type Reserved Pin Name
Enable SignalProbe
Select Pin Number
Click Add
Assign I/O Standard
![Page 84: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/84.jpg)
84
Copyright © 2005 Altera Corporation
Assign SignalProbe SourcesAssign SignalProbe Sources
Use SignalProbe Filter in Node Finder to Locate Sources
Assign Clock & Number of Registers for Pipelining
![Page 85: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/85.jpg)
85
Copyright © 2005 Altera Corporation
SignalProbe SourcesSignalProbe Sources
All Sources Must Be Nodes that Exist after Fitting Use SignalProbe Filter in Node Finder
Valid Examples LE Outputs Memory Block Outputs DSP Block Outputs
Invalid Examples Groups or Busses Carry or Cascade Chains
![Page 86: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/86.jpg)
86
Copyright © 2005 Altera Corporation
Change Source of Pins Add/Delete Source of Pins Enable/Disable SignalProbe Pins
All Require SignalProbe Compilation Only Do Not Need to Perform Full Compilation
Editing SignalProbe AssignmentsEditing SignalProbe Assignments
![Page 87: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/87.jpg)
87
Copyright © 2005 Altera Corporation
SignalProbe OptionsSignalProbe OptionsSignalProbe OptionsSignalProbe Options
Route SignalProbe Signals during Full Compilation Warning : Test Nodes May Be Synthesized
Away Allow Place & Route to Be Modified (If
Necessary)
![Page 88: Copyright © 2005 Altera Corporation Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer.](https://reader034.fdocuments.net/reader034/viewer/2022050908/56649ec55503460f94bcffe2/html5/thumbnails/88.jpg)
88
Copyright © 2005 Altera Corporation
Allows Internal Signals to Be Routed to Unused I/O Quickly & Easily
Ensures Design Placement & Routing Are Unchanged When Adding Test Points
SignalProbe SummarySignalProbe Summary