Copyright © 2003 Texas Instruments. All rights reserved. DSP C5000 Chapter 11 Understanding and...

Copyright © 2003 Texas Instruments. All rights reserved.

DSP C5000DSP C5000

Chapter 11Chapter 11

Understanding and Programming Understanding and Programming the Bootloaderthe Bootloader


ESIEE, Slide 2

BOOT Loader General FeaturesBOOT Loader General Features

Bootloader is used to transfer code from an external source into internal or external program memory following power-up.

Code can be stored in slow non-volatile memory, and be transferred to high-speed memory to be executed.


ESIEE, Slide 3

BOOT Loader BOOT Loader


ESIEE, Slide 4

How Does the DSP Boot?How Does the DSP Boot?

At Reset: Execution begins at location FF80h of the on-chip

ROM if the MP/MC pin is low, external ROM otherwise.

At FF80h a branch instruction jumps to the bootloader program

It sets up the CPU status registers before initiating the bootload.

Interrupts are globally disabled and internal RAMs are mapped into program/data space (OVLY = 1).

All program and data accesses are done with 7 Wait States.

The size of the external memory bank is set to 4K words.


ESIEE, Slide 5

BOOT Mode SelectionBOOT Mode Selection

The bootloader reads the I/O port address 0FFFFh by driving the I/O strobe signal low.

The lower eight bits of the word read from I/O port address 0FFFFh specify the mode of transfer.

The boot routine selection (BRS) word determines the boot mode.


ESIEE, Slide 6

Boot Routine Selection Modes Boot Routine Selection Modes The host port interface (HPI) uses interrupt 2

for bootload (INT2). If INT2 is not latched, the boot routine skips HPI boot mode.

The lower eight bits from the I/O address, 0FFFFh determine the boot mode: Parallel EPROM Boot, BRS word determines the

8- or 16-bit parallel EPROM Serial boot Mode, the six least significant bits and

the configuration of CLKX and FSX pins determine whether to use the 8- or 16-bit bootload serial boot option.

BRS word also determines the 8- or 16-bit parallel I/O mode.


ESIEE, Slide 7

HPI Boot loadingHPI Boot loading HPI is an 8 or 16-bit parallel port that interfaces a

host processor to the C54x The host interrupts the DSP by writing to the HPI

control register (HPIC). The DSP interrupts the host by asserting the host

interrupt (HINT) signal. If HINT=0 then the HPI boot mode is selected. This signal is tied to the external interrupt INT2

input pin if HPI boot mode is selected. If HPI boot mode is selected, the host must download

the code to on-chip HPI RAM before the HPI brings the device out of reset. The code will execute from address 1000h .The host controller must clear HINT by writing to HPIC.


ESIEE, Slide 8

16-Bit/8-Bit Parallel Boot

If the code is stored in EPROMs (8 or 16 bits wide) parallel boot option is used.

The code is transferred from data to program memory.

The 6 MSBs of the source address are specified by the SRC field of the BRS word

If 16-bit parallel mode is selected, data is read in 16-bit words from the source address with auto-incremented .

The destination address and the length of the code are specified by the first two 16-bit words.

After the code is transferred to program memory, the C54 branches to the destination address.


ESIEE, Slide 9

8-bits EPROM Parallel Boot8-bits EPROM Parallel Boot2 Memory locations are read to make the 16-bit word2 Memory locations are read to make the 16-bit word

of program memoryof program memory


ESIEE, Slide 10

EPROM Parallel Boot FlowchartEPROM Parallel Boot Flowchart


ESIEE, Slide 11

I/O Boot

In I/O boot mode, asynchronous transfer of code is done from I/O address 0h to internal/external program memory.

Word can be 16 or 8 bits long. The DSP communicates with external

devices using the BIO and XF handshake protocol


ESIEE, Slide 12

8 bits I/O Bootloader8 bits I/O Bootloader


ESIEE, Slide 13

Serial Boot ModeSerial Boot Mode

Serial boot can be done using McBSP or TDM

Eight modes are available for the serial boot option

Transfer can be done on 8 or 16 bits words


ESIEE, Slide 14

Warm Boot

If the warm boot option is specified: the C54x transfers control to the entry

address The warm boot option can be used after

a warm device reset or if the program has already been transferred to internal or external memory (DMA).

The six MSBs of the entry code are specified by the SRC or ADDR fields of the BRS word.

See Warmboot program exampleProgramme linkProgramme link


ESIEE, Slide 15

Programming the Bootloader Application for the C54x:

Determine vector table and visual linker inputs

Write fir_ISR and application setup code

Use HEX500 to create a boot table, discuss bootload options


ESIEE, Slide 16

[Project] - Physical Memory, Vector Table[Project] - Physical Memory, Vector Table

INBUF: start = 00080h, end = 000DFh

CODE: start = 00100h, end = 004FFh

VECS: start = 00500h, end = 005FFh

OUTBUF: start = 02000h, end = 0205Fh

COEFF: start = 02060h, end = 0225Fh

DARAM2: start = 03000h, end = 03FFFh

FLASH: start = 0E000h, end = 0EFFFh

The following sectionsare booted:- coefficients- code- vectors

Bootloader moves code from Data space to Program Space. Bootloader sets OVLYbit to one.

Using VL, create load/runmaps for coeffs, code andvectors. VL will resolve the run-time symbols

Vectors.ASM;unused: RETE;Ch2 Int @68hDMAC2: B fir_isr

Let’s now review ALL of the code...

Physical Memory

code

vecs

coeffs

Flash(load)

CODE

VECS

COEFFS

RAM(run)

boot


ESIEE, Slide 17

Project.ASMProject.ASM;** .set statements **

.mmregsDMPREC .set 54h ;Channel Priority and Enable Control DMSA .set 55h ;DMA sub-addressDMSDI .set 56h ;DMA write without indexingDMSDN .set 57h ;DMA write with indexingSPSA0 .set 38h ;McBSP0 sub-addressSP0 .set 039h ;Write for McBSP0 sub-addressed regsDRR10 .set 21h ;Data Receive for McBSP0DXR10 .set 23h ;Data Transmit for McBSP0SWCR .set 2bh ;Software Wait State

;** allocate aligned circular buffers for input and output **x .usect "in_bufs",96 bos .usect "STK",128FLAG1 .usect "vars",3 ;signal first time thru input routineFLAG2 .set FLAG1+1 ;signal first time thru output routineCOUNT .set FLAG1+2 ;which buffer is being processed? 1,2,3y .usect "out_bufs",96

;** allocate 16 initialized coeffs of 1/16th each **.sect "coeffs"

a .int 800h,800h,800h,800h.int 800h,800h,800h,800h.int 800h,800h,800h,800h.int 800h,800h,800h,800h


ESIEE, Slide 18

.sect "code";******************* H/W Setup Code *****************

;** PLL **start: STM #0B7FEh,CLKMD ;Setup CLKMD Register

;** SWWSR/SWCR/BSCR **STM #0900h,SWWSR ;SWWSR SetupSTM #0000h,SWCR ;SWCR SetupSTM #0000h,BSCR ;BSCR Setup

;** Reset/Program McBSP0 ** STM #00h,SPSA0 ;SPCR10 STM #4000h,SP0 STM #01h,SPSA0 ;SPCR20 STM #0100h,SP0 STM #02h,SPSA0 ;RCR10 STM #0040h,SP0 STM #03h,SPSA0 ;RCR20 STM #0000h,SP0 STM #04h,SPSA0 ;XCR10 STM #0040h,SP0

STM #05h,SPSA0 ;XCR20STM #0000h,SP0 STM #06h,SPSA0 ;SRGR10STM #0001h,SP0 STM #07h,SPSA0 ;SRGR20STM #30FFh,SP0STM #0Eh,SPSA0 ;PCR0STM #000Ch,SP0


ESIEE, Slide 19

;** McBSP0 Xmt out of reset **STM #01h,SPSA0 ;SPCR20STM #0101h,SP0 ;XRST=1

;** program AIC control registers **CALL XSR_EMPTYSSBX XFSTM #0101h,DXR10 ;CR-1CALL XSR_EMPTYSTM #0210h,DXR10 ;CR-2CALL XSR_EMPTYSTM #0312h,DXR10 ;CR-3CALL XSR_EMPTY STM #0400h,DXR10 ;CR-4

CALL XSR_EMPTY RSBX XF ;** DMA Channel 2 Setup ** STM #0Ah,DMSA STM #DRR10,DMSDI ;DMSRC2 w/auto-inc STM #80h,DMSDI ;DMDST2 STM #1Fh,DMSDI ;DMCTR2 STM #1002h,DMSDI ;DMSFC2 STM #0E045h,DMSDI ;DMMCR2 ;** DMA Channel 3 Setup ** STM #0Fh,DMSA STM #2000h,DMSDI ;DMSRC3 w/auto-inc STM #DXR10,DMSDI ;DMDST3 STM #1Fh,DMSDI ;DMCTR3 STM #2000,DMSDI ;DMSFC3 STM #0141h,DMSDI ;DMMCR3


ESIEE, Slide 20

;** DMA Global Reload Reg Setup **STM #24h,DMSA

STM #DRR10,DMSDI ;DMGSA w/auto-inc STM #80h,DMSDI ;DMGDA STM #1Fh,DMSDI ;DMGCR STM #02h,DMSDI ;DMGFR ;** Set PMST Register to proper value ** ;** **;** IPTR=500h (bootloaded vector table) **;** MP/MC = 0 (should be 0 already) **;** OVLY = 1 (should be 1 already) **;** AVIS = 0 (off) **;** DROM = 0 (off) **;** CLKOFF = 1 (off) **;** SMUL = 0 (off) **;** SST = 1 (on) ** STM #0525h,PMST

;** Check to ensure PLL is locked ** LD #0,DPplloop:

BITF @CLKMD,#1 ;loop until PLLSTATUS=1 BC plloop,NTC ;(PLL Locked)

;** Enable DMA Channels 2 & 3 ** STM #044Ch,DMPREC


ESIEE, Slide 21

;** McBSP0 (rcv) out of reset ** STM #00h,SPSA0 ;SPCR10 STM #4001h,SP0

;** AIC out of reset **CALL XSR_EMPTYSSBX XFSTM #0181h,DXR10 ;CR-1CALL XSR_EMPTYRSBX XF

;** enable DMA Ch2 interrupt, Clear IFR ** STM #0400h,IMR ;DMA-INT CH2

STM #0FFFFh,IFR ;Clr IFR

;** fir_isr setup code **LD #FLAG1,DP ;FLAG1,FLAG2 and COUNT on same DPST #0,FLAG1 ;assure FLAG1 (for in_bufs) is zeroST #0,FLAG2 ;assure FLAG2 (for out_bufs) is zeroST #0,COUNT ;assure COUNT is zeroSTM #31,BRC ;generate 32 resultsSTM #96,BK ;Moe, Larry, Curly input and

;Tom, Dick, Harry output buffersSTM #1,AR0 ;emulate post inc by 1STM #0Fh,DMSA ;0Fh is DMSRC3 (for all DMSRC3 writes)RSBX OVM ;clear overflow modeSSBX FRCT ;set fractional mode SSBX SXM ;set sign extensionRSBX INTM ;enable global interrupts last


ESIEE, Slide 22

;*************************

;** Main Loop **

;*************************

main:

IDLE 1 ;When DMA2 interrupts main, fir_isr runs and

NOP ;execution returns to this code. We then go

NOP ;back into IDLE mode and wait for the

NOP ;next interrupt.

NOP

B main

;*************************

;** XSR Empty Test **

;*************************

XSR_EMPTY:

LD #0,DP

BITF @SP0,2h ;poll XEMPTYn flag

BC XSR_EMPTY,TC

RET


ESIEE, Slide 23

;**************** FIR ISR (DMA Ch2 Int) ****************

fir_isr:LD #FLAG1,DP ;Ignore First DMA InterruptCMPM @FLAG1,#0Fh ; ST #0Fh,@FLAG1 ; BC done,NTC ; ADDM #1,@COUNT ;COUNT holds 1,2,3 for Moe,Larry,CurlyCMPM @COUNT,#1 ;1st pass (Moe)?BC loopinit,TC ;if so, setup ARs and set output SRCCMPM @COUNT,#2 ;2nd pass (Larry)?BC test3,NTC ;NO, go to test3STM #y+32,DMSDN ;DMA3 SRC = out_buf #2B math

test3: CMPM @COUNT,#3 ;3rd pass (Curly)?BC fourth,NTC ;NO, must be fourth, reset counterSTM #y+64,DMSDN ;DMA3 SRC = out_buf #3B math

fourth: ST #1,COUNT ;reset COUNT, reload ARs as 1st pass

loopinit:STM #x,AR3 ;setup ARs for MACSTM #y,AR4 STM #y,DMSDN ;DMA3 SRC = out_buf #1

math: ;...


ESIEE, Slide 24

math: STM #a,AR2 ;always re-init coeff pointer

RPTB tstflg2-1

MPY *AR2+,*AR3+0%,A ;1st product, AR3 circles on 96

RPT #14 ;mult/acc 15 terms

MAC *AR2+,*AR3+0%,A

MAR *+AR3(-15)% ;modify AR3 by -15 circularly

STH A,*AR4+ ;store result

tstflg2:

CMPM @FLAG2,#0Fh ;Write dummy DXR to initiate

ST #0Fh,@FLAG2 ;first DMA3 transfer IF the FIRST

XC 2,NTC ;out_buf is ready

STM #0,DXR10

done: RETE ;return with enable

Now that we’ve written all of the code,how does it get loaded into the system?


ESIEE, Slide 25

C5402 Boot Loader - OptionsC5402 Boot Loader - Options

Each C54x device has specific options and modes. Refer to the boot-loader specification for your chosen device for more details.

C5402 bootloader can copy to extended program space

Boot Mode Description Trigger

No Boot MP/MC=1, begin execution @RS vector None

HPI-8 DSP waits, host xfers code to mem. PC = *07Fh. INT2n low

Parallel Boot Loader xfrs code. Src = 8/16-bit async mem FFFFh in I/O = src

dest = int/ext’l RAM. PC = entry point specified. src = 8AA or 10AAh

then tries Data for src

I/O Boot Loader transfers code via I/O addr 0h. Drives XF high then

Handshake via XF/BIO. waits for BIO response

Serial Boot Loader configures SP and reads 1st word 8AA or 10AAh rcvd?

McBSP0 - 16bit , McBSP1 - 8bit.

Serial Bootloader configures SP in SPI-mode. INT3n low

EEPROM McBSP1 only


ESIEE, Slide 26

[Project] - Parallel Boot[Project] - Parallel Boot

1111000000000000

F

0

0

0

D15 . . . D8 D7 . . . D0

TransparentBuffer

F000hFFFFh

OEn

IS

10AA ;parallel boot0900h ;SWWSR0000h ;SWCR0000h ;BSCR0000h ;XPC entry pointstart ;PC entry pointSize of 1st section0000h ;XPC DEST0100h ;PC DEST - CODECode word 1-N - (CODE)Size of 2nd section0000h ;XPC DEST0500h ;PC DEST - VECSCode word 1-N - (VECS)

When I/O space is accessed,SRCaddr=F000h is returned

Boot table Generated by HEX500

F000h

… (COEFFS)


ESIEE, Slide 27

[Project] - Using HEX500[Project] - Using HEX500

HEX500 firmware.cmd

/* FIRMWARE.CMD */

project.out /* input file */

-e start /* set entry (execution) point */

-i /* select Intel format */

-map project.mxp /* map file for HEX500 */

-o project.hex /* output file */

-memwidth 16 /* DSP accesses mem as 8/16-bit */

-romwidth 16 /* physical mem width, 8/16-bit */

-boot /* make all sections bootable */

-bootorg 0xF000 /* location of boot table */ Must assemble .OUT file using -v548 if using C548/9 and C54x devices Programming formats: 16-bit ASCII hex, Tektronix, Intel MCS-86,

Motorola S (16/24/32-bit addresses), 16-bit TI-Tag

Flash burn programmeFlash burn programme


ESIEE, Slide 28

C55x Boot LoaderC55x Boot Loader

Different boot modes of the C55x: Boot from the Enhanced Host Port Interface

(EHPI) The code to be executed is loaded into on-chip

memory by an external host via the EHPI.

Parallel EMIF boot from 8-, 16- or 32-bit external asynchronous memory The bootloader reads the boot table from EMIF

configured for asynchronous memory. The boot table contains the code or data sections to be loaded, the destination addresses for each of the sections, the execution address.


ESIEE, Slide 29

Different Boot Modes of the C55xDifferent Boot Modes of the C55x

Standard serial boot through McBSP0 Standard serial boot through McBSP0 (8- or 16-bit supported)(8- or 16-bit supported) The bootloader receives the boot table from The bootloader receives the boot table from

the McBSP0 operating in standard mode the McBSP0 operating in standard mode and loads the code according to the and loads the code according to the information specified in the boot table.information specified in the boot table.

SPI EEPROM serial boot through SPI EEPROM serial boot through McBSP0McBSP0 Same as standard serial except that data Same as standard serial except that data

can be can be received from an SPI-format serial received from an SPI-format serial EEPROM, or from another SPI-compliant EEPROM, or from another SPI-compliant serial port operating as a SPI slave.serial port operating as a SPI slave.


ESIEE, Slide 30

More Boot Loader FeaturesMore Boot Loader Features Boot mode selection is I/O pin-controlled Boot mode selection is I/O pin-controlled First address of execution after the boot load is First address of execution after the boot load is

complete is programmable and is stored in the boot complete is programmable and is stored in the boot table. table.

Port-addressed register configuration during bootPort-addressed register configuration during boot Some of the port-addressed registers used to control Some of the port-addressed registers used to control

peripherals can be modified during the bootload, peripherals can be modified during the bootload, providing the ability to modify the clock generator, providing the ability to modify the clock generator, reconfigure the EMIF strobe timings or preset reconfigure the EMIF strobe timings or preset peripheral register values.peripheral register values.

Programmable delays of up to 65535 CPU clock Programmable delays of up to 65535 CPU clock cycles can be added during the register configuration cycles can be added during the register configuration process to ensure that new configurations are process to ensure that new configurations are complete before the boot process continues. complete before the boot process continues.


ESIEE, Slide 31

On Chip standard ROM DescriptionOn Chip standard ROM Description On-chip ROM contains several factory-On-chip ROM contains several factory-

programmed sections including:programmed sections including:


ESIEE, Slide 32

Bootloader Resource InitialisationBootloader Resource Initialisation Data Stack register (SP) is initialised to address Data Stack register (SP) is initialised to address

000090h, and the System Stack register (SSP) to 000090h, and the System Stack register (SSP) to address 000080h.address 000080h.

The stack configuration is set to 32-bit with slow The stack configuration is set to 32-bit with slow return.return.

The INTM bit of Status Register 1 (ST1_55) is set to The INTM bit of Status Register 1 (ST1_55) is set to 1, to disable interrupts.1, to disable interrupts.

Two words are reserved for temporary storage of the Two words are reserved for temporary storage of the entry-point address at 000060h and 000061h.entry-point address at 000060h and 000061h.

SXMD bit of ST1-55 is cleared , to disable sign SXMD bit of ST1-55 is cleared , to disable sign extension mode. After the bootloader copies all of the extension mode. After the bootloader copies all of the sections, SXMD is set back to 1 before execution is sections, SXMD is set back to 1 before execution is transferred to the application.transferred to the application.

The 54CM bit of ST1-55 is set to 1, to enable C54x The 54CM bit of ST1-55 is set to 1, to enable C54x compatibility mode during and after the bootload.compatibility mode during and after the bootload.


ESIEE, Slide 33

Boot Loader Mode SelectionBoot Loader Mode Selection

55105510

ROMROM

BootBootLoaderLoader

BOOTM[3:0]BOOTM[3:0]

BOOTMBOOTM pins (sampled at reset, stable for 30 pins (sampled at reset, stable for 30 cycles) determine type of boot:cycles) determine type of boot:

Boot up to Boot up to 64Kx1664Kx16 of the C5510’s of the C5510’s internal memoryinternal memory

Boot performed by ROM-coded Boot performed by ROM-coded boot routines during resetboot routines during reset

No boot (begin No boot (begin executionexecutionat reset vector)at reset vector)

EHPIEHPI ExternalExternal SerialSerial


ESIEE, Slide 34

BOOT Mode SelectionBOOT Mode Selection

0000 0000 No bootNo boot

0001 0001 Serial EEPROM (SPI) boot from McBSP0 Serial EEPROM (SPI) boot from McBSP0 supporting 24-bit addresssupporting 24-bit address

10001000 No boot No boot

1001 1001 Serial EEPROM (SPI) boot from McBSP0 Serial EEPROM (SPI) boot from McBSP0 supporting 16-bit address supporting 16-bit address

10101010 Parallel EMIF boot from 8-bit external Parallel EMIF boot from 8-bit external asynchronous asynchronous memory memory

10111011 Parallel EMIF boot from 16-bit external Parallel EMIF boot from 16-bit external asynchronous asynchronous memory memory

1100 1100 Parallel EMIF boot from 32-bit external Parallel EMIF boot from 32-bit external asynchronous asynchronous memory memory

1101 1101 EHPI EHPI

1110 1110 Standard serial boot from McBSP0 (16-bit)Standard serial boot from McBSP0 (16-bit)

1111 1111 Standard serial boot from McBSP0 (8-bitStandard serial boot from McBSP0 (8-bit) )

BOOTMBOOTM BOOT ModeBOOT Mode


ESIEE, Slide 35

Boot Load OptionsBoot Load Options

size: #words, DEST: word addr, 0000h terminates bootsize: #words, DEST: word addr, 0000h terminates boot

uPuP SARAMSARAM80008000

Host uP boots SARAM duringHost uP boots SARAM duringDSP resetDSP reset

After boot: execution begins atAfter boot: execution begins ataddress 8000h (word)address 8000h (word)

EHPIEHPI

16- or 32-bit async, CE116- or 32-bit async, CE1 CE1: 20_0000h (word)CE1: 20_0000h (word) Multiple sections can be bootedMultiple sections can be booted after boot: execution begins atafter boot: execution begins at

DESTDEST of 1st section of 1st section

InternalInternal

CE1CE1sizesize

DESTDEST

codecodeDESTDEST

codecodeExternalExternal

......

0000h0000h

8- or 16-bit transfers8- or 16-bit transfers Bootloader configures: external Bootloader configures: external

CLK and FS, frmlen=1CLK and FS, frmlen=1 Multiple sections can be bootedMultiple sections can be booted After boot: execution begins atAfter boot: execution begins at

DESTDEST of 1st section of 1st section

McBSP0McBSP0

InternalInternalDESTDEST

codecodeSerialSerialsizesize

DESTDEST

codecode

......

0000h0000h

Copyright © 2003 Texas Instruments. All rights reserved. DSP C5000 Chapter 11 Understanding and...

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Transcript of Copyright © 2003 Texas Instruments. All rights reserved. DSP C5000 Chapter 11 Understanding and...