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ECE 372 1st Midterm

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ECE 372 Midterm ExamFall 2004

In this exam only pencil/pen are allowed.Please write your name on the front page. If you unstaple the papers write your name on

the loose papers also.Please do not use additional paper. If you write on the back please indicate where thenotes belong to and also indicate on the front that there is additional information on thebackside.The approximate point value is shown in brackets [] following the problem number.You have 1 hour to complete the exam. Please note that some questions give significantlymore points and are more complex to solve.

Organization

0a) [2] What are the first or last names of our 3 TAs?

0b) [2] Can you name 2 people form technical support services (stockroom)?

Introduction

1a) [2] What is the difference between a micro controller and a micro processor?

1b) [2] What is the difference between a common computer system and an embeddedcomputer system?


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HC11 CPU / Microcontroller

2 a) [3] List all functional components of our microcontroller (built into microcontroller)2 b) [5] explain what they are used for2 c) [2] give suggestion what can be attached to the unit or what other unit is connected toit (do not list more than two)

Functional Unit Purpose Connected to


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ECE 372 1st Midterm

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3 a) [2] Our microcontroller has a register based design. List all registers by completingthe list below (do not list configuration registers = $10xx)3 b) [3] List the purpose of the register (do not list more than 2 purposes)

Register Purpose

- Condition Code Register (general answer, more details in next question)

- Program Counter


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3 c) [5] The Condition Code Register is based on 8 bits. All bits indicate certainconditions of the microcontroller. List the function of up to 5 of these bits.Bit FunctionZERO

3 d) [2] The system you constructed in the laboratory indicates that the program counterpoints to $4000. Is there a problem with that?


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UofA system hardware

4 a) [3] Our microcontroller can be operated in expanded mode but also in bootstrapmode and single chip mode. What is the difference between them?

4 b) The normal operation mode of our micro controller involves a multiplexed bus. A

bus is composed of data, address and control lines.- [2] What is a multiplexed bus?

- [4] What control lines do we have and what is their purpose?

- [1] How many data lines and how many address lines do we have?

- [1] How many physical pins are associated with the address and data lines?


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4 c) [4] In the laboratory you built a reset circuit. Why do we not simply use a pushbuttonto ground reset if we want to restart the microcontroller (or what is the purpose of those 2integrated circuits you wired to the reset pin)?


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ECE 372 1st Midterm

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Basic Instruction Cycle

You want to execute ABA.5a) [1] What does this instruction do?

5b) [4] Which part of this process would you consider to be Fetch, Decode and Execute?Think of what happens inside the microcontroller and associate the steps to fetch, decodeand execute.

Fetch

Decode

Execute?


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ECE 372 1st Midterm

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Data Formats

6) You read a faulty EEPROM and found that sometimes you read a binary value of0011 0011and sometimes a value of1001 0011

at the same memory location. What does this data represent in

6 a) [1] Hexadecimal

6 b) [3] HC11 instruction. You need to stateMNEMONIC instruction nameAddressing modeFunction of the instruction (speculate if you do not know)

6 c) [2] ASCII encoded value (give character as result if possible)

6 d) [1] Binary Coded Decimal value (give result in decimal)

6 e) [3] PC relative offset (give result in signed decimal)


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ECE 372 1st Midterm

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Assembly Programming

7 a) [10] This is a very short program. Please fill in the gaps. Shaded area=nothing canbe filled in.

Label Instruction Operand EEPROM

Address

Contents

MAIN LDX #$ $8000 $CE$8001 $00$8002 $00

LOOP INX $8003 $#$ $8004 $8C

$8005 $00

$8006 $03LOOP $8007 $25

$8008 $ *$8009

ORG $FFFE $FFFE $80DC.W MAIN $FFFFEND

*) counts at least one point.

7 b) [2] What is happening in register X in this program? If the program counter points to$8009 what is the contents of register X?


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ECE 372 1st Midterm

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7c) [10] For each E clock cycle (actually each half cycle) show what values will be on thepins (AD0..7,A8..15) when the previous program is executed. Assume that the resetswitch was pressed and show what happens from that point on forward. Fill in commentswhere appropriate. Only go through the loop one time.

$FFFE $FF80 $FFFF $FF $8000 $80CE $8001 $80..

ResetStart

LDX


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ECE 372 1st Midterm

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Appendix

Page0ASCII tableAssembly Commands for X register


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M68HC11ERG/AD

58 M68HC11E Series Programming Reference Guide MOTOROLA

Hexadecimal to ASCII Conversion

Table 2. Hexadecimal to ASCII Conversion

Hex ASCII Hex ASCII Hex ASCII Hex ASCII

$00 NUL $20 SP space $40 @ $60 `grave$01 SOH $21 ! $41 A $61 a

$02 STX $22 quote $42 B $62 b$03 ETX $23 # $43 C $63 c

$04 EOT $24 $ $44 D $64 d

$05 ENQ $25 % $45 E $65 e

$06 ACK $26 & $46 F $66 f

$07 BEL beep $27 apost. $47 G $67 g

$08BS back

sp$28 ( $48 H $68 h

$09 HT tab $29 ) $49 I $69 i

$0ALF

linefeed$2A * $4A J $6A j

$0B VT $2B + $4B K $6B k

$0C FF $2C , comma $4C L $6C l

$0D CR return $2D -dash $4D M $6D m$0E SO $2E .period $4E N $6E n$0F SI $2F / $4F O $6F o

$10 DLE $30 0 $50 P $70 p

$11 DC1 $31 1 $51 Q $71 q

$12 DC2 $32 2 $52 R $72 r

$13 DC3 $33 3 $53 S $73 s

$14 DC4 $34 4 $54 T $74 t

$15 NAK $35 5 $55 U $75 u

$16 SYN $36 6 $56 V $76 v

$17 ETB $37 7 $57 W $77 w

$18 CAN $38 8 $58 X $78 x

$19 EM $39 9 $59 Y $79 y

$1A SUB $3A : $5A Z $7A z

$1B ESCAPE $3B ; $5B [ $7B {

$1C FS $3C < $5C \ $7C |

$1D GS $3D = $5D ] $7D }

$1E RS $3E > $5E ^ $7E ~

$1F US $3F ? $5F _ under $7FDEL

delete

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M68HC11ERG/AD

8 M68HC11E Series Programming Reference Guide MOTOROLA

OpcodeMaps

Page1

ACCA

ACCB

INH

INH

REL

INH

ACCA

ACCB

IND,X

EXT

IMM

DIR

IND

,X

EXT

IMM

DIR

IND,X

EXT

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0000

0

TEST

SBA

BRA

TSX

N

EG

SUB

0

0001

1

NOP

CBA

BRN

INS

CMP

1

0010

2

IDIV

BRSET

BHI

PULA

SBC

2

0011

3

EDIV

BRCLR

BLS

PULB

C

OM

SUBD

ADDD

3

0100

4

LSRD

B

SET

BCC

DES

L

SR

AND

4

0101

5

ASLD

B

CLR

BCS

TXS

BIT

5

0110

6

TAP

TAB

BNE

PSHA

R

OR

LDA

6

0111

7

TPA

TBA

BEQ

PSHB

A

SR

ST

A

STA

7

1000

8

INX

PAGE2

BVC

PULX

ASL

EOR

8

1001

9

DEX

DAA

BVS

RTS

R

OL

ADC

9

1010

A

CLV

PAGE3

BPL

ABX

D

EC

ORA

A

1011

B

SEV

ABA

BMI

RTI

ADD

B

1100

C

CLC

B

SET

BGE

PSHX

INC

CPX

LDD

C

1101

D

SEC

B

CLR

BLT

MUL

TST

BSR

JS

R

PAGE4

STD

D

1110

E

CLI

BRSET

BGT

WAI

JMP

LDS

LDX

E

1111

F

SEI

BRCLR

BLE

SWI

C

LR

XGDX

ST

S

STOP

STX

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

MSB

LSB

DIR

IND,X

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Instruction Set Details

M68HC11 Instruction Set

M68HC11 Rev. 6 Reference Manual

MOTOROLA Instruction Set Details 493

ABX Add Accumulator B to Index Register X ABXOperation: IX (IX) + (ACCB)

Description: Adds the 8-bit unsigned contents of accumulator B to the contents ofindex register X (IX) considering the possible carry out of the low-order

byte of the index register X; places the result in index register X (IX).

Accumulator B is not changed. There is no equivalent instruction to add

accumulator A to an index register.

Condition Codes

and Boolean

Formulae:

None affected

Source Form: ABX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

S X H I N Z V C

CycleABX (INH)

Addr Data R/W

1 OP 3A 1

2 OP + 1 1

3 FFFF 1

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Reference Manual M68HC11 Rev. 6

512 Instruction Set Details MOTOROLA


BLO Branch if Lower (Same as BCS) BLOOperation: PC (PC) + $0002 + Rel if (C) = 1

i.e., if (ACCX) < (M) (unsigned binary numbers)

Description: If the BLO instruction is executed immediately after execution of anyof the instructions, CBA, CMP(A, B, or D), CP(X or Y), SBA, SUB(A, B,or D), the branch will occur if and only if the unsigned binary numberrepresented by ACCX was less than the unsigned binary numberrepresented by M. Generally not useful after INC/DEC, LD/ST,TST/CLR/COM because these instructions do not affect the C bit in theCCR.

See BRA instruction for further details of the execution of the branch.

Condition Codes

and Boolean

Formulae:None affected

Source Form: BLO (rel)


The following table is a summary of all branch instructions.

S X H I N Z V C

CycleBLO (REL)

Addr Data R/W

1 OP 25 1

2 OP + 1 rr 1

3 FFFF

1

Test Boolean Mnemonic Opcode Complementary Branch Comment

r > m Z + (N V) = 0 BGT 2E r m BLE 2F Signed

r m N V = 0 BGE 2C r < m BLT 2D Signed

r = m Z = 1 BEQ 27 r m BNE 26 Signed

r m Z + (N V) = 1 BLE 2F r > m BGT 2E Signed

r < m N V = 1 BLT 2D r m BGE 2C Signed

r > m C + Z = 0 BHI 22 r m BLS 23 Unsigned

r m C = 0 BHS/BCC 24 r < m BLO/BCS 25 Unsigned

r = m Z = 1 BEQ 27 r m BNE 26 Unsigned

r m C + Z = 1 BLS 23 r > m BHI 22 Unsigned

r < m C = 1 BLO/BCS 25 r m BHS/BCC 24 Unsigned

Carry C = 1 BCS 25 No Carry BCC 24 Simple

Negative N = 1 BMI 2B Plus BPL 2A Simple

Overflow V = 1 BVS 29 No Overflow BVC 28 Simple

r = 0 Z = 1 BEQ 27 r 0 BNE 26 Simple

Always BRA 20 Never BRN 21 Unconditional

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BLS Branch if Lower or Same BLSOperation: PC (PC) + $0002 + Rel if (C) + (Z) = 1

i.e., if (ACCX) (M) (unsigned binary numbers)

Description: If the BLS instruction is executed immediately after execution of any

of the instructions, CBA, CMP(A, B, or D), CP(X or Y), SBA, SUB(A, B,

or D), the branch will occur if and only if the unsigned binary number

represented by ACCX was less than or equal to the unsigned binary

number represented by M. Generally not useful after INC/DEC, LD/ST,

TST/CLR/COM because these instructions do not affect the C bit in the

CCR.

See BRA instruction for further details of the execution of the branch.

Condition Codesand Boolean

Formulae:None affected

Source Form: BLS (rel)


The following table is a summary of all branch instructions.

S X H I N Z V C

CycleBLS (REL)

Addr Data R/W

1 OP 23 1

2 OP + 1 rr 13 FFFF 1

Test Boolean Mnemonic Opcode Complementary Branch Comment

r > m Z + (N V) = 0 BGT 2E r m BLE 2F Signed

r m N V = 0 BGE 2C r < m BLT 2D Signed

r = m Z = 1 BEQ 27 r m BNE 26 Signed

r m Z + (N V) = 1 BLE 2F r > m BGT 2E Signed

r < m N V = 1 BLT 2D r m BGE 2C Signed

r > m C + Z = 0 BHI 22 r m BLS 23 Unsigned

r m C = 0 BHS/BCC 24 r < m BLO/BCS 25 Unsigned

r = m Z = 1 BEQ 27 r

m BNE 26 Unsignedr m C + Z = 1 BLS 23 r > m BHI 22 Unsigned

r < m C = 1 BLO/BCS 25 r m BHS/BCC 24 Unsigned

Carry C = 1 BCS 25 No Carry BCC 24 Simple

Negative N = 1 BMI 2B Plus BPL 2A Simple

Overflow V = 1 BVS 29 No Overflow BVC 28 Simple

r = 0 Z = 1 BEQ 27 r 0 BNE 26 Simple

Always BRA 20 Never BRN 21 Unconditional

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CPX Compare Index Register X CPXOperation: (IX) (M : M + 1)

Description: Compares the contents of index register X with a 16-bit value at theaddress specified and sets the condition codes accordingly. The

compare is accomplished internally by doing a 16-bit subtract of

(M : M + 1) from index register X without modifying either index register

X or (M : M + 1).

Condition Codes

and Boolean

Formulae:

N R15Set if MSB of result is set; cleared otherwise.

Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0Set if result is $0000; cleared otherwise.

V IX15 M15 R15 + IX15 M15 R15Set if a twos complement overflow resulted from the operation;cleared otherwise.

C IX15 M15 + M15 R15 + R15 IX15Set if the absolute value of the contents of memory is larger than theabsolute value of the index register; cleared otherwise.

Source Form: CPX (opr)


S X H I N Z V C

CycleCPX (IMM) CPX (DIR) CPX (EXT) CPX (IND,X) CPX (IND,Y)

Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W

1 OP 8C 1 OP 9C 1 OP BC 1 OP AC 1 OP CD 1

2 OP + 1 jj 1 OP + 1 dd 1 OP + 1 hh 1 OP + 1 ff 1 OP + 1 AC 1

3 OP + 2 kk 1 00dd (00dd) 1 OP + 2 ll 1 FFFF 1 OP + 2 ff 1

4 FFFF 1 00dd + 1 (00dd + 1) 1 hhll (hhll) 1 X + ff (X + ff) 1 FFFF 1

5 FFFF 1 hhll + 1 (hhll + 1) 1 X + ff + 1 (X + ff + 1) 1 Y + ff (Y + ff) 1

6 FFFF

1 FFFF

1 Y + ff + 1 (Y + ff + 1) 1

7 FFFF 1

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DEX Decrement Index Register X DEXOperation: IX (IX) $0001

Description: Subtract one from index register X

Only the Z bit is set or cleared according to the result of this operation.

Condition Codes

and Boolean

Formulae:


Source Form: DEX


S X H I N Z V C

CycleDEX (INH)

Addr Data R/W

1 OP 09 1

2 OP + 1 1

3 FFFF 1

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INX Increment Index Register X INXOperation: IX (IX) + $0001

Description: Adds one to index register X

Only the Z bit is set or cleared according to the result of this operation.

Condition Codes

and Boolean

Formulae:


Source Form: INX


S X H I N Z V C

CycleINX (INH)

Addr Data R/W

1 OP 08 1

2 OP + 1 1

3 FFFF 1

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LDX Load Index Register X LDXOperation: IXH (M), IXL (M + 1)

Description: Loads the most significant byte of index register X from the byte ofmemory at the address specified by the program, and loads the least

significant byte of index register X from the next byte of memory at one

plus the address specified by the program.

Condition Codes

and Boolean

Formulae:

N R15Set if MSB of result is set; cleared otherwise.


V 0Cleared

Source Form: LDX (opr)


S X H I N Z V C

0

CycleLDX (IMM) LDX (DIR) LDX (EXT) LDX (IND,X) LDX (IND,Y)

Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W1 OP CE 1 OP DE 1 OP FE 1 OP EE 1 OP CD 1

2 OP + 1 jj 1 OP + 1 dd 1 OP + 1 hh 1 OP + 1 ff 1 OP + 1 EE 1

3 OP + 2 kk 1 00dd (00dd) 1 OP + 2 ll 1 FFFF 1 OP + 2 ff 1

4 00dd + 1 (00dd + 1) 1 hhll (hhll) 1 X + ff (X + ff) 1 FFFF 1

5 hhll + 1 (hhll + 1) 1 X + ff + 1 (X + ff + 1) 1 Y + ff (Y + ff) 1

6 Y + ff + 1 (Y + ff + 1) 1

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PULX Pull Index Register X from Stack PULXOperation: SP (SP) + $0001; (IXH)

SP (SP) + $0001; (IXL)

Description: Index register X is pulled from the stack (high-order byte first) beginning

at the address contained in the stack pointer plus one. The stack pointer

is incremented by two in total.

Push instructions are commonly used to save the contents of one or

more CPU registers at the start of a subroutine. Just before returning

from the subroutine, corresponding pull instructions are used to restore

the saved CPU registers so the subroutine will appear not to have

affected these registers.

Condition Codes

and Boolean

Formulae:

None affected

Source Form: PULX


S X H I N Z V C

CyclePULX (INH)

Addr Data R/W1 OP 38 1

2 OP + 1 1

3 SP 1

4 SP + 1 get IXH 1

5 SP + 2 get IXL 1

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PSHX Push Index Register X onto Stack PSHXOperation: (IXL), SP (SP) $0001

(IXH), SP (SP) $0001

Description: The contents of index register X are pushed onto the stack (low-order

byte first) at the address contained in the stack pointer. The stack pointer

is then decremented by two.

Push instructions are commonly used to save the contents of one or

more CPU registers at the start of a subroutine. Just before returning

from the subroutine, corresponding pull instructions are used to restore

the saved CPU registers so the subroutine will appear not to have

affected these registers.

Condition Codes

and Boolean

Formulae:

None affected

Source Form: PSHX


S X H I N Z V C

CyclePSHX (INH)

Addr Data R/W1 OP 3C 1

2 OP + 1 1

3 SP (IXL) 0

4 SP 1 (IXH) 0

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STX Store Index Register X STXOperation: M (IXH), M + 1 (IXL)

Description: Stores the most significant byte of index register X in memory at theaddress specified by the program, and stores the least significant byte of

index register X at the next location in memory, at one plus the address

specified by the program.

Condition Codes

and Boolean

Formulae:

N IX15Set if MSB of result is set; cleared otherwise.

Z IX15 IX14 IX13 IX12 IX11 IX10 IX9 IX8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0Set if result is $0000; cleared otherwise.

V 0Cleared

Source Form: STX (opr)


S X H I N Z V C

0

CycleSTX (DIR) STX (EXT) STX (IND,X) STX (IND,Y)

Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W1 OP DF 1 OP FF 1 OP EF 1 OP CD 1

2 OP + 1 dd 1 OP + 1 hh 1 OP + 1 ff 1 OP + 1 EF 1

3 00dd (IXH) 0 OP + 2 ll 1 FFFF 1 OP + 2 ff 1

4 00dd + 1 (IXL) 0 hhll (IXH) 0 X + ff (IXH) 0 FFFF 1

5 hhll + 1 (IXL) 0 X + ff + 1 (IXL) 0 Y + ff (IXH) 0

6 Y + ff + 1 (IXL) 0

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