User Can Define Its Own Groups to Block Access to Certain Variables
CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 :...
Transcript of CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 :...
![Page 1: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/1.jpg)
PG26 RX, ORX TALISE APG27 RX, ORX TALISE BPG28 TX TALISE APG29 TX TALISE BPG30 HMC7044 JESD CLOCK GENPG31 DECOUPLING HMC7044
PG34 PS_0V85,1V8 REGULATORS
PG38 PL_DDR4, PS_DDR4 REGULATORS
M. BANCISO20FEB20AS PER ECR-091616C
B C. GOGA28MAY19AS PER ECR-085795
C. GOGA05OCT18INITIAL RELEASEA
PG2 SOM INTERFACE
PG4 ETHERNET PHY, USB PHY
PG6 BANK 500, 501, 502, 503
PG19 ZYNQ POWERPG20 ZYNQ POWERPG21 ZYNQ POWER
PG18 ZYNQ POWER
PG15 HP BANK 68 - 71PG16 HD BANK 88,89
PG22 TALISE APG23 TALISE B
PG14 HP BANK 64 - 67
PG9 PS DDR4
PG11 PL DDR4 PG12 PL DDR4
PG17 GTH TRANSCEIVERS
PG24 DECOUPLING TALISE A
05OCT18
05OCT18
05OCT18
05OCT18
05OCT18
PG32 POWER MONITRING
PG10 PS DDR4 TERMINATIONS
PG13 PL DDR4 TERMINATIONS
PG25 DECOUPLING TALISE B
PG33 PL_0V85 REGULATOR
PG37 3V3, 2V5 REGULATORSPG36 MGTAVCC, MGTAVTT REGULATORSPG35 MGTRAVCC, MGTRAVTT REGULATORS
PG39 RF SWITCHHING REGULATORPG40 RF SWITCHHING REGULATORPG41 RF LDOS
PG8 PS DDR4PG7 GTR REFERENCE CLOCK, GTR BANK
PG5 SD CARD, QSPI FLASH
PG3 SOM INTERFACE
1 41
<User Define><User Define><User Define>
: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
no_template
CCodeID1:1
02_048949TBD
N/A
R. MACDONALD
N/A
M. JOSE
A. CAUILAN
C. GOGA
N/A
K. JABATAN
N/A
N/A
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
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PROVIDED BY CARRIER
PROVIDED BY CARRIERPROVIDED BY CARRIER
SE ONLY
PROVIDED BY CARRIER
SE ONLY
SE ONLY
SE ONLYSE ONLY
SE ONLYSE ONLY
SOM SIGNAL INTERFACE
2 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ASP-134486-01
ASP-134486-01ASP-134486-01 ASP-134486-01 ASP-134486-01ASP-134486-01ASP-134486-01
ASP-134486-01ASP-134486-01ASP-134486-01
P2P2
P2 P2
P2 P2P2P2
P2 P2
SCL_ADM1266_3V3PS_SRST_BPS_PROG_B
SDA_ADM1266_3V3
IO_L6P_HDGC_89
IO_L14N_T2L_N3_GC_67IO_L14P_T2L_N2_GC_67
IO_L9N_T1L_N5_AD12N_67
IO_L10P_T1U_N6_QBC_AD4P_65
IO_L12P_T1U_N10_GC_67
IO_L22N_T3U_N7_DBC_AD0N_65IO_L22P_T3U_N6_DBC_AD0P_65
IO_L8P_T1L_N2_AD5P_68
IO_L11P_T1U_N8_GC_68IO_L11N_T1U_N9_GC_68
IO_L7N_T1L_N1_QBC_AD13N_65
IO_L1N_T0L_N1_DBC_65
IO_L2N_T0L_N3_67IO_L13P_T2L_N0_GC_QBC_65
IO_T3U_N12_67
IO_L17N_T2U_N9_AD10N_65VCCO_67VREF_67VREF_65
IO_L7N_T1L_N1_QBC_AD13N_68IO_L7P_T1L_N0_QBC_AD13P_68
IO_L12P_T1U_N10_GC_68IO_L12N_T1U_N11_GC_68
IO_L10P_T1U_N6_QBC_AD4P_68IO_L10N_T1U_N7_QBC_AD4N_68
IO_T0U_N12_VRP_68
IO_L22N_T3U_N7_DBC_AD0N_68IO_L22P_T3U_N6_DBC_AD0P_68
IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65IO_L23P_T3U_N8_I2C_SCLK_65
IO_L3N_T0L_N5_AD15N_67IO_L3P_T0L_N4_AD15P_67
IO_L13N_T2L_N1_GC_QBC_65
IO_L8P_T1L_N2_AD5P_65
IO_L5N_T0U_N9_AD14N_68IO_L5P_T0U_N8_AD14P_68
IO_L15N_T2L_N5_AD11N_67IO_L15P_T2L_N4_AD11P_67
IO_L5P_T0U_N8_AD14P_65IO_L5N_T0U_N9_AD14N_65
IO_L17P_T2U_N8_AD10P_65
IO_L5P_T0U_N8_AD14P_67
IO_L2P_T0L_N2_67
IO_L5N_T0U_N9_AD14N_67
IO_L10P_T1U_N6_QBC_AD4P_67IO_L10N_T1U_N7_QBC_AD4N_67
IO_L16P_T2U_N6_QBC_AD3P_65
IO_L18P_T2U_N10_AD2P_67
IO_L23N_T3U_N9_67IO_L23P_T3U_N8_67
IO_L17P_T2U_N8_AD10P_67IO_L17N_T2U_N9_AD10N_67
IO_L16N_T2U_N7_QBC_AD3N_65
IO_L12N_T1U_N11_GC_67
IO_L24P_T3U_N10_68
IO_L4P_T0U_N6_DBC_AD7P_68
IO_L14N_T2L_N3_GC_68IO_L21P_T3L_N4_AD8P_68
IO_L17N_T2U_N9_AD10N_68IO_L17P_T2U_N8_AD10P_68
IO_L9N_T1L_N5_AD12N_65
IO_L7P_T1L_N0_QBC_AD13P_65
IO_T2U_N12_65
IO_L18N_T2U_N11_AD2N_67
IO_L8P_T1L_N2_AD5P_67
IO_L14P_T2L_N2_GC_65IO_L14N_T2L_N3_GC_65
IO_L12P_T1U_N10_GC_65
IO_L10N_T1U_N7_QBC_AD4N_65
IO_T3U_N12_PERSTN0_65
IO_L3P_T0L_N4_AD15P_65IO_L3N_T0L_N5_AD15N_65
IO_L6P_T0U_N10_AD6P_67
IO_L24N_T3U_N11_67
IO_L19N_T3L_N1_DBC_AD9N_67
IO_L13P_T2L_N0_GC_QBC_67
IO_L9P_T1L_N4_AD12P_67
S_IN_P
PS_GTR_RX3_505_P
PS_GTR_TX0_505_P
PS_GTR_RX1_505_NIO_L3N_AD13N_89
ETH_MD1_N
IO_L5N_HDGC_89
SDIO_CARRIER_CLK
JTAG_TDIJTAG_TCKSDIO_SELSDIO_CARRIER_CD
PS_MIO22_500_SPI1_SCLK_OUTPS_MIO21_500_SPI1_N_SS_OUT0
PS_ERROR_STATUS
VCCO_89
PS_MIO17_500_UART1_RXD
IO_L3P_AD13P_89
IO_L2N_AD14N_89IO_L1P_AD15P_89IO_L1N_AD15N_89
SDIO_CARRIER_DAT0
PS_MIO23_500_SPI1_MOSI
PS_MIO28_501_DPAUX_HOT_PLUG_DET
JTAG_TDO
PS_MIO34_501_UART0_RXDPS_MIO35_501_UART0_TXD
IO_L19P_T3L_N0_DBC_AD9P_65IO_L19N_T3L_N1_DBC_AD9N_65
IO_L24P_T3U_N10_67
IO_L15N_T2L_N5_AD11N_68IO_L15P_T2L_N4_AD11P_68
IO_L13P_T2L_N0_GC_QBC_68IO_L13N_T2L_N1_GC_QBC_68
IO_L9P_T1L_N4_AD12P_68
IO_L19P_T3L_N0_DBC_AD9P_67
IO_L8N_T1L_N3_AD5N_67
IO_L24N_T3U_N11_65
IO_L1N_T0L_N1_DBC_67
IO_L2P_T0L_N2_65
IO_L1P_T0L_N0_DBC_67
IO_L9P_T1L_N4_AD12P_65
IO_L12N_T1U_N11_GC_65
VCCO_68
IO_L2P_AD14P_89
IO_L4N_AD12N_89IO_L4P_AD12P_89
IO_L5P_HDGC_89IO_L6N_HDGC_89
IO_L16P_T2U_N6_QBC_AD3P_68IO_L16N_T2U_N7_QBC_AD3N_68
VREF_68
PS_MIO77_502_ETH_MDIOPS_MIO18_500_SPI1_MISO
PG_SOMPG_ALL
VIN
IO_L20N_T3L_N3_AD1N_68
IO_L6P_T0U_N10_AD6P_68
IO_L21N_T3L_N5_AD8N_68
IO_L1N_T0L_N1_DBC_68
IO_L11P_T1U_N8_GC_65IO_L11N_T1U_N9_GC_65
IO_L1P_T0L_N0_DBC_65
IO_L4N_T0U_N7_DBC_AD7N_67
IO_L20N_T3L_N3_AD1N_65
IO_L13N_T2L_N1_GC_QBC_67
SDIO_CARRIER_DAT1
IO_L9N_T1L_N5_AD12N_68
1V8
1V8
3V3
SDIO_CARRIER_DAT3
IO_L20P_T3L_N2_AD1P_68
IO_L3N_T0L_N5_AD15N_68
IO_L6N_T0U_N11_AD6N_68
PS_MIO76_502_ETH_MDC
PS_MIO19_500_SPI1_N_SS_OUT2
PS_MIO37_501
PS_MIO33_501_I2C1_SDA
PS_MIO30_501_DPAUX_DATA_INPS_MIO29_501_DPAUX_DATA_OE
PS_MIO38_501
SDIO_CARRIER_CMD
SDIO_CARRIER_DAT2
PS_MIO27_501_DPAUX_DATA_OUT
PS_MIO36_501
PS_MIO31_501
PS_MIO26_501_ID
PS_MIO16_500_UART1_TXDPS_MIO15_500_I2C0_SDA
PS_MIO20_500_SPI1_N_SS_OUT1
PS_MIO32_501_I2C1_SCL
JTAG_TMS
PS_MIO14_500_I2C0_SCL
IO_L21N_T3L_N5_AD8N_65
IO_L7P_T1L_N0_QBC_AD13P_67IO_L7N_T1L_N1_QBC_AD13N_67
IO_L6N_T0U_N11_AD6N_67
IO_L8N_T1L_N3_AD5N_65
IO_L4P_T0U_N6_DBC_AD7P_65IO_L4N_T0U_N7_DBC_AD7N_65
IO_T2U_N12_68IO_T3U_N12_68
IO_L22N_T3U_N7_DBC_AD0N_67IO_L22P_T3U_N6_DBC_AD0P_67
IO_L4N_T0U_N7_DBC_AD7N_68
IO_L11P_T1U_N8_GC_67
IO_L15N_T2L_N5_AD11N_65IO_L15P_T2L_N4_AD11P_65
IO_L20P_T3L_N2_AD1P_67IO_L20N_T3L_N3_AD1N_67
IO_L11N_T1U_N9_GC_67
IO_L19P_T3L_N0_DBC_AD9P_68
IO_L23P_T3U_N8_68IO_L23N_T3U_N9_68
IO_L19N_T3L_N1_DBC_AD9N_68
IO_L6P_T0U_N10_AD6P_65
IO_L21P_T3L_N4_AD8P_67
IO_T2U_N12_67
IO_L21N_T3L_N5_AD8N_67
IO_L16P_T2U_N6_QBC_AD3P_67IO_L16N_T2U_N7_QBC_AD3N_67
IO_L8N_T1L_N3_AD5N_68
IO_L24N_T3U_N11_68
IO_L14P_T2L_N2_GC_68
IO_T1U_N12_68
USB_OTG_P
ETH_MD4_NETH_MD4_P
PS_GTR_RX2_505_PPS_GTR_RX2_505_N
IO_L18P_T2U_N10_AD2P_68
PS_MODE3_503
IO_T0U_N12_VRP_67
IO_L4P_T0U_N6_DBC_AD7P_67
IO_L2N_T0L_N3_68
IO_L1P_T0L_N0_DBC_68
IO_L21P_T3L_N4_AD8P_65
IO_L24P_T3U_N10_65
IO_L6N_T0U_N11_AD6N_65
IO_L2P_T0L_N2_68
IO_L18N_T2U_N11_AD2N_68
IO_T1U_N12_67
VCCO_65
IO_L2N_T0L_N3_65
IO_L20P_T3L_N2_AD1P_65
IO_T1U_N12_SMBALERT_65IO_T0U_N12_VRP_65
IO_L3P_T0L_N4_AD15P_68
IO_L18P_T2U_N10_AD2P_65IO_L18N_T2U_N11_AD2N_65
PS_DONEPS_INIT_B
PS_ERROR_OUTETH_PHY_LED1
ETH_MD3_P
PS_GTR_RX3_505_N
ETH_MD2_P
PS_GTR_RX1_505_P
ETH_MD2_N
PS_GTR_RX0_505_P
ETH_PHY_LED0
ETH_MD3_N
S_OUT_NS_OUT_P
S_IN_N
PS_MODE0_503
USB_OTG_N
USB_VBUS_OTG
PS_MODE2_503PS_MODE1_503
PS_GTR_TX0_505_N
PS_GTR_TX1_505_P
PS_GTR_TX3_505_N
PS_GTR_TX2_505_N
PS_GTR_TX1_505_N
PS_GTR_TX2_505_P
PS_GTR_TX3_505_P
USB_OTG_CPEN
PS_GTR_RX0_505_N
ETH_MD1_P
USB_ID
PS_GTR_REFCLK0_505_PPS_GTR_REFCLK0_505_N
VCC_PSBATT
D29D30
J17J18
K14
K8
J12
J2
H5
G8
G15G14
H24H25
J38J39
H32H31
G16
F4
F23
G11G10
G20
G17
G7
H11J11
J14
J27
J40G39
F34
E31E32
E30
F32
G35
H37H38
K4
J13
J8J7
H33
J25
K18
C37
B30
A19
C27
C30C31
C10
C8 B8C9
D14D13
D11
C16
C13C14
D25
C20
B38
D20
D24D23D22
D5D6
D8
K24 J24
J28J29J30J31
K5
H17H16H15
G9
H20
D21
C1
D10D9
C7
D2
C15
C11
D15
D19
D16
C12
D4
C22
C19
C35
C29
C38
C2C3C4C5C6
C17C18
C21
C23C24C25C26
C28
C32
C36
C39
D18
K38
D26
B16
K15
K13
K16K17
K12K11K10K9
K7K6
H2
D1
B15
D27
B1
F9
F7F6
H3
F39
F31
B11
E35
F38E37
E34
F21
E4
E40E39E38
E36
E33
E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14
E12E11E10E9E8E7E6E5
E3E2E1
E13
G18
F33
F14F13
F28
F30
F40
F37F36F35
F29
F27F26F25F24
F22
F20F19F18F17F16F15
F12F11F10
F8
F5
F3F2F1
H10H9
G4
G1
G40
G38G37G36
G34G33G32G31G30G29G28G27G26G25G24G23G22G21
G19
G13G12
G6G5
G3G2
H40H39
H36H35H34
H30H29H28H27H26
H23H22H21
H19H18
H14H13H12
H8H7H6
H4
H1
K28
J16
J9
J37J36J35J34J33J32
J26
J23J22J21
J19
J15
J10
J6J5J4J3
J1
J20
K40K39
K37K36K35K34K33K32K31K30K29
K27K26K25
K23K22K21K20K19
K3K2K1
A25A26
A30
B2B3B4B5B6B7
B9B10
B12B13B14
B17B18B19B20B21B22B23B24B25B26B27B28B29
B31B32B33B34B35B36B37
B39B40
D3
D7
D12
D17
D28
D31D32D33
D35D36D37D38D39D40
A1
A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
A20A21A22A23A24
A27A28A29
A31A32A33A34A35A36A37A38A39A40
A2
D34
C40
C33C34
GNDGND
GND
GND
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 3: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/3.jpg)
SOM SIGNAL INTERFACE
1V8 GPIOS
1V8 GPIOS
3 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ASP-134486-01
ASP-134486-01
ASP-134486-01 ASP-134486-01
ASP-134486-01 ASP-134486-01 ASP-134486-01ASP-134486-01
ASP-134486-01
ASP-134486-01
P1P1P1 P1
P1P1P1P1P1P1
GPIO_3P3_3_A
GPIO_13_AGPIO_14_A
1V8
MGTHTXN3_229
MGTHRXN3_228
MGTHTXP1_226MGTHTXN1_226
MGTHTXP1_224MGTHTXN1_224
MGTHTXP2_227
MGTHRXN1_228
MGTHRXP0_224MGTHRXN0_224
MGTHTXN2_224MGTHTXP2_224
MGTHTXN1_225MGTHTXP1_225
MGTREFCLK0P_229
GPIO_0_AGPIO_1_A
RF_SYNTH_VTUNE_A
GPIO_3P3_2_A
GPIO_3P3_1_AGPIO_3P3_0_A
IO_L20P_T3L_N2_AD1P_66SPI_MOSISPI_MISOSPI_CLK
IO_L19N_T3L_N1_DBC_AD9N_66IO_L19P_T3L_N0_DBC_AD9P_66
GPIO_15_B
RX2_ENABLE_BTX1_ENABLE_BTX2_ENABLE_BRX2_ENABLE_ATX1_ENABLE_A
GPIO_17_ARX1_ENABLE_A
RF_SYNTH_VTUNE_BAUX_SYNTH_VTUNE_B
GPIO_7_A IO_L12P_T1U_N10_GC_64
IO_L13P_T2L_N0_GC_QBC_64IO_L13N_T2L_N1_GC_QBC_64IO_L14P_T2L_N2_GC_64
IO_L12N_T1U_N11_GC_64
GPIO_2_A
AUX_SYNTH_VTUNE_AAUX_SYNTH_OUT_A
GPIO_6_ATX2_ENABLE_A
GPIO_18_A
GPIO_16_AGPIO_15_A
GPIO_12_AGPIO_11_AGPIO_10_AGPIO_9_AGPIO_8_A
GPIO_5_AGPIO_4_AGPIO_3_A
1V8
GPIO_3P3_11_AGPIO_3P3_10_A
GPIO_3P3_5_AGPIO_3P3_4_AGPIO_3P3_11_BGPIO_3P3_10_BGPIO_3P3_9_BGPIO_3P3_8_BGPIO_3P3_7_BGPIO_3P3_6_BGPIO_3P3_5_BGPIO_3P3_4_BGPIO_3P3_3_B
VDDA3P3
GPIO_3P3_6_AGPIO_3P3_7_AGPIO_3P3_8_AGPIO_3P3_9_A
AUXADC_0_B
AUXADC_2_B
AUXADC_1_B
GPIO_3P3_2_BGPIO_3P3_1_B
AUXADC_3_BAUX_SYNTH_OUT_B
CLKIN3_HMC7044_NCLKIN3_HMC7044_P
CLKIN0_HMC7044_NCLKIN0_HMC7044_P
CLKIN1_HMC7044_NCLKIN1_HMC7044_P
GPIO_13_B
GPIO_17_BGPIO_16_B
GPIO_9_B
GPIO_12_B
GPIO_18_B
MGTHTXP1_229
MGTHTXN3_228
MGTREFCLK0N_229
MGTHTXP3_228
AUXADC_0_A
MGTREFCLK0P_228MGTREFCLK0N_228
MGTHRXP2_229MGTHRXN2_229
AUXADC_1_A
SYNC_HMC7044
PWR_FAULT2PWR_FAULT1
RX1_ENABLE_B
GPIO_10_B
GPIO_6_B
GPIO_2_BGPIO_1_BGPIO_0_B
GPIO_8_B
IO_L14N_T2L_N3_GC_64
GPIO_7_B
AUXADC_3_A
AUXADC_2_A
GPIO_3P3_0_B
MGTHRXP3_229
MGTREFCLK1N_228MGTHTXP3_229
MGTHRXP1_229MGTHRXN1_229
MGTREFCLK1P_228
MGTHRXP0_229MGTHRXN0_229
MGTHRXN3_229
MGTHRXP3_228
MGTHTXN0_228
GPIO_5_B
MGTHRXP0_227MGTHRXN0_227
MGTHRXP2_226MGTHRXN2_226
MGTHTXN2_228
MGTHRXN2_228
MGTHTXN1_229
MGTHTXN1_227
MGTHRXP3_226MGTHRXN3_226
MGTHRXP0_226MGTHRXN0_226
MGTHTXP3_227
MGTREFCLK0N_226
MGTREFCLK0P_227MGTREFCLK0N_227
MGTREFCLK0P_226
MGTHTXN3_227
MGTHTXP1_228
MGTREFCLK1P_227
MGTHTXN2_227
MGTHTXN1_228
MGTREFCLK1P_229
MGTHTXP2_226
MGTHRXN2_227
MGTREFCLK1N_229
MGTHTXP0_228
MGTHRXP2_228
MGTREFCLK1N_226
MGTHTXN3_226
MGTHTXP0_226
MGTHTXN0_227
MGTREFCLK0P_225MGTREFCLK0N_225
MGTHRXN3_224MGTHRXP3_224
MGTHRXP0_228MGTHRXN0_228
MGTHRXP1_226
MGTHRXP1_227
MGTHRXN1_226
MGTHRXN1_227
MGTHRXN2_225MGTHRXP2_225
MGTHRXN3_225MGTHRXP3_225
MGTHRXP0_225MGTHRXN0_225
MGTHRXP1_224MGTHRXN1_224
MGTHTXN0_226
MGTHRXN1_225MGTHRXP1_225
MGTHRXP2_224MGTHRXN2_224
MGTHTXP2_225
MGTREFCLK0P_224
MGTHTXN3_224MGTHTXP3_224
MGTREFCLK1P_225
MGTHTXN2_225
MGTHTXP0_224
MGTHTXP1_227
MGTREFCLK1N_225
MGTHTXN3_225
MGTHTXP0_225
MGTHTXP3_225
MGTHTXN0_225
MGTHTXN0_229
MGTHTXN2_229MGTHTXP0_229
MGTREFCLK1N_227
MGTHTXN2_226
MGTHTXN0_224MGTREFCLK1P_224
MGTREFCLK0N_224
GPIO_14_B
GPIO_11_B
GPIO_4_BGPIO_3_B
MGTHTXP2_228
MGTREFCLK1N_224
MGTREFCLK1P_226
MGTHTXP3_226
MGTHRXP1_228
MGTHTXP2_229
MGTHTXP0_227
MGTHRXN3_227MGTHRXP3_227MGTHRXP2_227
C30
B37 A37
H25
J21
K11
K26
H31
G12
G39
J34
J37J38
K12
K14
K23K24
C5
C11A12
A36
A39A40
A32A31
A34A33
A29A28A27
C29C28
C25C26
C18
B35B34B33
B22
C27B26
B29B30B31B32
B23B24
C13
C19
C17C16
C23
C15C14
C12
C10
C21C20
C7C8C9
B4C4
D20D21
D14
D8D7D6
B13
B15
C24
B19
A14
B10
A7
H40
J30
A15A16
A6A5A4
J35
D3C2
C31
C6
C3
D31
D34
D24
D28
D25
D33D32
D27
D19D18D17D16D15
D10
D23
D13
D11D12
B38
D9
D22
A30
A35
A1A2
B1
B3
B18
B2
C36
C32
C22
B25
B27
C40C39
C35
C1
D30
D26
K19K20
J27
B6
G38
H14H13
H8
H28
G22
G15
G8
G1
F28F27
F25
F22F21F20
B11
D36
A9
F35
A3
E40E39
E37E36
F39
G33
H30
H26H27
J36
J32
D37D38D39
F31
G29
H36K35K34
K32K31K30K29K28K27
J31
G27
F24
E17E16
F18
G20G19
H22
J19 H19
J23
J25
G14
G21
G17G16
H24
H29
J18
J22K22
E38
E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18
E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1
F19
H12
H6
F12F13F14
F16F15
G13
H11H10H9
H7
J12
J17J16
J4
K7
K17
K13
K9
G7
G2
J14J13
K3K4K5
K18
K6
K8
F33
G30
J24
F17
H20
H18
B12
B14
B16B17
A25
A23
D4D5
D1
D35
D2
D29
D40
F38
F1F2F3F4F5F6F7F8F9F10F11
F23
F26
F29F30
F32
F34
F36F37
G4
G6
G10
G5
G9
G11
G18
G23G24G25G26
G28
G31G32
G34G35G36
G40
G37
H33
H21
H5
H1H2H3H4
H15H16H17
H23
H32
H34H35
H37H38H39
J5
K2
J6
J1J2J3
J7J8J9
J10J11
J15
J20
J26
J28J29
J33
J39J40
K1
K10
K15K16
K21
K25
K33
K36K37K38K39K40
B40
B36
A38
A26
A24
A22A21A20A19A18A17
A13
A11A10
A8
B39
B28
B21B20
B9B8B7
B5
C38C37
C34C33
G3
F40
GNDGNDGNDGND
GNDGNDGNDGNDGNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 4: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/4.jpg)
STANDBY - 1 OR OPEN: OSCILLATION
PHY1
CONNECTED TO GEM 3: MIO64...75ETHERNET PHY
USB PHYCONNECTED TO USB0 : MIO52...63
4 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
220
BSS138LT1G
BSS138LT1G
39
NC7SZ08FHX
4.99K
0
24MEGHZUSB3320C-EZK
0.1UF
0.1UF
0
220
100OHM
L0805
41
L0805
100OHM
L0805
100OHM
1K
BSS138LT1G
1K
1K
BSS138LT1G
1UF
27PF
10
0.1UF
0.1UF
1UF10UF
4.7UF
51
4.7UF
4.7UF
51
1UF0.1UF 0.1UF
0.1UF 0.1UF
0.1UF 0.1UF
0.1UF 0.1UF 0.1UF
0.1UF
NC7SZ08FHX
88E1512-A0-NNP2I000
0.1UF
0.1UF 4.7UF
0.1UF
27PF
4.7UF
25MEGHZ
0.1UF
8.06K
4.7K
1UF0.1UF0.1UF
1K
2.2UF0 DNI
Q2
R69
R66
R62
U33
Y2
C192
C197
R59
R61
R70
E4
E5
E6
Q4R67
R65
C201
C196
C191
U32
C214C211
C217C215
C219C216C213C207C205
C220
C222C210C209
C193
U7
C194
C206 C208
C218
Y3
C223
C212
C198
C224
C203 C204
C221
U34
R63
R64
C195 C199 C200
R58
Q5
Q3
R68
R60
PHY1_AVDD_1V8S_OUT_P
PS_MIO59_502_USB0_D3PS_MIO60_502_USB0_D4PS_MIO61_502_USB0_D5PS_MIO62_502_USB0_D6
USB_OTG_NUSB_OTG_P
USB_VBUS_OTG
3V3
PS_MIO56_502_USB0_D0
PS_MIO55_502_USB0_NXT
PS_MIO26_501_ID
USB_ID
ETH_PHY_LED1
ETH_PHY_LED0
PHY1_LED_0
PHY1_LED_1
PHY1_VDD_3V3
USB_OTG_CPEN
PS_MIO58_502_USB0_STP
ETH_MD1_PETH_MD1_NETH_MD2_P
PHY1_LED_0PHY1_LED_1
PS_MIO76_502_ETH_MDCPHY1_DVDD_1V0
S_OUT_N
1V8
PHY1_1V8
1V8
ETH_MD3_P
PS_MIO71_502_ETH3_RX_D0PS_MIO72_502_ETH3_RX_D1PS_MIO73_502_ETH3_RX_D2PS_MIO74_502_ETH3_RX_D3
ETH_MD2_NPS_MIO25_500_ETH3_RESET_B
ETH_MD4_PETH_MD3_N
1V8
PG_ALL
PS_MIO70_502_ETH3_RX_CLK
PS_MIO57_502_USB0_D1
3V3
PHY1_AVDD_3V3
PS_MIO64_502_ETH3_TX_CLK
PS_MIO66_502_ETH3_TX_D1PS_MIO67_502_ETH3_TX_D2
PS_MIO65_502_ETH3_TX_D0
PHY1_DVDD_1V0
PG_ALL
1V8
PHY1_AVDD_3V3
PHY1_1V8
PHY1_1V8 PHY1_VDD_3V3
PHY1_AVDD_1V8
PS_MIO63_502_USB0_D7
PHY1_AVDD_1V8_OUT
PHY1_AVDD_1V8_OUT
PHY1_AVDD_1V8
1V8
PHY1_AVDD_3V3
PHY1_VDD_3V3
PHY1_VDD_3V3
PS_MIO75_502_ETH3_RX_CTL
PHY1_DVDD_1V0
PS_MIO69_502_ETH3_TX_CTL
PS_MIO68_502_ETH3_TX_D3
PS_MIO54_502_USB0_D2
PS_MIO77_502_ETH_MDIO
S_IN_PS_IN_N
PHY1_AVDD_1V8
PS_MIO52_502_USB0_CLKPS_MIO53_502_USB0_DIR
ETH_MD4_N
PHY1_VDD_3V3
3V3
PS_MIO13_500_USB0_RESET_B
1V8
3V3
2
3
1
2
3
1
2
3
1
2
3
1
13
12
3
4
5
6
12
3
4
5
6
26
15
32
25
26
21
21
21
3
19
3310
52 49
11
55 54 5056 53
45
2
48 47 45 4446
30
16
41
36
PAD
18 22 28
8
17 21 27
7
121314
3231
40
6
15
935
2520
39
19
31
42
22
2927
14
8
2
23
18
31
1097654
1
4
1 3
2 12
24
17
21
PAD
43
42
51
3
29
24
34
3738
1
16
3028
23
20
11
GND
GND
PINSPARE
GND
GND
GNDGND
GND
GND
GND
PAD
TX_C
TRL
TXD(
3)TX
D(2)
TX_C
LKVD
DOTX
D(1)
TXD(
0)VD
DORX
D(3)
RXD(
2)RX
_CLK
RXD(
1)RX
D(0)
RX_C
TRL
DVDDREGCAP2
DVDD_OUTAVDD18_OUT
AVDD18REGCAP1
REG_INAVDDC18XTAL_IN
XTAL_OUTHSDACPHSDACN
RSETTSTPT
MDI
P(0)
MDI
N(0)
AVDD
18AV
DD33
MDI
P(1)
MDI
N(1)
MDI
P(2)
MDI
N(2)
AVDD
33AV
DD18
MDI
P(3)
MDI
N(3)
RESE
TNCO
NFIG
LED(0)LED(1)LED(2)/INTNVDDOVDDO_SELCLK125MDIOMDCDVDDS_OUTNS_OUTPAVDD18S_INNS_INP
GND
GND
GNDGNDGND
PINSPARE
PINSPARE
PINSPARE
PINSPARE
PINSPARE
GND
GND
GND
GND
VCC
NC
Y
GNDBA
PINSPARE
GND_FLAG
VDDI
O
DIR
VDD1
8
STP
VDD1
8
RESETB
REFCLK
XO
RBIAS
IDVBUSVBAT
VDD3
3
DMDP
CPEN
SPK_RSPK_L
REFSEL2
DATA7
N/C
REFSEL1
DATA6DATA5
REFSEL0
DATA4DATA3DATA2DATA1DATA0
NXT
CLKOUT
GND
GND
PINSPARE
GNDPIN
SPARE
GND
GND
VCC
NC
Y
GNDBA
GND
GND
VDDSTANDBY
GNDOUTPUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 5: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/5.jpg)
QSPI FLASH
ZYNQ ULTRASCALE SUPPORTS V3.0 (104MBYTE/S). A 3.0 COMPLIANT TRANSLATOR NEEDS TO BE USED
ACTIVE "0"
DAT2
CMD
CLK
DAT0
VDD
CD/DAT3
VSS
DAT1
SD CARD
SDIO_SEL = GND FOR CARRIER SD
CONTROLLED BY CARRIER:
SDIO_SEL = OPEN FOR SOM SD
SWITCH SHOWN FOR LOGIC 1
5 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ADG849YKSZ
0.1UF
10K
10K
MT25QU512ABB1EW9-0SIT
4.7K
MT25QU512ABB1EW9-0SIT
0 0.1UF
IP4856CX25/CZ
10K
FSA1208BQX
FSA1208BQX
0.1UF
10K
1000PF
0 DNI
DM3BT-DSF-PEJS
4.7K
0.1UF
0.1UF
0.1UF
1UF 4.7UF
1000PF
1UF
0.1UF
4.7K
4.7K
4.7K4.7K4.7K
4.7K
C226U35
C225
R72
R78
R80R76
C236
R82
C232
U10
C230
U37
R74 R75
R419
R418
P3
C227
R71
C228
U36
U8U9
C231
C235
C229
C233 C234
R81
R73
R77R79
1V8
1V8
1V8
SDIO_SEL
SDIO_CARRIER_CMD
1V8
SDIO_CARRIER_SEL
SDIO_CARRIER_CD
SDIO_CARRIER_DAT2SDIO_CARRIER_DAT1SDIO_CARRIER_DAT0
SDIO_CARRIER_DAT3
SDIO_CARRIER_CLK
PS_MIO49_501_SDIO_DAT3
PS_MIO47_501_SDIO_DAT1
PS_MIO50_501_SDIO_CMD
PS_MIO45_501_SDIO_DETECT
SDIO_CARRIER_SEL
SDIO_SOM_SEL
PS_MIO05_500_QSPI_LWR_SS_BPS_MIO00_500_QSPI_LWR_SCLK
PS_MIO03_500_QSPI_LWR_IO3PS_MIO02_500_QSPI_LWR_IO2PS_MIO01_500_QSPI_LWR_IO1PS_MIO04_500_QSPI_LWR_IO0
PS_MIO07_500_QSPI_UPR_SS_B
PS_MIO48_501_SDIO_DAT2
PS_MIO46_501_SDIO_DAT0
PS_MIO42_501_SDIO_DIR_DAT1_3PS_MIO41_501_SDIO_DIR_DAT0
PS_MIO40_501_SDIO_DIR_CMD
SDIO_DAT3
SDIO_DAT0
PS_MIO51_501_SDIO_CLK
PS_MIO39_501_SDIO_SEL
PS_MIO45_501_SDIO_DETECT
SDIO_CMDSDIO_CLK
SDIO_DAT1SDIO_DAT2
SDIO_DAT0SDIO_DAT1SDIO_DAT2SDIO_DAT3SDIO_CMDSDIO_CLK
SDIO_SOM_CDSDIO_SOM_CLK
SDIO_SOM_SEL
SDIO_SOM_CMD
3V3
SDIO_SOM_CD
1V8
SDIO_SOM_CMDSDIO_SOM_DAT3SDIO_SOM_DAT2
SDIO_SOM_CLK
SDIO_SOM_DAT0
1V8
SDIO_SOM_DAT1
SDIO_SOM_DAT1
3V3
1V8
PS_MIO10_500_QSPI_UPR_IO2PS_MIO11_500_QSPI_UPR_IO3
1V8
PS_MIO12_500_QSPI_UPR_SCLKPS_MIO08_500_QSPI_UPR_IO0PS_MIO09_500_QSPI_UPR_IO1
1V8 1V8
3V3
1V8
3V3
SDIO_SOM_DAT0
3V3
SDIO_SOM_DAT2SDIO_SOM_DAT3
1V8
3V3
2
6
3
5 4
1
16
D1 D5E5
B5A5
D3
A1B1
D4C5
E2
C3
D2A2C1
A3E3
E1
C2
PAD11 10
7
5
19
20
7 1413
9
4
8
15
18
SH2
A
6
8
5
SH1
SH3
1
7
4
SH4
B
23
652
7
PAD
1
8
4
3 652
7
PAD
1
8
4
3
B2
B3
B4
C4
A4
E4
23456
89
19
171615
12
1
3
6
1817
141312
PAD10
20
1
11
2
S2VDD
INGND
S1D
SHLDPINS
GND
GND
GND
GND
GND
PAD
OE_N
B1B2B3B4B5B6B7B8
NC GND
A8A7A6A5A4A3A2A1
VCC
GND
GND
GND
GND
PAD
OE_N
B1B2B3B4B5B6B7B8
NC GND
A8A7A6A5A4A3A2A1
VCC
GND
GND
GND
GNDGND
GND
DIR_1_3
VCCA
DATA3_SD
VLDO
ENABLE
DATA1_SD
GND
VSD_REFSEL
DATA3_HDATA2_SD
VSUPPLY
DIR_0
DIR_CMD
DATA2_H
WP
CLK_FB
DATA1_HDATA0_SD
CMD_SD
CD
CMD_H
DATA0_H
CLK_SDCLK_IN
GND
GND
PAD
VCC
HOLD#/DQ3
CDQ0
VSS
W#/DQ2DQ1
S#PAD
VCC
HOLD#/DQ3
CDQ0
VSS
W#/DQ2DQ1
S#
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 6: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/6.jpg)
KEEP MIO6 UNCONNECTED FOR THE LOOPBACK FEATURE
PS BANK 501 1V8
PULL-DOWN ON SD WP FOR WRITE ENABLE
PS BANK 502 1V8
BANK 500 BANK 501 BANK 502
PS BANK 500 1V8
PS BANK 503 1V8
PG_ALL FROM CARRIER, OPEN DRAIN
BOOT AND CONFIGURATION
ASSERTED AFTER PG_SOM AND PG_CARRIER
BANK 503
6 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
33PF
100100
30
XCZU11EG-1FFVF1517I
22PF
4.7MEG
20
10KDNI
39
18
30
30
30
30
30
30
30
30
30
30
30
30
30
30
1K
4.7K4.7K
4.7K4.7K4.7K4.7K
4.7K4.7K4.7K4.7K4.7K
22
4.7K
17
10KDNI
16
XCZU11EG-1FFVF1517I
0.032768MEGHZ
22PF
33.333MEGHZ
0.1UF
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
100UF100UF 100UF 100UF 100UF100UF 100UF 100UF
0.1UF
4.7UF4.7UF 4.7UF4.7UF
C7
R558R557
R16R7
R411
U21
C1094
R4R2
R3
R9
R8R13
R12
R11
R20
R19
R17
R18
R24
R23
R22
R21
R10
R15R14
R415R414R413R412
R410R409R408R407R6R5
R1
C1095
Y4
Y7
C2
U21U21
C1 C5 C9 C12C3 C6 C10 C13C4 C8 C11 C14
C15
U21
I2C0_SDAPS_MIO15_500_I2C0_SDAI2C0_SCLPS_MIO14_500_I2C0_SCL
PS_MIO52_502_USB0_CLKPS_MIO53_502_USB0_DIR
PS_MIO42_501_SDIO_DIR_DAT1_3PS_MIO41_501_SDIO_DIR_DAT0PS_MIO40_501_SDIO_DIR_CMDPS_MIO39_501_SDIO_SEL
PS_MIO02_500_QSPI_LWR_IO2
PS_ERROR_OUT
PS_MODE2_503
PS_MIO16_500_UART1_TXDPS_MIO15_500_I2C0_SDAPS_MIO14_500_I2C0_SCLPS_MIO13_500_USB0_RESET_BPS_MIO12_500_QSPI_UPR_SCLKPS_MIO11_500_QSPI_UPR_IO3PS_MIO10_500_QSPI_UPR_IO2
PS_MIO20_500_SPI1_N_SS_OUT1
PS_MIO22_500_SPI1_SCLK_OUTPS_MIO19_500_SPI1_N_SS_OUT2
PS_MIO01_500_QSPI_LWR_IO1PS_MIO00_500_QSPI_LWR_SCLK
PS_MIO25_500_ETH3_RESET_BPS_MIO24_500_AD9542_RESET_BPS_MIO23_500_SPI1_MOSI
PS_MIO21_500_SPI1_N_SS_OUT0
PS_MIO64_502_ETH3_TX_CLKPS_MIO63_502_USB0_D7
PS_MIO49_501_SDIO_DAT3PS_MIO50_501_SDIO_CMDPS_MIO51_501_SDIO_CLK
PS_MIO08_500_QSPI_UPR_IO0PS_MIO07_500_QSPI_UPR_SS_B
PS_MIO54_502_USB0_D2
PS_MIO03_500_QSPI_LWR_IO3
PS_MIO05_500_QSPI_LWR_SS_BPS_MIO04_500_QSPI_LWR_IO0
PS_MIO09_500_QSPI_UPR_IO1
PS_MIO17_500_UART1_RXDPS_MIO18_500_SPI1_MISO
PS_MODE3_503
PS_MODE0_503
JTAG_TDO
PS_ERROR_STATUS
1V8
JTAG_TCKJTAG_TDIJTAG_TMS
PS_PROG_BPG_ALL
1V8
PS_SRST_B
1V8
PS_MODE1_503
PS_DONE
1V8
PS_INIT_B
1V8
1V8
PS_MIO34_501_UART0_RXD
PS_MIO27_501_DPAUX_DATA_OUT
PS_MIO46_501_SDIO_DAT0
PS_MIO48_501_SDIO_DAT2PS_MIO47_501_SDIO_DAT1
PS_MIO61_502_USB0_D5
PS_MIO57_502_USB0_D1
PS_MIO59_502_USB0_D3
PS_MIO62_502_USB0_D6
PS_MIO60_502_USB0_D4
PS_MIO58_502_USB0_STP
PS_MIO56_502_USB0_D0
PS_MIO77_502_ETH_MDIOPS_MIO76_502_ETH_MDCPS_MIO75_502_ETH3_RX_CTLPS_MIO74_502_ETH3_RX_D3PS_MIO73_502_ETH3_RX_D2PS_MIO72_502_ETH3_RX_D1PS_MIO71_502_ETH3_RX_D0PS_MIO70_502_ETH3_RX_CLKPS_MIO69_502_ETH3_TX_CTLPS_MIO68_502_ETH3_TX_D3PS_MIO67_502_ETH3_TX_D2PS_MIO66_502_ETH3_TX_D1PS_MIO65_502_ETH3_TX_D0
PS_MIO55_502_USB0_NXT
PS_MIO45_501_SDIO_DETECT
PS_MIO38_501PS_MIO37_501PS_MIO36_501PS_MIO35_501_UART0_TXD
PS_MIO33_501_I2C1_SDAPS_MIO32_501_I2C1_SCLPS_MIO31_501PS_MIO30_501_DPAUX_DATA_INPS_MIO29_501_DPAUX_DATA_OEPS_MIO28_501_DPAUX_HOT_PLUG_DET
PS_MIO26_501_ID
1V8
1V8
1V8
VCC_ADC
1V81V8 1V8
GND_ADC
AE30AH32
Y28
R27
N27
Y30N28
AA30
N33
AB28
W30
V27
T28
P29
L31
K39
AG29
AG31AH31AK30
AH27AH28AJ27AH29
AJ30
AG30AG28
AF29
AJ31
AE29AF31
AF30
AJ29
AJ28
2
1
4
3
P38
P33
R32N32R39P31N34P30R37R34P35R33M30P32R30P36
N36
P37N38N37N39M31R35R38P39P34N31
L34
J38
J36
M39M38
J39J37K33L35L38J34J35L37L36
M33K35K34L32L30M36M35M34K32K38L33K37
Y29R28
U30
W29W27
U29
T30M29R29M28
P27V28V29U28N29T27
AC28
P28
W28
GNDGND
VCCO
_PSI
O3_
503
VCCO
_PSI
O3_
503
PS_SRST_BPS_REF_CLKPS_PROG_BPS_POR_B
PS_PADO
PS_PADI
PS_MODE3PS_MODE2PS_MODE1PS_MODE0
PS_JTAG_TMSPS_JTAG_TDO
PS_JTAG_TDIPS_JTAG_TCK
PS_INIT_BPS_ERROR_STATUS
PS_ERROR_OUTPS_DONE
VCCO
_PSI
O2_
502
VCCO
_PSI
O2_
502
PS_MIO77PS_MIO76PS_MIO75PS_MIO74PS_MIO73PS_MIO72PS_MIO71PS_MIO70PS_MIO69PS_MIO68PS_MIO67PS_MIO66PS_MIO65PS_MIO64
PS_MIO63PS_MIO62PS_MIO61PS_MIO60PS_MIO59PS_MIO58PS_MIO57PS_MIO56PS_MIO55PS_MIO54PS_MIO53PS_MIO52
VCCO
_PSI
O1_
501
VCCO
_PSI
O1_
501
PS_MIO51PS_MIO50PS_MIO49PS_MIO48PS_MIO47PS_MIO46PS_MIO45PS_MIO44PS_MIO43PS_MIO42PS_MIO41PS_MIO40PS_MIO39PS_MIO38
PS_MIO37PS_MIO36PS_MIO35PS_MIO34PS_MIO33PS_MIO32PS_MIO31PS_MIO30PS_MIO29PS_MIO28PS_MIO27PS_MIO26
VCC_
PSAD
CG
ND_P
SADC
VCCO
_PSI
O0_
500
VCCO
_PSI
O0_
500
PS_MIO9PS_MIO8PS_MIO7PS_MIO6PS_MIO5PS_MIO4PS_MIO3
PS_MIO25PS_MIO24PS_MIO23PS_MIO22PS_MIO21PS_MIO20PS_MIO2
PS_MIO19PS_MIO18PS_MIO17PS_MIO16PS_MIO15PS_MIO14PS_MIO13PS_MIO12PS_MIO11PS_MIO10PS_MIO1PS_MIO0
GNDGND
GNDGND
GND
GNDGND
GND
GND
VDDSTANDBY
GNDOUTPUT
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 7: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/7.jpg)
FROM CARRIER
ADDRESS 0X50 - 0X57
ADDRESS 0X4BI2C
PS_GTR_P/N (BANK 505) 100OHM DIFFERENTIAL
GTR REFERENCE CLOCK
M3 = HIGH - LOAD FROM EEPROM
GTR TRANSCEIVERS
7 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
NC7SZ08FHX
4.7K
R0402L R0402L
15PF15PF
DNI
R0402L
49.9
49.152MEGHZ
DNI
0.22UF0.22UF
AD9542BCPZ
3900PF
0
R0402L
4.7K
4.7K4.7K
0
DNI
0DNI
0
24AA16-I/SN
100K
3900PF
100K
C0603L
100K
C0603L
0.1UF
DNI
0.1UF
0.1UF
0.1UF120OHM
0.1UF 0.1UF
R0402L
10
49.9
49.9
49.9
49.9
R0402L
49.9
R0402L
R0402L
49.9
49.9
DNI
1UF120OHMDNI
10UF 0.1UF
DNI
0.1UF
0.01UF
0.01UF
0.01UF
24MEGHZ
DNI
0.01UF
0.01UF
0.1UF49.9
49.9
0.1UF
49.9
10
R0402L
R0402L
R0402L
0.1UF 10UF1UF1UF0.1UF0.1UF
R0402L
49.9 R0402L
R0402L 0.01UF
R0402L
R0402L
0.1UF
XCZU11EG-1FFVF1517I
49.9
DNI
0.1UF100K
0.1UF
49.9
R0402LR0402L
4.7K
1UF
R0402L
R0402L
R0402L
49.9
4.7K
R0402L
R561
U1
C23C22
C25
Y5
C20 C24
R360
R564R417
R465
R566R563
R565R562
R466
R27R26
R25
C1124
R31
C37
R416
C47
C30
E3
C31C46 C27
R42
R41
R40
R33
R36
R37
R32
C21
C45
C16
Y1
C18 C19
C41
C36
C43
C34
C33
E2
C44
C42
R35
R28
R38
R39
C40
C48
C28 C39C38C29
R34
C26
C35
U29
C17
C32
R30
U21
R29
R559
U49
R560
PS_GTR_TX2_505_NPS_GTR_TX3_505_NPS_GTR_TX0_505_PPS_GTR_TX1_505_PPS_GTR_TX2_505_P
PS_GTR_TX1_505_NPS_GTR_TX0_505_N
OUT1_A_P
1V8_VDDIOB
1V8_VDDIOB
1V8_AD9542
RESETB_AD9542
OUT1_B_P
OUT1_B_N
1V8_AD9542
1V8_VDDIOB
PS_MIO24_500_AD9542_RESET_B
PS_GTR_REFCLK0_505_PPS_GTR_REFCLK0_505_N
PS_GTR_125MHZ_505_NPS_GTR_125MHZ_505_PPS_GTR_27MHZ_505_N
1V8_AD9542
1V8_AD9542
1V8_AD9542
1V8_VDDIOBI2C_MASTER_SDAI2C_MASTER_SCL
1V8_AD9542
1V8_VDDIOA
I2C0_SDA
1V8_AD9542
1V8_AD9542
OUT1_A_N
1V8_VDDIOA
1V8_AD9542
1V8_AD9542
1V8_AD9542
OUT0_B_P
PL_DDR4_1_CKIN_71_N
PS_GTR_26MHZ_505_N
1V8_AD9542
OUT0_A_N
1V8_AD9542
OUT0_C_N
1V8 1V8_AD9542
I2C_MASTER_SCL
OUT0_A_N
PS_GTR_26MHZ_505_P
1V8
1V8
OUT1_A_P
OUT0_B_N
OUT0_A_P
PS_GTR_125MHZ_505_N
PG_ALL
1V8PS_GTR_27MHZ_505_P
PS_GTR_27MHZ_505_N
PL_DDR4_1_CKIN_71_P1V2_PL_DDR4
PL_DDR4_0_CKIN_69_P
PL_DDR4_0_CKIN_69_N
1V2_PL_DDR4
1V8
1V8_VDDIOB
PS_GTR_RX2_505_N
PS_GTR_RX0_505_P
PS_GTR_26MHZ_505_N
PS_GTR_RX0_505_N
PS_GTR_RX3_505_N
PS_GTR_TX3_505_PPS_GTR_RX3_505_PPS_GTR_RX2_505_PPS_GTR_RX1_505_P
PS_GTR_RX1_505_N
PS_GTR_26MHZ_505_P
PS_GTR_27MHZ_505_P
1V8PS_GTR_125MHZ_505_P
OUT1_B_P
OUT1_A_N
1V8
OUT1_B_N
OUT0_A_P
1V8
I2C0_SCLI2C0_SDA
OUT0_B_N
OUT0_C_POUT0_C_N
RESETB_AD9542
OUT0_B_P
1V8_VDDIOB
OUT0_C_P
1V8_AD9542
I2C0_SCL
I2C_MASTER_SDA
1V8_AD9542
12
3
4
5
6
32
373842
AB32
28
2321
11 26
41 40 3945
12
3130
234
PAD
27
29
25
9
15
1
345678
10
13 14 16 17 18 19 20 22 24
33
3536
4344464748
4
1
2
3
AB33
AA35AA34
Y33Y32V33V32
AA39
V37U39
AA38W38V36U38
AB37Y37W35U35AB36Y36W34U34
W39
321
678
4 5
GND
PS_MGTRTXP3_505PS_MGTRTXP2_505PS_MGTRTXP1_505PS_MGTRTXP0_505PS_MGTRTXN3_505PS_MGTRTXN2_505PS_MGTRTXN1_505PS_MGTRTXN0_505
PS_MGTRRXP3_505PS_MGTRRXP2_505PS_MGTRRXP1_505PS_MGTRRXP0_505PS_MGTRRXN3_505PS_MGTRRXN2_505PS_MGTRRXN1_505PS_MGTRRXN0_505PS_MGTREFCLK3P_505PS_MGTREFCLK3N_505PS_MGTREFCLK2P_505PS_MGTREFCLK2N_505PS_MGTREFCLK1P_505PS_MGTREFCLK1N_505PS_MGTREFCLK0P_505PS_MGTREFCLK0N_505
GND
PAD
RESE
TBRE
FARE
FAA
VDD
DNC
XOB
XOA
VDD
VDD
REFB
BRE
FB M4
M3M2
VDDIOBM1M0
VDDLDO1
LF1VDDVDD
OUT1ANOUT1AP
VDD
OUT
1BN
OUT
1BP
DNC
VDD
VDD
OUT
0CN
OUT
0CP
DNC
OUT
0BN
OUT
0BP
VDD
OUT0ANOUT0APVDDVDDLF0LVO0VDDCSB/M6SDIO/SDAVDDIOASCLK/SCLSDO/M5
GND
GND
GND
VSS
VCCWP
A2A1A0
SCLSDA
GND
GND
VCC
NC
Y
GNDBA
GND
GND
GND
GND
GND GND
GND
GND
GND
GNDGNDVDD
STANDBYGND
OUTPUT
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 8: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/8.jpg)
4GBYTE DDR4 WITH ECC
PLACE DIRECTLY UNDERNEATH THE PAD
PS DDR
8 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
240
240
240
22
499
499
0.01UF 0.01UF0.01UF
MT40A512M16LY-062E IT:E
6
0.068UF
4.7UF
11
7
17 16 12 14 18
103418
91319
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
0.01UF0.01UF0.01UF
0.1UF 0.1UF
0.1UF
0.068UF0.068UF 0.068UF0.068UF0.068UF
0.068UF0.068UF
0.068UF0.068UF0.068UF
0.068UF
0.068UF
0.068UF
0.068UF
0.068UF 0.068UF 0.068UF 0.068UF
100UF100UF
5
0.47UF
2
0.47UF
15
0.47UF
20
0.47UF
0.47UF
0.47UF0.47UF
XCZU11EG-1FFVF1517I
21
MT40A512M16LY-062E IT:E
4.7UF
0.068UF
0.47UF
0.1UF
R47
R46
R43
R44
R45
U21
C53C51
U3
C77
U2
C91
C49 C50 C52 C54 C55 C56 C57
C66 C88 C90
C58 C68 C80 C84
C92C85C81C70C60
C76
C93
C94
C89
C86C82
C95C87
C79
C62
C74
C59 C69
C71C61
C73
C75C65
C72
C64 C83
C67
C78C63PS_DDR4_DQ26_504PS_DDR4_DQ25_504PS_DDR4_DQ24_504
PS_DDR4_DQ31_504
PS_DDR4_DQ28_504
PS_DDR4_DQ25_504
PS_DDR4_DQ71_504
PS_DDR4_DQ67_504PS_DDR4_DQ66_504PS_DDR4_DQ65_504
PS_DDR4_DQ51_504PS_DDR4_DQ52_504
PS_DDR4_DQ58_504PS_DDR4_DQ62_504
PS_DDR4_DQ42_504
PS_DDR4_DQ34_504PS_DDR4_DQ36_504
PS_DDR4_DQ23_504PS_DDR4_DQ17_504PS_DDR4_DQ18_504PS_DDR4_DQ21_504PS_DDR4_DQ20_504PS_DDR4_DQ19_504
PS_DDR4_DQ13_504PS_DDR4_DQ15_504PS_DDR4_DQ8_504PS_DDR4_DQ9_504PS_DDR4_DQ11_504PS_DDR4_DQ14_504PS_DDR4_DQ12_504PS_DDR4_DQ3_504PS_DDR4_DQ0_504PS_DDR4_DQ4_504
PS_DDR4_DQ5_504PS_DDR4_DQ2_504PS_DDR4_DQ7_504PS_DDR4_DQ1_504
PS_DDR4_ALERT#
PS_DDR4_DQS6_504_PPS_DDR4_DQS5_504_PPS_DDR4_DQS4_504_PPS_DDR4_DQS3_504_PPS_DDR4_DQS2_504_PPS_DDR4_DQS1_504_PPS_DDR4_DQS0_504_PPS_DDR4_DQS8_504_NPS_DDR4_DQS7_504_NPS_DDR4_DQS6_504_NPS_DDR4_DQS5_504_NPS_DDR4_DQS4_504_N
PS_DDR4_DQS2_504_NPS_DDR4_DQS1_504_NPS_DDR4_DQS0_504_N
PS_DDR4_RESET#PS_DDR4_PARITY
PS_DDR4_ODT0PS_DDR4_DM8_504PS_DDR4_DM7_504PS_DDR4_DM6_504PS_DDR4_DM5_504
PS_DDR4_DM2_504
PS_DDR4_DM0_504
PS_DDR4_CS0#
PS_DDR4_CK0_504_N
PS_DDR4_CKE0
PS_DDR4_CK0_504_P
PS_DDR4_BG0_504PS_DDR4_BA1_504PS_DDR4_BA0_504PS_DDR4_ACT#
PS_DDR4_A16_504PS_DDR4_A15_504PS_DDR4_A14_504PS_DDR4_A13_504PS_DDR4_A12_504PS_DDR4_A11_504PS_DDR4_A10_504PS_DDR4_A9_504PS_DDR4_A8_504PS_DDR4_A7_504PS_DDR4_A6_504PS_DDR4_A5_504PS_DDR4_A4_504PS_DDR4_A3_504PS_DDR4_A2_504PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_DQ6_504
PS_DDR4_DQ10_504
1V2_PS_DDR4
PS_DDR4_CKE0
PS_DDR4_A7_504PS_DDR4_A6_504
VREF_PS_DDR4
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_RESET#
PS_DDR4_A3_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_DQ16_504PS_DDR4_DQ17_504
PS_DDR4_DM3_504
1V2_PS_DDR4
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_A4_504
VREF_PS_DDR4
PS_DDR4_A16_504
PS_DDR4_DQ7_504
PS_DDR4_DQ0_504PS_DDR4_DQ1_504
1V2_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR42V5_VP_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
PS_DDR4_A10_504PS_DDR4_A9_504
PS_DDR4_A7_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_A14_504
PS_DDR4_BG0_504PS_DDR4_BA1_504PS_DDR4_BA0_504
PS_DDR4_A13_504PS_DDR4_A12_504PS_DDR4_A11_504
PS_DDR4_A4_504PS_DDR4_DQS3_504_N
PS_DDR4_CK0_504_NPS_DDR4_CKE0
PS_DDR4_A16_504PS_DDR4_A14_504
PS_DDR4_BG0_504PS_DDR4_BA1_504
PS_DDR4_DQS7_504_PPS_DDR4_DQS8_504_P
PS_DDR4_DQ64_504
PS_DDR4_DQ56_504PS_DDR4_DQ57_504
PS_DDR4_DQ68_504PS_DDR4_DQ69_504PS_DDR4_DQ70_504
PS_DDR4_CS0#PS_DDR4_ODT0PS_DDR4_RESET#
PS_DDR4_PARITY
PS_DDR4_ACT#
PS_DDR4_A15_504 PS_DDR4_DQS0_504_NPS_DDR4_DQS0_504_P
PS_DDR4_DQ15_504
PS_DDR4_DQ11_504PS_DDR4_DQ10_504
PS_DDR4_DQ6_504PS_DDR4_DQ5_504PS_DDR4_DQ4_504PS_DDR4_DQ3_504PS_DDR4_DQ2_504
PS_DDR4_A3_504
PS_DDR4_DQ14_504PS_DDR4_DQ13_504PS_DDR4_DQ12_504
PS_DDR4_DQ9_504PS_DDR4_DQ8_504
PS_DDR4_DQ21_504
PS_DDR4_DQ22_504
PS_DDR4_ALERT#
PS_DDR4_DM1_504PS_DDR4_DM0_504
PS_DDR4_DQS1_504_NPS_DDR4_DQS1_504_P
PS_DDR4_DQ18_504
1V2_PS_DDR4
PS_DDR4_DQ19_504PS_DDR4_DQ20_504
PS_DDR4_DQ22_504
1V2_PS_DDR4
PS_DDR4_DQ60_504PS_DDR4_DQ61_504PS_DDR4_DQ63_504PS_DDR4_DQ59_504
PS_DDR4_DQ55_504PS_DDR4_DQ54_504PS_DDR4_DQ50_504PS_DDR4_DQ48_504PS_DDR4_DQ49_504PS_DDR4_DQ53_504PS_DDR4_DQ41_504PS_DDR4_DQ44_504PS_DDR4_DQ43_504PS_DDR4_DQ45_504PS_DDR4_DQ47_504PS_DDR4_DQ40_504PS_DDR4_DQ46_504
PS_DDR4_DQ32_504PS_DDR4_DQ37_504PS_DDR4_DQ35_504PS_DDR4_DQ33_504PS_DDR4_DQ39_504PS_DDR4_DQ38_504
PS_DDR4_DQ16_504
PS_DDR4_DM1_504
PS_DDR4_DM4_504
PS_DDR4_DQ29_504PS_DDR4_DQ27_504
PS_DDR4_DM3_504
PS_DDR4_DQS3_504_PPS_DDR4_DQS3_504_N
PS_DDR4_DM2_504
PS_DDR4_DQS2_504_N
PS_DDR4_DQ24_504
PS_DDR4_DQ26_504
PS_DDR4_DQ27_504
PS_DDR4_DQ30_504
PS_DDR4_DQ28_504
PS_DDR4_DQS2_504_P
PS_DDR4_DQ31_504PS_DDR4_DQ30_504PS_DDR4_DQ29_504
PS_DDR4_DQ23_504
G3
AR32
AG38
AH36
AJ39
AG35
AF38AE39
AF36
AD35AD36
AE35
AE38
AH39
AG36
AD34
AG33AD32AF32
AH34
AH33AK33
AF35
AN32
AH37
AN34
AV35
AT39
AT34
AP38
AP33
AL34
AL30
AM33AU35AW37
AM38
AE33AK34
AM28AU33AU28AM39AE37AH38
AK35AR33AN28AV33AU29
AN37
AM36AL35
AP31AL27
AK28
AP27AL28AN27AP29AU31AV34AW35AW31AU34AW34AV32AV31AW29AV28AT28AR27AV29AR28AR29AW30
AL38AF37AJ37AE34AJ35
AM29
AU30AP34AW36
AT35AV36
AP35AV38
AR35AV37AL32
AN36
AM34
AL33AJ32AN33AP36AP37AR39AR38AR37AR34AM31AM30AL31AK32AU39AT37AT38AU38AU36AT36
AK29
AF33
AD37
AL37
AN38
P2
P3P7R3N7N3P8
R2R7M3T2
N8
L8
K2
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1D1B9B3
T8
T7T3
R8
P9
P1
N9
N2
M7
M2
M1
L7
L3
L2
K8K7
K3
H3
G2
F9
F7
E7E2
B7
D3
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T7T3
T2
R8
R7
R3
R2
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G2
F9
F7
F3
E7E2
D7
C3B8
B7A7
A3
J8 G7
AG39
A7
H8
M8AK37
AG34AD31
AN39AK39
AD39AK38
AP39
G3
C2C7
C8
C2C8
AE32AL36
AN31
AT30
AM35
AJ34
AT31AT32
AP30
AN29
AP32
AK27
P9
H2H7
J3
B8A3AJ36
AT33
AW32
AR30
C7C3
D3D7
F3
J7
GND
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
PS_DDR_DQ66PS_DDR_DQ65PS_DDR_DQ64PS_DDR_DQ63PS_DDR_DQ62PS_DDR_DQ61PS_DDR_DQ60PS_DDR_DQ59PS_DDR_DQ58PS_DDR_DQ57PS_DDR_DQ56PS_DDR_DQ55PS_DDR_DQ54PS_DDR_DQ53PS_DDR_DQ52PS_DDR_DQ51PS_DDR_DQ50PS_DDR_DQ49PS_DDR_DQ48PS_DDR_DQ47PS_DDR_DQ46PS_DDR_DQ45PS_DDR_DQ44PS_DDR_DQ43PS_DDR_DQ42PS_DDR_DQ41PS_DDR_DQ40PS_DDR_DQ39PS_DDR_DQ38PS_DDR_DQ37PS_DDR_DQ36PS_DDR_DQ35PS_DDR_DQ34PS_DDR_DQ33PS_DDR_DQ32PS_DDR_DQ31PS_DDR_DQ30PS_DDR_DQ29PS_DDR_DQ28PS_DDR_DQ27PS_DDR_DQ26PS_DDR_DQ25PS_DDR_DQ24PS_DDR_DQ23PS_DDR_DQ22PS_DDR_DQ21PS_DDR_DQ20PS_DDR_DQ19PS_DDR_DQ18PS_DDR_DQ17PS_DDR_DQ16PS_DDR_DQ15PS_DDR_DQ14PS_DDR_DQ13PS_DDR_DQ12PS_DDR_DQ11PS_DDR_DQ10PS_DDR_DQ9PS_DDR_DQ8PS_DDR_DQ7PS_DDR_DQ6PS_DDR_DQ5PS_DDR_DQ4PS_DDR_DQ3PS_DDR_DQ2PS_DDR_DQ1PS_DDR_DQ0
PS_DDR_ALERT_N
PS_DDR_ZQ
PS_DDR_DQS_P8PS_DDR_DQS_P7PS_DDR_DQS_P6PS_DDR_DQS_P5PS_DDR_DQS_P4PS_DDR_DQS_P3PS_DDR_DQS_P2PS_DDR_DQS_P1PS_DDR_DQS_P0PS_DDR_DQS_N8PS_DDR_DQS_N7PS_DDR_DQS_N6PS_DDR_DQS_N5PS_DDR_DQS_N4PS_DDR_DQS_N3PS_DDR_DQS_N2PS_DDR_DQS_N1PS_DDR_DQS_N0
PS_DDR_DQ71PS_DDR_DQ70PS_DDR_DQ69PS_DDR_DQ68PS_DDR_DQ67
PS_DDR_RAM_RST_NPS_DDR_PARITY
PS_DDR_ODT1PS_DDR_ODT0
PS_DDR_DM8PS_DDR_DM7PS_DDR_DM6PS_DDR_DM5PS_DDR_DM4PS_DDR_DM3PS_DDR_DM2PS_DDR_DM1PS_DDR_DM0
PS_DDR_CS_N1PS_DDR_CS_N0PS_DDR_CK_N1PS_DDR_CK_N0
PS_DDR_CKE1PS_DDR_CKE0
PS_DDR_CK1PS_DDR_CK0PS_DDR_BG1PS_DDR_BG0PS_DDR_BA1PS_DDR_BA0
PS_DDR_ACT_NPS_DDR_A17PS_DDR_A16PS_DDR_A15PS_DDR_A14PS_DDR_A13PS_DDR_A12PS_DDR_A11PS_DDR_A10
PS_DDR_A9PS_DDR_A8PS_DDR_A7PS_DDR_A6PS_DDR_A5PS_DDR_A4PS_DDR_A3PS_DDR_A2PS_DDR_A1PS_DDR_A0
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 9: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/9.jpg)
PS DDR 4GBYTE DDR4 WITH ECC
9 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.47UF0.47UF
0.47UF
0.47UF0.47UF
0.47UF0.47UF 0.47UF
0.47UF0.47UF
0.47UF 0.47UF
39.2
39.2
39.2
240240
240
499
499
499
0.068UF0.068UF 0.068UF
MT40A512M16LY-062E IT:E
MT40A512M16LY-062E IT:EMT40A512M16LY-062E IT:E
0.068UF
4.7UF
4.7UF 4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 0.1UF
0.068UF 0.068UF 0.068UF
0.068UF 0.068UF 0.068UF 0.068UF
0.068UF
0.068UF0.068UF
0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF
0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF
C108C99
C135
C142C137
C140C101 C111
C113C103
C97 C106
R422
R420
R421
R50R53
R51
R48
R49
R52
C107 C117
U5
U6U4
C127
C110
C131
C132C125C120
C133C126C121
C119
C118
C109
C100
C112C102
C105
C128
C129
C124
C122C116
C130C123
C115
C114
C104
C96
C98
C139
C150
C151
C149
C147C145
C152C148C146
C144
C143
C138
C134
C141C136
VREF_PS_DDR4
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
VREF_PS_DDR4
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ55_504PS_DDR4_DQ54_504PS_DDR4_DQ53_504
PS_DDR4_DQ51_504PS_DDR4_DQ50_504
PS_DDR4_DQ52_504
PS_DDR4_DQS6_504_P
PS_DDR4_DQ48_504PS_DDR4_DQ49_504
PS_DDR4_DQS6_504_N
PS_DDR4_DM6_504PS_DDR4_DM7_504
PS_DDR4_DQ63_504PS_DDR4_DQ62_504PS_DDR4_DQ61_504
PS_DDR4_DQ59_504PS_DDR4_DQ58_504
PS_DDR4_DQ60_504
PS_DDR4_DQ57_504
PS_DDR4_DQS7_504_PPS_DDR4_DQS7_504_N
PS_DDR4_DQ56_504
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ70_504PS_DDR4_DQ69_504
PS_DDR4_DQ67_504PS_DDR4_DQ66_504
PS_DDR4_DQ68_504
PS_DDR4_DQS8_504_P
PS_DDR4_DQ64_504PS_DDR4_DQ65_504
PS_DDR4_DQS8_504_N
PS_DDR4_DM8_504
PS_DDR4_DQ71_504
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
VREF_PS_DDR4
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ39_504PS_DDR4_DQ38_504PS_DDR4_DQ37_504
PS_DDR4_DQ35_504PS_DDR4_DQ34_504
PS_DDR4_DQ36_504
PS_DDR4_DQS4_504_P
PS_DDR4_DQ32_504PS_DDR4_DQ33_504
PS_DDR4_DQS4_504_N
PS_DDR4_DM4_504PS_DDR4_DM5_504
PS_DDR4_DQ47_504PS_DDR4_DQ46_504PS_DDR4_DQ45_504
PS_DDR4_DQ43_504PS_DDR4_DQ42_504
PS_DDR4_DQ44_504
PS_DDR4_DQ41_504
PS_DDR4_DQS5_504_PPS_DDR4_DQS5_504_N
PS_DDR4_DQ40_504
1V2_PS_DDR4
1V2_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4 2V5_VP_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
2V5_VP_DDR4
1V2_PS_DDR41V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
G3
T7
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G3
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G3
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 10: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/10.jpg)
PS DDR TERMINATION
10 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
49.9
39.239.239.239.239.239.2
1K
39.2
36.536.5
39.2 39.2 39.2 39.239.239.239.2 39.239.239.239.239.239.239.239.239.239.239.2
14412131912
3
4.7UF 4.7UF 4.7UF
0.01UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
R148
R159R158R157R156R155R154R153
R151R147
R172 R173 R174 R175R171R170R152 R169R168R167R166R165R164R163R162R161R160R150
C428C427C426C425C423C422C421C420C419
C424
R149
PS_DDR4_CK0_504_N
1V2_PS_DDR4
PS_DDR4_RESET#
PS_DDR4_A10_504PS_DDR4_A9_504PS_DDR4_A8_504
PS_DDR4_A15_504
PS_DDR4_A13_504
PS_DDR4_A11_504
PS_DDR4_A6_504
PS_DDR4_A4_504
VTT_PS_DDR4
1V2_PS_DDR4
PS_DDR4_ALERT#
PS_DDR4_CS0#PS_DDR4_ODT0PS_DDR4_PARITYPS_DDR4_ACT#
VTT_PS_DDR4
PS_DDR4_CKE0PS_DDR4_BG0_504PS_DDR4_BA1_504
PS_DDR4_A16_504
PS_DDR4_A14_504
PS_DDR4_A12_504
PS_DDR4_A5_504
PS_DDR4_A3_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A7_504
PS_DDR4_A2_504
PS_DDR4_BA0_504
PS_DDR4_CK0_504_P
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 11: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/11.jpg)
PL DDR 2GBYTE DDR4, X32
11 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.47UF 0.47UF 0.47UF 0.47UF
0.47UF 0.47UF0.47UF 0.47UF
240
240
499
499MT40A512M16LY-062E IT:E
0.068UF
0.1UF
MT40A512M16LY-062E IT:E
0.1UF 4.7UF0.1UF
4.7UF4.7UF
4.7UF
4.7UF
4.7UF
0.1UF
0.068UF 0.068UF 0.068UF 0.068UF 0.068UF0.068UF0.068UF
0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF
0.068UF0.068UF0.068UF0.068UF
0.068UF0.068UF
C156 C162 C178 C182
C159 C180C154 C176
R57
R56
R55
R54
U31
U30
C155 C161
C160
C165
C166 C168 C174
C170 C173
C177 C181
C185
C186 C188 C190
C164
C163
C153
C171C169
C172C167C158
C157
C189C187C184C179
C183
C175
PL_DDR4_0_A13_69
PL_DDR4_0_PARITY_69
PL_DDR4_0_A11_69
PL_DDR4_0_A7_69
PL_DDR4_0_A9_69
PL_DDR4_0_A2_69
PL_DDR4_0_A8_69
PL_DDR4_0_ALERT#_70
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A6_69
PL_DDR4_0_RST#_70
PL_DDR4_0_BA1_69
PL_DDR4_0_A3_69PL_DDR4_0_A4_69
PL_DDR4_0_BA0_69
PL_DDR4_0_A15_69
PL_DDR4_0_A12_69
PL_DDR4_0_A10_69
PL_DDR4_0_BG0_69
VREF_PL_DDR4
PL_DDR4_0_A16_69
PL_DDR4_0_CS#_69
PL_DDR4_0_ACT#_69
PL_DDR4_0_A14_69
PL_DDR4_0_CK_69_NPL_DDR4_0_CK_69_P
PL_DDR4_0_ODT_69
PL_DDR4_0_CKE_69
PL_DDR4_0_DQ7_69PL_DDR4_0_DQ6_69PL_DDR4_0_DQ5_69
PL_DDR4_0_DQ3_69PL_DDR4_0_DQ2_69
PL_DDR4_0_DQ4_69
PL_DDR4_0_DQS0_69_P
PL_DDR4_0_DQ0_69PL_DDR4_0_DQ1_69
PL_DDR4_0_DQS0_69_N
PL_DDR4_0_DM0_69PL_DDR4_0_DM1_69
PL_DDR4_0_DQ15_69PL_DDR4_0_DQ14_69PL_DDR4_0_DQ13_69
PL_DDR4_0_DQ11_69PL_DDR4_0_DQ10_69
PL_DDR4_0_DQ12_69
PL_DDR4_0_DQ9_69
PL_DDR4_0_DQS1_69_PPL_DDR4_0_DQS1_69_N
PL_DDR4_0_DQ8_69
2V5_VP_DDR4
PL_DDR4_0_DQ26_70PL_DDR4_0_DQ27_70PL_DDR4_0_DQ28_70
PL_DDR4_0_DQ25_70PL_DDR4_0_DQ24_70PL_DDR4_0_DQ23_70PL_DDR4_0_DQ22_70PL_DDR4_0_DQ21_70
1V2_PL_DDR4PL_DDR4_0_DQ16_70PL_DDR4_0_DQ17_70PL_DDR4_0_DQ18_70
PL_DDR4_0_DQ20_70PL_DDR4_0_DQ19_70
PL_DDR4_0_DQ31_70
PL_DDR4_0_DQ29_70PL_DDR4_0_DQ30_70
PL_DDR4_0_DQS2_70_P
1V2_PL_DDR4
1V2_PL_DDR4
PL_DDR4_0_DQS2_70_NPL_DDR4_0_A15_69PL_DDR4_0_A16_69
PL_DDR4_0_CK_69_P
PL_DDR4_0_A13_69
PL_DDR4_0_PARITY_69
PL_DDR4_0_A11_69
PL_DDR4_0_A7_69
PL_DDR4_0_A9_69
PL_DDR4_0_A2_69
PL_DDR4_0_A8_69
PL_DDR4_0_ALERT#_70
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A6_69
PL_DDR4_0_RST#_70
PL_DDR4_0_BA1_69
PL_DDR4_0_A3_69PL_DDR4_0_A4_69
PL_DDR4_0_BA0_69
PL_DDR4_0_A12_69
PL_DDR4_0_A10_69
PL_DDR4_0_BG0_69
VREF_PL_DDR4
PL_DDR4_0_CS#_69
PL_DDR4_0_ACT#_69
PL_DDR4_0_A14_69
PL_DDR4_0_CK_69_N
PL_DDR4_0_ODT_69
PL_DDR4_0_CKE_69PL_DDR4_0_DM2_70PL_DDR4_0_DM3_70
PL_DDR4_0_DQS3_70_PPL_DDR4_0_DQS3_70_N
VREF_PL_DDR4
VREF_PL_DDR41V2_PL_DDR42V5_VP_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
F1
A7B7
B8
C8D3
E2E7
F9
H2
H3H7
K2
K3
K7K8
L3
L7
L8
M1
M2
M3
M7
M8
N2
N3N7
N8
N9
P1
P2
P3P7
P8
P9
R2
R3
R7
R8
T2
T3T7
B3 B9 D1 G7
L1 R1 T9A1 A9 D9 F2 G1
G9
J2 J8B1 R9
B2 E1 E9 G8 K1 K9 M9 N1 T1A2 A8 C9 D2 D8 E3 E8 H1 H9
T8
L2
A3J7J3H8
D7
C2
C3
L9
F7
J9J1C1 F8
G2
C7
F3G3
F7
C2
B9F2
C3
J7
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8D9C1A9A1 T9R1L9L1J9J1G7
D1B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J3H8
H7H3
H2
G3
G2
F9
F3
E7E2
D7D3C8
C7
B8
B7A7
A3
GNDGND
GND GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 12: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/12.jpg)
2GBYTE DDR4, X32PL DDR
12 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.47UF0.47UF
0.47UF0.47UF
0.47UF0.47UF
0.47UF0.47UF
240
240
499
499
0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF 0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF0.068UF
0.068UF
0.1UF0.1UF
0.1UF 0.1UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
MT40A512M16LY-062E IT:E
0.068UF0.068UF
MT40A512M16LY-062E IT:E
C680C676
C682C678
C659C654
C662C656
R222
R221
R220
R219
C655 C661
C660
C666
C663
C668
C685
C674
C670 C673
C677 C681 C686 C688 C690
C683
C653 C658
C657
C664 C667 C672
C669 C671
C675 C679 C684 C687 C689
U41
U42
C665PL_DDR4_1_DQ24_71PL_DDR4_1_DQ25_71PL_DDR4_1_DQ26_71PL_DDR4_1_DQ27_71PL_DDR4_1_DQ28_71PL_DDR4_1_DQ29_71PL_DDR4_1_DQ30_71
PL_DDR4_1_DQ23_71
PL_DDR4_1_DQ21_71PL_DDR4_1_DQ22_71
PL_DDR4_1_DQ20_71PL_DDR4_1_DQ19_71PL_DDR4_1_DQ18_71PL_DDR4_1_DQ17_71PL_DDR4_1_DQ16_71
PL_DDR4_1_DQ0_70
PL_DDR4_1_DQ3_70PL_DDR4_1_DQ2_70
PL_DDR4_1_DQ5_70
PL_DDR4_1_DQ1_70
PL_DDR4_1_DQ4_70
PL_DDR4_1_DQ14_70
PL_DDR4_1_DQ10_70PL_DDR4_1_DQ9_70PL_DDR4_1_DQ8_70PL_DDR4_1_DQ7_70
PL_DDR4_1_DQ13_70PL_DDR4_1_DQ12_70PL_DDR4_1_DQ11_70
PL_DDR4_1_DQ6_70
PL_DDR4_1_DQ15_70
PL_DDR4_1_DQS0_70_N
PL_DDR4_1_DQS1_70_PPL_DDR4_1_DQS1_70_N
PL_DDR4_1_DM0_70PL_DDR4_1_DM1_70
PL_DDR4_1_DQS0_70_P
2V5_VP_DDR4
PL_DDR4_1_DQ31_71
PL_DDR4_1_DQS2_71_P
1V2_PL_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
VREF_PL_DDR4
VREF_PL_DDR4
PL_DDR4_1_DQS3_71_N
PL_DDR4_1_DM3_71PL_DDR4_1_DM2_71
PL_DDR4_1_ODT_71
PL_DDR4_1_A14_71
PL_DDR4_1_ACT#_71
PL_DDR4_1_CS#_71
VREF_PL_DDR4
PL_DDR4_1_BG0_71
PL_DDR4_1_A10_71
PL_DDR4_1_A12_71
PL_DDR4_1_BA0_71
PL_DDR4_1_A4_71PL_DDR4_1_A3_71
PL_DDR4_1_BA1_71
PL_DDR4_1_RST#_70
PL_DDR4_1_A6_71
PL_DDR4_1_A0_71PL_DDR4_1_A1_71
PL_DDR4_1_A5_71
PL_DDR4_1_A8_71
PL_DDR4_1_A2_71
PL_DDR4_1_A9_71
PL_DDR4_1_A7_71
PL_DDR4_1_A11_71
PL_DDR4_1_A13_71
PL_DDR4_1_ACT#_71
PL_DDR4_1_BG0_71
PL_DDR4_1_A14_71PL_DDR4_1_A16_71PL_DDR4_1_A15_71
PL_DDR4_1_A15_71PL_DDR4_1_A16_71
PL_DDR4_1_A3_71
PL_DDR4_1_A0_71PL_DDR4_1_A1_71PL_DDR4_1_A2_71
PL_DDR4_1_BA0_71
PL_DDR4_1_A13_71PL_DDR4_1_A12_71PL_DDR4_1_A11_71PL_DDR4_1_A10_71PL_DDR4_1_A9_71PL_DDR4_1_A8_71PL_DDR4_1_A7_71
PL_DDR4_1_A4_71PL_DDR4_1_A5_71PL_DDR4_1_A6_71
PL_DDR4_1_ODT_71PL_DDR4_1_RST#_70
PL_DDR4_1_PARITY_71PL_DDR4_1_ALERT#_70
PL_DDR4_1_ALERT#_70PL_DDR4_1_PARITY_71
PL_DDR4_1_CS#_71
1V2_PL_DDR4
VREF_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DQS2_71_N
PL_DDR4_1_CKE_71PL_DDR4_1_CK_71_NPL_DDR4_1_CK_71_P
PL_DDR4_1_CKE_71PL_DDR4_1_CK_71_NPL_DDR4_1_CK_71_P
PL_DDR4_1_BA1_71
PL_DDR4_1_DQS3_71_P
GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 13: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/13.jpg)
PL DDR TERMINATION
13 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
36.5
0.01UF
39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2
1K
4.7K
39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2
1K
39.2 39.2 39.2 39.2 39.2
36.5
39.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.2
36.536.5
4.7K
4.7UF 4.7UF4.7UF 4.7UF4.7UF4.7UF
0.01UF
0.1UF 0.1UF0.1UF 0.1UF 0.1UF 0.1UF0.1UF0.1UF0.1UF 0.1UF 0.1UF 0.1UF
R276R274
C709
R275R273
R224 R226 R228 R230 R232 R234 R236 R238 R240 R242 R244 R246
R280
R279
R248 R250 R252 R254 R256 R258 R260 R262
R278
R264 R266 R268 R270 R272
R271R269R267R265R263R261R259R257R255R253R251R249R247R245R243R241R239R237R235R233R231R229R227R225R223
R277
C710
C700 C704 C705 C706 C707 C708C703C702C701C693 C699C698C697C696C695C694C692C691
PL_DDR4_1_CK_71_P
1V2_PL_DDR4
PL_DDR4_1_A0_71
PL_DDR4_0_BG0_69PL_DDR4_0_BA1_69
PL_DDR4_0_A15_69PL_DDR4_0_BA0_69
PL_DDR4_0_A16_69
PL_DDR4_1_A15_71
PL_DDR4_0_A14_69
PL_DDR4_1_A16_71PL_DDR4_1_A14_71PL_DDR4_1_A13_71PL_DDR4_1_A12_71
PL_DDR4_1_BA0_71
PL_DDR4_1_CKE_71PL_DDR4_1_BG0_71PL_DDR4_1_BA1_71
PL_DDR4_1_ACT#_71PL_DDR4_1_PARITY_71PL_DDR4_1_ODT_71PL_DDR4_1_CS#_71
PL_DDR4_1_A9_71PL_DDR4_1_A8_71
PL_DDR4_1_ALERT#_70
PL_DDR4_1_CK_71_N
PL_DDR4_1_RST#_70
PL_DDR4_0_ALERT#_70
PL_DDR4_0_CK_69_PPL_DDR4_0_CK_69_N
PL_DDR4_0_PARITY_69PL_DDR4_0_ODT_69
PL_DDR4_0_ACT#_69
1V2_PL_DDR4
PL_DDR4_0_RST#_70
VTT_PL_DDR4VTT_PL_DDR4
PL_DDR4_1_A5_71PL_DDR4_1_A4_71
PL_DDR4_1_A1_71
PL_DDR4_1_A11_71
PL_DDR4_1_A6_71
PL_DDR4_1_A3_71PL_DDR4_1_A2_71
PL_DDR4_1_A10_71
PL_DDR4_1_A7_71
PL_DDR4_0_CS#_69
PL_DDR4_0_CKE_69
PL_DDR4_0_A12_69
PL_DDR4_0_A3_69PL_DDR4_0_A2_69
PL_DDR4_0_A0_69
PL_DDR4_0_A4_69
PL_DDR4_0_A1_69
PL_DDR4_0_A5_69PL_DDR4_0_A6_69
PL_DDR4_0_A8_69PL_DDR4_0_A9_69
PL_DDR4_0_A7_69
PL_DDR4_0_A10_69PL_DDR4_0_A11_69
PL_DDR4_0_A13_69
VTT_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
VTT_PL_DDR4
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 14: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/14.jpg)
VCCO 0.95V...1.9
VCCO 0.95V...1.9
PL HP BANK 64, 65, 66, 67
UG 583 PLACE NEAR CONNECTOR P1
14 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
XCZU11EG-1FFVF1517I
4.7UF 100UF 100UF 4.7UF 100UF 4.7UF
0.1UF499
100UF4.7UF
R0402L
499
240
240
100UF 100UF 100UF
0.1UF
R0402L
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
100UF
R0402L
2K 2K
R0402L
C292 C293 C294 C298 C299 C301
TP129TP128TP127TP126
C1111R289
R458
R524
TP125TP124TP104
C295 C302 C303
C1112
U21U21
U21
C297
R525
U21
C300C296
R522 R523
SYNCOUTB1_B_PSYNCOUTB1_B_N
RX1_ENABLE_B
GPIO_9_AGPIO_10_A
SPI_CLK
1V8VCCO_67
GPIO_8_A
SPI_CSN_ADRV9009_B
VREF_65
1V8
GPIO_2_HMC7044
TX1_ENABLE_ATX2_ENABLE_AJESD_SYSREF_FPGA_A_PJESD_SYSREF_FPGA_A_N
TX1_ENABLE_B
GPIO_0_B
IO_L14N_T2L_N3_GC_64IO_L13N_T2L_N1_GC_QBC_65
IO_L10N_T1U_N7_QBC_AD4N_65IO_L9P_T1L_N4_AD12P_65
IO_L8N_T1L_N3_AD5N_65IO_L7P_T1L_N0_QBC_AD13P_65
IO_L6P_T0U_N10_AD6P_65
IO_L13P_T2L_N0_GC_QBC_65
SPI_CSN_HMC7044
CORE_CLK_B_NCORE_CLK_B_P
SPI_MOSI
SPI_CSN_ADRV9009_A
CORE_CLK_A_P
GPIO_7_A
SYNCINB1_A_N
1V8
VCCO_65
VCCO_67
VREF_67
IO_L21P_T3L_N4_AD8P_65
IO_T1U_N12_SMBALERT_65
IO_T3U_N12_PERSTN0_65
IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
IO_L22N_T3U_N7_DBC_AD0N_65
IO_L3P_T0L_N4_AD15P_65
IO_L7N_T1L_N1_QBC_AD13N_65
IO_L21P_T3L_N4_AD8P_67
IO_L23P_T3U_N8_67IO_L23N_T3U_N9_67
GPIO_6_A
CORE_CLK_A_N
GPIO_1_A
GPIO_3_A
GPIO_4_AGPIO_5_AGPIO_2_A
IO_L8N_T1L_N3_AD5N_67
IO_L7N_T1L_N1_QBC_AD13N_67
IO_L3N_T0L_N5_AD15N_67
GPIO_11_A
IO_L4P_T0U_N6_DBC_AD7P_65
IO_L8P_T1L_N2_AD5P_65
IO_L4P_T0U_N6_DBC_AD7P_67
IO_L10N_T1U_N7_QBC_AD4N_67
IO_L15N_T2L_N5_AD11N_67
IO_L2P_T0L_N2_67
IO_L6N_T0U_N11_AD6N_67IO_L5P_T0U_N8_AD14P_67IO_L5N_T0U_N9_AD14N_67
IO_L20P_T3L_N2_AD1P_67IO_L21N_T3L_N5_AD8N_67
IO_L19N_T3L_N1_DBC_AD9N_67IO_L18P_T2U_N10_AD2P_67IO_L18N_T2U_N11_AD2N_67IO_L17P_T2U_N8_AD10P_67
IO_T3U_N12_67
IO_L10P_T1U_N6_QBC_AD4P_67IO_L11N_T1U_N9_GC_67
IO_L7P_T1L_N0_QBC_AD13P_67
IO_L6P_T0U_N10_AD6P_67
IO_L4N_T0U_N7_DBC_AD7N_67IO_L3P_T0L_N4_AD15P_67
IO_L22P_T3U_N6_DBC_AD0P_67IO_L22N_T3U_N7_DBC_AD0N_67
IO_T0U_N12_VRP_67IO_L24P_T3U_N10_67IO_L24N_T3U_N11_67
IO_L16N_T2U_N7_QBC_AD3N_67
IO_L14N_T2L_N3_GC_67
IO_L16P_T2U_N6_QBC_AD3P_67
IO_L14P_T2L_N2_GC_67
IO_L15P_T2L_N4_AD11P_67
IO_L17N_T2U_N9_AD10N_67
IO_T2U_N12_67IO_T1U_N12_67
IO_L13P_T2L_N0_GC_QBC_67IO_L13N_T2L_N1_GC_QBC_67IO_L12P_T1U_N10_GC_67
GPIO_17_BGPIO_16_B
SYNCOUTB0_A_N
RX1_ENABLE_A
RESETB_A
RX2_ENABLE_A
SYNCOUTB1_A_PSYNCINB0_A_N
GPINT_A
IO_L14P_T2L_N2_GC_65IO_L15N_T2L_N5_AD11N_65IO_L15P_T2L_N4_AD11P_65IO_L16N_T2U_N7_QBC_AD3N_65IO_L16P_T2U_N6_QBC_AD3P_65IO_L17N_T2U_N9_AD10N_65IO_L17P_T2U_N8_AD10P_65IO_L18N_T2U_N11_AD2N_65IO_L18P_T2U_N10_AD2P_65IO_L19N_T3L_N1_DBC_AD9N_65IO_L19P_T3L_N0_DBC_AD9P_65
IO_L20P_T3L_N2_AD1P_65IO_L21N_T3L_N5_AD8N_65
IO_L22P_T3U_N6_DBC_AD0P_65
IO_L23P_T3U_N8_I2C_SCLK_65
IO_L24P_T3U_N10_65IO_L2P_T0L_N2_65IO_L3N_T0L_N5_AD15N_65
IO_L4N_T0U_N7_DBC_AD7N_65
IO_L5N_T0U_N9_AD14N_65IO_L5P_T0U_N8_AD14P_65IO_L6N_T0U_N11_AD6N_65
IO_L9N_T1L_N5_AD12N_65
IO_T2U_N12_65
IO_T0U_N12_VRP_65
IO_L12P_T1U_N10_GC_65
SYNCOUTB0_A_P
IO_L12N_T1U_N11_GC_67IO_L11P_T1U_N8_GC_67
TEST_B
SYNCINB0_B_P
SYNCOUTB0_B_P
SYNCINB0_B_N
IO_L10P_T1U_N6_QBC_AD4P_65IO_L11N_T1U_N9_GC_65IO_L11P_T1U_N8_GC_65IO_L12N_T1U_N11_GC_65
SYNCINB0_A_P
SPI_MOSISPI_MISO
SYNCOUTB0_B_N
SYNCINB1_A_PI2C0_SDAI2C0_SCL
GPIO_14_BGPIO_13_B
SYNCOUTB1_A_N
GPIO_1_B
TX2_ENABLE_B
SPI_CSN_HMC7044
GPIO_12_BGPIO_11_B
SPI_CSN_ADRV9009_B
IO_L14P_T2L_N2_GC_64
1V8
SPI_MOSISPI_CLKOSCOUT1_NOSCOUT1_P
1V8
SPI_MISO
GPIO_12_A
GPIO_13_AGPIO_14_A
SPI_MISO
TEST_A
GPIO_0_A
IO_L1N_T0L_N1_DBC_67
GPIO_15_A
IO_L20P_T3L_N2_AD1P_66
IO_L20N_T3L_N3_AD1N_67IO_L19P_T3L_N0_DBC_AD9P_67
IO_L14N_T2L_N3_GC_65
IO_L20N_T3L_N3_AD1N_65
IO_L24N_T3U_N11_65
IO_L2N_T0L_N3_65
GPIO_1_HMC7044
GPIO_3_HMC7044GPIO_4_HMC7044RESET_HMC7044SYNC_HMC7044_FPGA
IO_L12N_T1U_N11_GC_64IO_L12P_T1U_N10_GC_64IO_L13P_T2L_N0_GC_QBC_64IO_L13N_T2L_N1_GC_QBC_64
IO_L1N_T0L_N1_DBC_65IO_L1P_T0L_N0_DBC_65
IO_L1P_T0L_N0_DBC_67IO_L2N_T0L_N3_67
GPINT_BGPIO_18_B
GPIO_18_A
GPIO_9_BGPIO_10_BGPIO_15_BGPIO_8_BGPIO_6_BGPIO_7_BGPIO_4_BGPIO_5_BGPIO_2_BGPIO_3_B RESETB_B
RX2_ENABLE_B
SYNCINB1_B_NSYNCINB1_B_P
SPI_CSN_ADRV9009_A
JESD_SYSREF_FPGA_B_NJESD_SYSREF_FPGA_B_P
IO_L8P_T1L_N2_AD5P_67
IO_L19P_T3L_N0_DBC_AD9P_66
IO_L9N_T1L_N5_AD12N_67IO_L9P_T1L_N4_AD12P_67
GPIO_16_AGPIO_17_AIO_L19N_T3L_N1_DBC_AD9N_66
VCCO_65
AT21
AG16
AT14
AN15
AK16
AH18AR17
AR5
AK11
AW5
AJ21
AP3AM11
AN10
AR8
AT12AR12
AV6
AT18
AV13
AR18
AK20
AJ26
AU21
AL19
AP18
AG24
AP23
AL24
AH23AL26AT27AU23AK22AK23AH24AJ24AH22AJ22AJ25
AG22AG23AK24AK25AM23AM24AL25AM25AL22AL23AM26AN26AN22AP22AN23
AN24AP24AR24AP25AP26AR23AT23AR25
AR22AT22AT26
AV23AV24AU24AU25AW24AW25AV26AV27
AW22AW26AW27
AT9
AR6
AP4
AU8
AT5AT8AT7AV8AV7AU6
AV4AW4AU5AU4
AW6AV9AW9AP2AP1AR3AT3AT1AU1AR2AT2AV2AW2AU3AV3
AH17AL12AT15AU15AJ15
AH14AJ14AH16AJ16AJ12AK12AJ17AK17AK14AK13AL16AM16AL13AM13AM15AN14AL15AM14AN16AP16AN13
AN12AP15AR15AP14AR14AR13AT13AP12
AT11AT10AU10AV12AW12AU14AU13AV14
AW11AW10AW15AW14AU11AV11
AG21
AJ19
AJ20AG20AG19
AT20
AR20
AN17AP17AN21
AM21AM19AM18
AV19AV16AW16
AW19AV17AW17AV21AW21AU18AV18
AK18AK19
AT17
AL20
AP10AL11
AR19AP19
AP7AR7
AR4AU9
AP8AP5
AK10
AP11
AW7
AT6
AL10
AV22
AU22
AK15
AM20AU16
AT16
AN11
AP6
AL21AL17
AN18
AU19
AH21AH19
AW20
AN19
AP21
AU17
AG18
AU20AL18
AU26
AT25
AP9AR9AR10AM10
AP20
GND
GND
GND
GND
GND
GND
GND
VREF
_67
VCCO
_67
VCCO
_67
VCCO
_67
IO_T3U_N12_67IO_T2U_N12_67IO_T1U_N12_67
IO_T0U_N12_VRP_67
IO_L9P_T1L_N4_AD12P_67IO_L9N_T1L_N5_AD12N_67IO_L8P_T1L_N2_AD5P_67IO_L8N_T1L_N3_AD5N_67IO_L7P_T1L_N0_QBC_AD13P_67IO_L7N_T1L_N1_QBC_AD13N_67IO_L6P_T0U_N10_AD6P_67IO_L6N_T0U_N11_AD6N_67IO_L5P_T0U_N8_AD14P_67IO_L5N_T0U_N9_AD14N_67IO_L4P_T0U_N6_DBC_AD7P_67IO_L4N_T0U_N7_DBC_AD7N_67IO_L3P_T0L_N4_AD15P_67IO_L3N_T0L_N5_AD15N_67IO_L2P_T0L_N2_67IO_L2N_T0L_N3_67
IO_L24P_T3U_N10_67IO_L24N_T3U_N11_67
IO_L23P_T3U_N8_67IO_L23N_T3U_N9_67
IO_L22P_T3U_N6_DBC_AD0P_67IO_L22N_T3U_N7_DBC_AD0N_67
IO_L21P_T3L_N4_AD8P_67IO_L21N_T3L_N5_AD8N_67IO_L20P_T3L_N2_AD1P_67IO_L20N_T3L_N3_AD1N_67
IO_L1P_T0L_N0_DBC_67IO_L1N_T0L_N1_DBC_67
IO_L19P_T3L_N0_DBC_AD9P_67IO_L19N_T3L_N1_DBC_AD9N_67
IO_L18P_T2U_N10_AD2P_67IO_L18N_T2U_N11_AD2N_67IO_L17P_T2U_N8_AD10P_67IO_L17N_T2U_N9_AD10N_67
IO_L16P_T2U_N6_QBC_AD3P_67IO_L16N_T2U_N7_QBC_AD3N_67
IO_L15P_T2L_N4_AD11P_67IO_L15N_T2L_N5_AD11N_67
IO_L14P_T2L_N2_GC_67IO_L14N_T2L_N3_GC_67IO_L13P_T2L_N0_GC_QBC_67
IO_L13N_T2L_N1_GC_QBC_67IO_L12P_T1U_N10_GC_67IO_L12N_T1U_N11_GC_67IO_L11P_T1U_N8_GC_67IO_L11N_T1U_N9_GC_67IO_L10P_T1U_N6_QBC_AD4P_67IO_L10N_T1U_N7_QBC_AD4N_67
VREF
_66
VCCO
_66
VCCO
_66
VCCO
_66
IO_T3U_N12_66IO_T2U_N12_66IO_T1U_N12_66
IO_T0U_N12_VRP_66
IO_L9P_T1L_N4_AD12P_66IO_L9N_T1L_N5_AD12N_66IO_L8P_T1L_N2_AD5P_66IO_L8N_T1L_N3_AD5N_66IO_L7P_T1L_N0_QBC_AD13P_66IO_L7N_T1L_N1_QBC_AD13N_66IO_L6P_T0U_N10_AD6P_66IO_L6N_T0U_N11_AD6N_66IO_L5P_T0U_N8_AD14P_66IO_L5N_T0U_N9_AD14N_66IO_L4P_T0U_N6_DBC_AD7P_66IO_L4N_T0U_N7_DBC_AD7N_66IO_L3P_T0L_N4_AD15P_66IO_L3N_T0L_N5_AD15N_66IO_L2P_T0L_N2_66IO_L2N_T0L_N3_66
IO_L24P_T3U_N10_66IO_L24N_T3U_N11_66
IO_L23P_T3U_N8_66IO_L23N_T3U_N9_66
IO_L22P_T3U_N6_DBC_AD0P_66IO_L22N_T3U_N7_DBC_AD0N_66
IO_L21P_T3L_N4_AD8P_66IO_L21N_T3L_N5_AD8N_66IO_L20P_T3L_N2_AD1P_66IO_L20N_T3L_N3_AD1N_66
IO_L1P_T0L_N0_DBC_66IO_L1N_T0L_N1_DBC_66
IO_L19P_T3L_N0_DBC_AD9P_66IO_L19N_T3L_N1_DBC_AD9N_66
IO_L18P_T2U_N10_AD2P_66IO_L18N_T2U_N11_AD2N_66IO_L17P_T2U_N8_AD10P_66IO_L17N_T2U_N9_AD10N_66
IO_L16P_T2U_N6_QBC_AD3P_66IO_L16N_T2U_N7_QBC_AD3N_66
IO_L15P_T2L_N4_AD11P_66IO_L15N_T2L_N5_AD11N_66
IO_L14P_T2L_N2_GC_66IO_L14N_T2L_N3_GC_66IO_L13P_T2L_N0_GC_QBC_66
IO_L13N_T2L_N1_GC_QBC_66IO_L12P_T1U_N10_GC_66IO_L12N_T1U_N11_GC_66IO_L11P_T1U_N8_GC_66IO_L11N_T1U_N9_GC_66IO_L10P_T1U_N6_QBC_AD4P_66IO_L10N_T1U_N7_QBC_AD4N_66
VREF
_65
VCCO
_65
VCCO
_65
VCCO
_65
IO_T3U_N12_PERSTN0_65IO_T2U_N12_65
IO_T1U_N12_SMBALERT_65IO_T0U_N12_VRP_65
IO_L9P_T1L_N4_AD12P_65IO_L9N_T1L_N5_AD12N_65IO_L8P_T1L_N2_AD5P_65IO_L8N_T1L_N3_AD5N_65IO_L7P_T1L_N0_QBC_AD13P_65IO_L7N_T1L_N1_QBC_AD13N_65IO_L6P_T0U_N10_AD6P_65IO_L6N_T0U_N11_AD6N_65IO_L5P_T0U_N8_AD14P_65IO_L5N_T0U_N9_AD14N_65IO_L4P_T0U_N6_DBC_AD7P_65IO_L4N_T0U_N7_DBC_AD7N_65IO_L3P_T0L_N4_AD15P_65IO_L3N_T0L_N5_AD15N_65IO_L2P_T0L_N2_65IO_L2N_T0L_N3_65
IO_L24P_T3U_N10_65IO_L24N_T3U_N11_65
IO_L23P_T3U_N8_I2C_SCLK_65IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
IO_L22P_T3U_N6_DBC_AD0P_65IO_L22N_T3U_N7_DBC_AD0N_65
IO_L21P_T3L_N4_AD8P_65IO_L21N_T3L_N5_AD8N_65IO_L20P_T3L_N2_AD1P_65IO_L20N_T3L_N3_AD1N_65
IO_L1P_T0L_N0_DBC_65IO_L1N_T0L_N1_DBC_65
IO_L19P_T3L_N0_DBC_AD9P_65IO_L19N_T3L_N1_DBC_AD9N_65
IO_L18P_T2U_N10_AD2P_65IO_L18N_T2U_N11_AD2N_65IO_L17P_T2U_N8_AD10P_65IO_L17N_T2U_N9_AD10N_65
IO_L16P_T2U_N6_QBC_AD3P_65IO_L16N_T2U_N7_QBC_AD3N_65
IO_L15P_T2L_N4_AD11P_65IO_L15N_T2L_N5_AD11N_65
IO_L14P_T2L_N2_GC_65IO_L14N_T2L_N3_GC_65IO_L13P_T2L_N0_GC_QBC_65
IO_L13N_T2L_N1_GC_QBC_65IO_L12P_T1U_N10_GC_65IO_L12N_T1U_N11_GC_65IO_L11P_T1U_N8_GC_65IO_L11N_T1U_N9_GC_65IO_L10P_T1U_N6_QBC_AD4P_65IO_L10N_T1U_N7_QBC_AD4N_65
VREF
_64
VCCO
_64
VCCO
_64
VCCO
_64
IO_T3U_N12_64IO_T2U_N12_64IO_T1U_N12_64
IO_T0U_N12_VRP_64
IO_L9P_T1L_N4_AD12P_64IO_L9N_T1L_N5_AD12N_64IO_L8P_T1L_N2_AD5P_64IO_L8N_T1L_N3_AD5N_64IO_L7P_T1L_N0_QBC_AD13P_64IO_L7N_T1L_N1_QBC_AD13N_64IO_L6P_T0U_N10_AD6P_64IO_L6N_T0U_N11_AD6N_64IO_L5P_T0U_N8_AD14P_64IO_L5N_T0U_N9_AD14N_64IO_L4P_T0U_N6_DBC_AD7P_64IO_L4N_T0U_N7_DBC_AD7N_64IO_L3P_T0L_N4_AD15P_64IO_L3N_T0L_N5_AD15N_64IO_L2P_T0L_N2_64IO_L2N_T0L_N3_64
IO_L24P_T3U_N10_64IO_L24N_T3U_N11_64
IO_L23P_T3U_N8_64IO_L23N_T3U_N9_64
IO_L22P_T3U_N6_DBC_AD0P_64IO_L22N_T3U_N7_DBC_AD0N_64
IO_L21P_T3L_N4_AD8P_64IO_L21N_T3L_N5_AD8N_64IO_L20P_T3L_N2_AD1P_64IO_L20N_T3L_N3_AD1N_64
IO_L1P_T0L_N0_DBC_64IO_L1N_T0L_N1_DBC_64
IO_L19P_T3L_N0_DBC_AD9P_64IO_L19N_T3L_N1_DBC_AD9N_64
IO_L18P_T2U_N10_AD2P_64IO_L18N_T2U_N11_AD2N_64IO_L17P_T2U_N8_AD10P_64IO_L17N_T2U_N9_AD10N_64
IO_L16P_T2U_N6_QBC_AD3P_64IO_L16N_T2U_N7_QBC_AD3N_64
IO_L15P_T2L_N4_AD11P_64IO_L15N_T2L_N5_AD11N_64
IO_L14P_T2L_N2_GC_64IO_L14N_T2L_N3_GC_64IO_L13P_T2L_N0_GC_QBC_64
IO_L13N_T2L_N1_GC_QBC_64IO_L12P_T1U_N10_GC_64IO_L12N_T1U_N11_GC_64IO_L11P_T1U_N8_GC_64IO_L11N_T1U_N9_GC_64IO_L10P_T1U_N6_QBC_AD4P_64IO_L10N_T1U_N7_QBC_AD4N_64
GNDGNDGNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 15: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/15.jpg)
100OHM DIFFERENTIAL TRACES
BANK 71
PLACE DIRECTLY UNDERNEATH THE PAD PLACE DIRECTLY UNDERNEATH THE PAD
BANK 70
PLACE DIRECTLY UNDERNEATH THE PAD
BANK 69
VCCO 0.95V...1.9
PL HP BANK 68, 69, 70, 71
100OHM DIFFERENTIAL TRACES
BANK 68
PLACE NEAR ZYNQ
PLACE NEAR ZYNQ
15 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
DNI
0
DNI
0
0
DNI
0.1UF
XCZU11EG-1FFVF1517I
0.1UF
5
6
XCZU11EG-1FFVF1517I
100UF100UF 100UF
0.01UF 0.01UF
100UF4.7UF
XCZU11EG-1FFVF1517I
100UF
XCZU11EG-1FFVF1517I
0.1UF499
R0402L
499
R0402L
240240
240
100
100
0.01UF
100UF
0.01UF
4.7UF
0.01UF
4.7UF
7
100UF
0.01UF
100UF4.7UF
499
DNI
0.1UF
R0402L
R486
R487
R483
C360
U21U21
C437
C446C445C440C436C433C431
U21
C447
U21
C439 C449R482 R484
R485
R126 R128
R454
R456
R457
C430
C429
C432 C435
C434
C443
C438
C441
C444C442
C448
PL_DDR4_1_DQ14_70
PL_DDR4_1_DQ15_70PL_DDR4_1_DQ11_70
PL_DDR4_1_DQ9_70PL_DDR4_1_DQ13_70PL_DDR4_1_DQ12_70PL_DDR4_1_DQ10_70
PL_DDR4_0_DQS3_70_NPL_DDR4_0_DQ31_70
PL_DDR4_0_DQS3_70_PPL_DDR4_0_DQ25_70
PL_DDR4_0_DM0_69PL_DDR4_0_CS#_69PL_DDR4_0_CK_69_PPL_DDR4_0_CK_69_NPL_DDR4_0_CKIN_69_P
PL_DDR4_0_DQ26_70
PL_DDR4_1_DQ8_70
PL_DDR4_1_DM1_70
PL_DDR4_1_DQ6_70
PL_DDR4_1_DQS0_70_PPL_DDR4_1_DQS0_70_NPL_DDR4_0_DQ27_70
PL_DDR4_0_DQ29_70PL_DDR4_0_DQ24_70PL_DDR4_0_DQ28_70
PL_DDR4_0_DQ16_70
PL_DDR4_0_DM3_70
PL_DDR4_0_DQ18_70PL_DDR4_0_DQ21_70PL_DDR4_0_DQ17_70PL_DDR4_0_DQS2_70_PPL_DDR4_0_DQS2_70_NPL_DDR4_0_DQ23_70
PL_DDR4_0_DQ20_70
PL_DDR4_0_DQ4_69
PL_DDR4_0_CKIN_69_NPL_DDR4_0_BA1_69
PL_DDR4_0_A4_69PL_DDR4_0_A7_69PL_DDR4_0_A6_69PL_DDR4_0_A9_69
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A10_69PL_DDR4_0_A13_69PL_DDR4_0_A12_69PL_DDR4_0_A16_69PL_DDR4_0_A14_69PL_DDR4_0_BA0_69PL_DDR4_0_A15_69PL_DDR4_0_BG0_69
PL_DDR4_0_DQ12_69PL_DDR4_0_DQ9_69
PL_DDR4_0_DQS1_69_PPL_DDR4_0_DQS1_69_N
PL_DDR4_0_DQ6_69PL_DDR4_0_DQ2_69
PL_DDR4_0_DQ0_69
PL_DDR4_0_DQ1_69
PL_DDR4_0_DQS0_69_N
PL_DDR4_0_DQ3_69
PL_DDR4_0_DQS0_69_P
PL_DDR4_0_DQ5_69PL_DDR4_0_DQ7_69
PL_DDR4_0_DQ10_69PL_DDR4_0_DQ14_69PL_DDR4_0_DQ13_69PL_DDR4_0_DQ11_69
PL_DDR4_0_DQ15_69
PL_DDR4_0_DQ8_69
PL_DDR4_0_ACT#_69PL_DDR4_0_PARITY_69
PL_DDR4_0_ODT_69
VCCO_68
VREF_PL_DDR4
PL_DDR4_1_BA0_71
1V2_PL_DDR4
PL_DDR4_1_RST#_70PL_DDR4_1_ALERT#_70PL_DDR4_0_ALERT#_70
PL_DDR4_1_CKE_71PL_DDR4_1_A10_71PL_DDR4_1_ACT#_71
PL_DDR4_1_CK_71_PPL_DDR4_1_CK_71_NPL_DDR4_1_BG0_71PL_DDR4_1_PARITY_71
IO_L19N_T3L_N1_DBC_AD9N_68
PL_DDR4_0_A8_69
IO_L14N_T2L_N3_GC_68IO_L14P_T2L_N2_GC_68
PL_DDR4_0_CKIN_69_PPL_DDR4_0_CKIN_69_N
PL_DDR4_1_DQS1_70_PPL_DDR4_1_DQS1_70_N
IO_L20N_T3L_N3_AD1N_68IO_L20P_T3L_N2_AD1P_68IO_L21N_T3L_N5_AD8N_68IO_L21P_T3L_N4_AD8P_68IO_L22N_T3U_N7_DBC_AD0N_68
PL_DDR4_1_A16_71PL_DDR4_1_BA1_71
PL_DDR4_1_A15_71PL_DDR4_1_A13_71PL_DDR4_1_A14_71
PL_DDR4_0_A11_69
IO_L13P_T2L_N0_GC_QBC_68IO_L13N_T2L_N1_GC_QBC_68
PL_DDR4_1_A5_71
PL_DDR4_1_A8_71PL_DDR4_1_A9_71
PL_DDR4_1_A7_71PL_DDR4_1_A4_71
PL_DDR4_1_A3_71
PL_DDR4_1_A1_71
PL_DDR4_1_A2_71
PL_DDR4_1_A0_71
PL_DDR4_0_A3_69PL_DDR4_0_A2_69
PL_DDR4_0_CKE_69PL_DDR4_0_DM1_69
1V2_PL_DDR4
IO_L8N_T1L_N3_AD5N_68
IO_L6P_T0U_N10_AD6P_68
IO_L5P_T0U_N8_AD14P_68
IO_L7P_T1L_N0_QBC_AD13P_68
IO_L9N_T1L_N5_AD12N_68IO_L8P_T1L_N2_AD5P_68
IO_L10N_T1U_N7_QBC_AD4N_68
IO_L6N_T0U_N11_AD6N_68
IO_L1N_T0L_N1_DBC_68IO_L1P_T0L_N0_DBC_68
IO_L12N_T1U_N11_GC_68
IO_L10P_T1U_N6_QBC_AD4P_68
IO_T1U_N12_68
IO_L23N_T3U_N9_68IO_L22P_T3U_N6_DBC_AD0P_68
IO_L9P_T1L_N4_AD12P_68
IO_L4N_T0U_N7_DBC_AD7N_68IO_L3P_T0L_N4_AD15P_68
IO_L5N_T0U_N9_AD14N_68IO_L4P_T0U_N6_DBC_AD7P_68
IO_L7N_T1L_N1_QBC_AD13N_68
PL_DDR4_1_A11_71PL_DDR4_1_A12_71
PL_DDR4_1_A6_71
PL_DDR4_1_CKIN_71_P
IO_L18P_T2U_N10_AD2P_68
IO_L19P_T3L_N0_DBC_AD9P_68
IO_L15P_T2L_N4_AD11P_68
IO_L17P_T2U_N8_AD10P_68IO_L17N_T2U_N9_AD10N_68
IO_L16N_T2U_N7_QBC_AD3N_68
IO_L15N_T2L_N5_AD11N_68
IO_L16P_T2U_N6_QBC_AD3P_68
IO_L18N_T2U_N11_AD2N_68
PL_DDR4_1_DQ2_70
VCCO_68
PL_DDR4_1_DM2_71PL_DDR4_1_CS#_71
PL_DDR4_1_DQ16_71PL_DDR4_1_DQ20_71
PL_DDR4_1_DQ21_71
PL_DDR4_1_DQS2_71_NPL_DDR4_1_DQS2_71_P
PL_DDR4_1_DQ23_71
PL_DDR4_1_DQ19_71PL_DDR4_1_DQ17_71
PL_DDR4_1_DQ22_71PL_DDR4_1_DQ18_71
PL_DDR4_1_DQS3_71_NPL_DDR4_1_DQS3_71_P
PL_DDR4_1_CKIN_71_N
PL_DDR4_1_DQ27_71
PL_DDR4_1_DQ26_71
PL_DDR4_0_DQ22_70PL_DDR4_0_DM2_70PL_DDR4_0_RST#_70
IO_T3U_N12_68IO_T2U_N12_68
IO_T0U_N12_VRP_68IO_L24P_T3U_N10_68IO_L24N_T3U_N11_68IO_L23P_T3U_N8_68
VREF_68
IO_L3N_T0L_N5_AD15N_68IO_L2P_T0L_N2_68IO_L2N_T0L_N3_68
PL_DDR4_0_DQ19_70
IO_L11P_T1U_N8_GC_68IO_L11N_T1U_N9_GC_68
VREF_PL_DDR4
1V2_PL_DDR4
IO_L12P_T1U_N10_GC_68
VREF_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DM0_70
1V2_PL_DDR41V2_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DQ5_70PL_DDR4_1_DQ3_70PL_DDR4_1_DQ4_70
1V2_PL_DDR4
PL_DDR4_0_DQ30_70
PL_DDR4_1_DQ0_70PL_DDR4_1_DQ7_70
PL_DDR4_1_CKIN_71_PPL_DDR4_1_CKIN_71_N
PL_DDR4_1_DQ1_70
1V2_PL_DDR4
PL_DDR4_1_DQ31_71PL_DDR4_1_DQ29_71
PL_DDR4_1_DQ24_71PL_DDR4_1_DQ25_71
PL_DDR4_1_DQ30_71PL_DDR4_1_DQ28_71PL_DDR4_1_DM3_71PL_DDR4_1_ODT_71
E17G19
J19
B24C21
D24F22F21
C17
C19K15
C24
E30
K27J30D31C26M25L25
J26J27
F26H26H27G30G31H28H29
L22
K22
L26M26B30
C22
E33
G23H23
L23
A33D32
K24
D26
F30
J20E22C23N22N23L20K20
M20L21K23
N21M21J22H22J21H21J24H24G20G21G24G25
F23E23
F25E25E24D25B23
A25A26B21A21B25B26
A23
F19
C20
D20D19K18N17B20A20B16A16
A17
C16B19B18
C18
E20
F18
G18F17F16H19H18H17
J16H16K17J17
J15
L18M15L15L17L16N16M16
N18N14
M24
J28
F29
C30
L27L28
K25J25K29K30
G26
G28G29E27E28F27F28
D27D29D30E29
F31C27B28B29
C28C29A30A31A27A28
B31
J31
G32
E36
D33
B36C33
D37A37A38C34B35A35A36C37B38C38C39D36
C32B33B34E32
E34D34E35
D35
F36G35G36F32F33G33G34H31H32J32H33F37E37G38G39E39D39H36H37F38E38
H39
A32C36
J29K28
C31
A22
K19G16
D22D21
M14
A18
M18
H38H34
J18
N19
M19
F35
M23
J23
F24
C25
E18E19D16D17
F20
GND
GND
GNDGND
GND
GND
GND
GND
GNDGNDGND
GND
VREF
_71
VCCO
_71
VCCO
_71
VCCO
_71
IO_T3U_N12_71IO_T2U_N12_71IO_T1U_N12_71
IO_T0U_N12_VRP_71
IO_L9P_T1L_N4_AD12P_71IO_L9N_T1L_N5_AD12N_71IO_L8P_T1L_N2_AD5P_71IO_L8N_T1L_N3_AD5N_71IO_L7P_T1L_N0_QBC_AD13P_71IO_L7N_T1L_N1_QBC_AD13N_71IO_L6P_T0U_N10_AD6P_71IO_L6N_T0U_N11_AD6N_71IO_L5P_T0U_N8_AD14P_71IO_L5N_T0U_N9_AD14N_71IO_L4P_T0U_N6_DBC_AD7P_71IO_L4N_T0U_N7_DBC_AD7N_71IO_L3P_T0L_N4_AD15P_71IO_L3N_T0L_N5_AD15N_71IO_L2P_T0L_N2_71IO_L2N_T0L_N3_71
IO_L24P_T3U_N10_71IO_L24N_T3U_N11_71
IO_L23P_T3U_N8_71IO_L23N_T3U_N9_71
IO_L22P_T3U_N6_DBC_AD0P_71IO_L22N_T3U_N7_DBC_AD0N_71
IO_L21P_T3L_N4_AD8P_71IO_L21N_T3L_N5_AD8N_71IO_L20P_T3L_N2_AD1P_71IO_L20N_T3L_N3_AD1N_71
IO_L1P_T0L_N0_DBC_71IO_L1N_T0L_N1_DBC_71
IO_L19P_T3L_N0_DBC_AD9P_71IO_L19N_T3L_N1_DBC_AD9N_71
IO_L18P_T2U_N10_AD2P_71IO_L18N_T2U_N11_AD2N_71IO_L17P_T2U_N8_AD10P_71IO_L17N_T2U_N9_AD10N_71
IO_L16P_T2U_N6_QBC_AD3P_71IO_L16N_T2U_N7_QBC_AD3N_71
IO_L15P_T2L_N4_AD11P_71IO_L15N_T2L_N5_AD11N_71
IO_L14P_T2L_N2_GC_71IO_L14N_T2L_N3_GC_71IO_L13P_T2L_N0_GC_QBC_71
IO_L13N_T2L_N1_GC_QBC_71IO_L12P_T1U_N10_GC_71IO_L12N_T1U_N11_GC_71IO_L11P_T1U_N8_GC_71IO_L11N_T1U_N9_GC_71IO_L10P_T1U_N6_QBC_AD4P_71IO_L10N_T1U_N7_QBC_AD4N_71
VREF
_70
VCCO
_70
VCCO
_70
VCCO
_70
IO_T3U_N12_70IO_T2U_N12_70IO_T1U_N12_70
IO_T0U_N12_VRP_70
IO_L9P_T1L_N4_AD12P_70IO_L9N_T1L_N5_AD12N_70IO_L8P_T1L_N2_AD5P_70IO_L8N_T1L_N3_AD5N_70IO_L7P_T1L_N0_QBC_AD13P_70IO_L7N_T1L_N1_QBC_AD13N_70IO_L6P_T0U_N10_AD6P_70IO_L6N_T0U_N11_AD6N_70IO_L5P_T0U_N8_AD14P_70IO_L5N_T0U_N9_AD14N_70IO_L4P_T0U_N6_DBC_AD7P_70IO_L4N_T0U_N7_DBC_AD7N_70IO_L3P_T0L_N4_AD15P_70IO_L3N_T0L_N5_AD15N_70IO_L2P_T0L_N2_70IO_L2N_T0L_N3_70
IO_L24P_T3U_N10_70IO_L24N_T3U_N11_70
IO_L23P_T3U_N8_70IO_L23N_T3U_N9_70
IO_L22P_T3U_N6_DBC_AD0P_70IO_L22N_T3U_N7_DBC_AD0N_70
IO_L21P_T3L_N4_AD8P_70IO_L21N_T3L_N5_AD8N_70IO_L20P_T3L_N2_AD1P_70IO_L20N_T3L_N3_AD1N_70
IO_L1P_T0L_N0_DBC_70IO_L1N_T0L_N1_DBC_70
IO_L19P_T3L_N0_DBC_AD9P_70IO_L19N_T3L_N1_DBC_AD9N_70
IO_L18P_T2U_N10_AD2P_70IO_L18N_T2U_N11_AD2N_70IO_L17P_T2U_N8_AD10P_70IO_L17N_T2U_N9_AD10N_70
IO_L16P_T2U_N6_QBC_AD3P_70IO_L16N_T2U_N7_QBC_AD3N_70
IO_L15P_T2L_N4_AD11P_70IO_L15N_T2L_N5_AD11N_70
IO_L14P_T2L_N2_GC_70IO_L14N_T2L_N3_GC_70IO_L13P_T2L_N0_GC_QBC_70
IO_L13N_T2L_N1_GC_QBC_70IO_L12P_T1U_N10_GC_70IO_L12N_T1U_N11_GC_70IO_L11P_T1U_N8_GC_70IO_L11N_T1U_N9_GC_70IO_L10P_T1U_N6_QBC_AD4P_70IO_L10N_T1U_N7_QBC_AD4N_70
VREF
_69
VCCO
_69
VCCO
_69
VCCO
_69
IO_T3U_N12_69IO_T2U_N12_69IO_T1U_N12_69
IO_T0U_N12_VRP_69
IO_L9P_T1L_N4_AD12P_69IO_L9N_T1L_N5_AD12N_69IO_L8P_T1L_N2_AD5P_69IO_L8N_T1L_N3_AD5N_69IO_L7P_T1L_N0_QBC_AD13P_69IO_L7N_T1L_N1_QBC_AD13N_69IO_L6P_T0U_N10_AD6P_69IO_L6N_T0U_N11_AD6N_69IO_L5P_T0U_N8_AD14P_69IO_L5N_T0U_N9_AD14N_69IO_L4P_T0U_N6_DBC_AD7P_69IO_L4N_T0U_N7_DBC_AD7N_69IO_L3P_T0L_N4_AD15P_69IO_L3N_T0L_N5_AD15N_69IO_L2P_T0L_N2_69IO_L2N_T0L_N3_69
IO_L24P_T3U_N10_69IO_L24N_T3U_N11_69
IO_L23P_T3U_N8_69IO_L23N_T3U_N9_69
IO_L22P_T3U_N6_DBC_AD0P_69IO_L22N_T3U_N7_DBC_AD0N_69
IO_L21P_T3L_N4_AD8P_69IO_L21N_T3L_N5_AD8N_69IO_L20P_T3L_N2_AD1P_69IO_L20N_T3L_N3_AD1N_69
IO_L1P_T0L_N0_DBC_69IO_L1N_T0L_N1_DBC_69
IO_L19P_T3L_N0_DBC_AD9P_69IO_L19N_T3L_N1_DBC_AD9N_69
IO_L18P_T2U_N10_AD2P_69IO_L18N_T2U_N11_AD2N_69IO_L17P_T2U_N8_AD10P_69IO_L17N_T2U_N9_AD10N_69
IO_L16P_T2U_N6_QBC_AD3P_69IO_L16N_T2U_N7_QBC_AD3N_69
IO_L15P_T2L_N4_AD11P_69IO_L15N_T2L_N5_AD11N_69
IO_L14P_T2L_N2_GC_69IO_L14N_T2L_N3_GC_69IO_L13P_T2L_N0_GC_QBC_69
IO_L13N_T2L_N1_GC_QBC_69IO_L12P_T1U_N10_GC_69IO_L12N_T1U_N11_GC_69IO_L11P_T1U_N8_GC_69IO_L11N_T1U_N9_GC_69IO_L10P_T1U_N6_QBC_AD4P_69IO_L10N_T1U_N7_QBC_AD4N_69
VREF
_68
VCCO
_68
VCCO
_68
VCCO
_68
IO_T3U_N12_68IO_T2U_N12_68IO_T1U_N12_68
IO_T0U_N12_VRP_68
IO_L9P_T1L_N4_AD12P_68IO_L9N_T1L_N5_AD12N_68IO_L8P_T1L_N2_AD5P_68IO_L8N_T1L_N3_AD5N_68IO_L7P_T1L_N0_QBC_AD13P_68IO_L7N_T1L_N1_QBC_AD13N_68IO_L6P_T0U_N10_AD6P_68IO_L6N_T0U_N11_AD6N_68IO_L5P_T0U_N8_AD14P_68IO_L5N_T0U_N9_AD14N_68IO_L4P_T0U_N6_DBC_AD7P_68IO_L4N_T0U_N7_DBC_AD7N_68IO_L3P_T0L_N4_AD15P_68IO_L3N_T0L_N5_AD15N_68IO_L2P_T0L_N2_68IO_L2N_T0L_N3_68
IO_L24P_T3U_N10_68IO_L24N_T3U_N11_68
IO_L23P_T3U_N8_68IO_L23N_T3U_N9_68
IO_L22P_T3U_N6_DBC_AD0P_68IO_L22N_T3U_N7_DBC_AD0N_68
IO_L21P_T3L_N4_AD8P_68IO_L21N_T3L_N5_AD8N_68IO_L20P_T3L_N2_AD1P_68IO_L20N_T3L_N3_AD1N_68
IO_L1P_T0L_N0_DBC_68IO_L1N_T0L_N1_DBC_68
IO_L19P_T3L_N0_DBC_AD9P_68IO_L19N_T3L_N1_DBC_AD9N_68
IO_L18P_T2U_N10_AD2P_68IO_L18N_T2U_N11_AD2N_68IO_L17P_T2U_N8_AD10P_68IO_L17N_T2U_N9_AD10N_68
IO_L16P_T2U_N6_QBC_AD3P_68IO_L16N_T2U_N7_QBC_AD3N_68
IO_L15P_T2L_N4_AD11P_68IO_L15N_T2L_N5_AD11N_68
IO_L14P_T2L_N2_GC_68IO_L14N_T2L_N3_GC_68IO_L13P_T2L_N0_GC_QBC_68
IO_L13N_T2L_N1_GC_QBC_68IO_L12P_T1U_N10_GC_68IO_L12N_T1U_N11_GC_68IO_L11P_T1U_N8_GC_68IO_L11N_T1U_N9_GC_68IO_L10P_T1U_N6_QBC_AD4P_68IO_L10N_T1U_N7_QBC_AD4N_68
GNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 16: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/16.jpg)
VCCO 1.14V...3.4V
PL HD BANK 88, 89
16 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.001UF
0.001UF
0.001UF
0.001UF
0.001UF
0.001UF
0.001UF
0.001UF
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
1KR0402L
R0402L1K
1K
R0402L
1KR0402L
499
1K
R0402L
R0402L
R0402L
750
3K
R0402L1K
R0402L
750
1KR0402L
R0402L
R0402L
R0402L
R0402L
R0402L R0402L
R0402L
R0402L
R0402L
3K
3K
750
3K
750
1K
499
1K
1K
499
499
1KR0402L
R0402L
R0402L
R0402L R0402L
1K
47UF
C1110
C1109
C1108
C1107
C1105
C1104
C1103
C1102
U21
R437
R430
R434
R432
R439
R445
R448
R447
R446
R450
R443
R451
R442
R441
R449
R440R428
R436
R431
R438
R429
R433
R435
R444
C1106
U21
VCCO_89
IO_L4P_AD12P_89IO_L4N_AD12N_89IO_L3P_AD13P_89
IO_L1P_AD15P_89IO_L1N_AD15N_89
IO_L2N_AD14N_89
IO_L5P_HDGC_89IO_L5N_HDGC_89
IO_L6N_HDGC_89IO_L6P_HDGC_89
IO_L3N_AD13N_89IO_L2P_AD14P_89
VDDA1P3_ANLG_A_SNS_NVDDA1P3_ANLG_A_SNS_P
VDDA3P3_VCXO_SNS_PVDDA3P3_VCXO_SNS_NVDDA3P3_SNS_P
VDDA1P8_B_SNS_PVDDA1P8_B_SNS_NVDDA3P3_VCO_SNS_PVDDA3P3_VCO_SNS_NVDDA3P3_CLK_SNS_PVDDA3P3_CLK_SNS_N
VDDA1P3_ANLG_B_N
VDDA1P3_ANLG_A_N
VDDA1P8_A_SNS_P
VDDA1P8_A_SNS_N
VDDA1P3_ANLG_A_SNS_P
VDDA1P3_ANLG_A_SNS_N
VDDA1P3_ANLG_A_P
VDDA1P8_B_SNS_P
VDDA1P8_B_SNS_NVDDA1P8_B_N
VDDA3P3_VCXO_P
VDDA3P3_CLK_P
VDDA3P3_SNS_P
VDDA3P3_SNS_N
VDDA3P3_VCO_N VDDA3P3_VCO_SNS_N
VDDA3P3_VCO_P
VDDA3P3_N
VDDA1P3_ANLG_B_SNS_N
VDDA1P3_ANLG_B_P
VDDA3P3_P
VDDA1P8_A_P
VDDA1P8_B_P
VDDA1P8_A_N
1V8
VDDA1P3_ANLG_B_SNS_P
VDDA1P8_A_SNS_N
VDDA3P3_VCO_SNS_P
VDDA3P3_CLK_SNS_P
VDDA3P3_VCXO_N
VDDA3P3_CLK_SNS_N
VDDA3P3_VCXO_SNS_P
VDDA3P3_VCXO_SNS_N
VDDA3P3_CLK_N
VDDA3P3_SNS_N
VDDA1P8_A_SNS_PVDDA1P3_ANLG_B_SNS_NVDDA1P3_ANLG_B_SNS_P
C14B14
E15
K12 K13K14H13J14
F13
G14H14
E14
C13D14
J13
F14
A13
E13
D15
B13
B15A15L13
G13
G15
L12
F10 F15
H10
E11
A12A11B10A10C11B11D12C12D11D10F12E12
E10G11F11H11G10J12H12
J11K10J10
VCCO
_89
VCCO
_89
IO_L9P_AD11P_89IO_L9N_AD11N_89IO_L8P_HDGC_89IO_L8N_HDGC_89IO_L7P_HDGC_89IO_L7N_HDGC_89IO_L6P_HDGC_89
IO_L6N_HDGC_89IO_L5P_HDGC_89IO_L5N_HDGC_89IO_L4P_AD12P_89IO_L4N_AD12N_89IO_L3P_AD13P_89IO_L3N_AD13N_89IO_L2P_AD14P_89IO_L2N_AD14N_89IO_L1P_AD15P_89IO_L1N_AD15N_89 IO_L12P_AD8P_89
IO_L12N_AD8N_89IO_L11P_AD9P_89IO_L11N_AD9N_89
IO_L10P_AD10P_89IO_L10N_AD10N_89
VCCO
_88
VCCO
_88
IO_L9P_AD3P_88IO_L9N_AD3N_88
IO_L8P_HDGC_AD4P_88IO_L8N_HDGC_AD4N_88IO_L7P_HDGC_AD5P_88IO_L7N_HDGC_AD5N_88IO_L6P_HDGC_AD6P_88
IO_L6N_HDGC_AD6N_88IO_L5P_HDGC_AD7P_88IO_L5N_HDGC_AD7N_88IO_L4P_AD8P_88IO_L4N_AD8N_88IO_L3P_AD9P_88IO_L3N_AD9N_88IO_L2P_AD10P_88IO_L2N_AD10N_88IO_L1P_AD11P_88IO_L1N_AD11N_88 IO_L12P_AD0P_88
IO_L12N_AD0N_88IO_L11P_AD1P_88IO_L11N_AD1N_88IO_L10P_AD2P_88IO_L10N_AD2N_88
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 17: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/17.jpg)
FROM ON-BOARD HMC7044
TALISE JESD INTERFACE A
TALISE JESD INTERFACE B
GTH TRANSCEIVERS
FROM ON-BOARD HMC7044
17 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
XCZU11EG-1FFVF1517I XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
U21
U21
U21
U21
U21
U21
U21
U21
MGTREFCLK0N_224MGTREFCLK1P_228MGTREFCLK1N_228MGTHTXP3_228MGTHTXP2_228MGTHTXP1_228MGTHTXP0_228MGTHTXN3_228MGTHTXN2_228MGTHTXN1_228
MGTHRXP3_228MGTREFCLK0N_228
MGTHRXP2_228
MGTHTXN0_225MGTHTXN1_225MGTHTXN2_225MGTHTXN3_225MGTHTXP0_225
MGTHTXN3_224
MGTREFCLK1P_229
MGTHTXP3_229
MGTHTXP1_229
MGTREFCLK1N_229
MGTHTXP0_229
MGTREFCLK0P_229
MGTHRXN0_225MGTHRXN1_225MGTHRXN2_225MGTHRXN3_225MGTHRXP0_225MGTHRXP1_225MGTHRXP2_225MGTHRXP3_225
MGTHTXP1_225MGTHTXP2_225MGTHTXP3_225
MGTREFCLK0N_225 MGTREFCLK1N_225MGTREFCLK1P_225MGTREFCLK0P_225
MGTHTXN0_229MGTHTXN1_229MGTHTXN2_229
MGTHTXP2_229
MGTHTXN3_229
MGTHTXN0_228
MGTHRXN1_229
MGTHRXN3_228MGTHRXN2_228
MGTHRXP1_228
MGTHRXN1_228
MGTREFCLK0P_228
MGTHRXP0_228
MGTHRXN0_228
MGTHRXN3_229
JESD_SERDOUT0_B_N
MGTHRXP1_229
MGTHRXP3_229MGTHRXP2_229
MGTHRXN2_229
MGTREFCLK0N_229
MGTHRXP0_229
MGTHRXN0_229
JESD_REFCLK_FPGA_B_PJESD_REFCLK_FPGA_B_NJESD_SERDOUT3_B_PJESD_SERDOUT2_B_PJESD_SERDOUT1_B_PJESD_SERDOUT0_B_PJESD_SERDOUT3_B_NJESD_SERDOUT2_B_NJESD_SERDOUT1_B_N
MGTHTXP1_227MGTHTXP2_227MGTHTXP3_227MGTREFCLK1N_227MGTREFCLK1P_227
MGTHTXN3_227MGTHTXN2_227MGTHTXN1_227
MGTHTXP0_227
MGTHTXN0_227 JESD_SERDOUT0_A_N
MGTHTXP2_226MGTHTXP3_226MGTREFCLK1N_226
MGTHTXN3_226MGTHTXN2_226
MGTREFCLK1P_226
MGTHTXP1_226
MGTHTXN1_226
MGTHTXP0_226
MGTHTXN0_226
MGTREFCLK1N_224MGTREFCLK1P_224
MGTHTXP3_224MGTHTXP2_224
MGTHTXN2_224
MGTHTXP1_224
MGTHTXN1_224
MGTHTXP0_224
MGTHTXN0_224
MGTREFCLK0P_226
MGTREFCLK0P_227
MGTHRXP3_224
MGTHRXN3_224
MGTHRXP2_224
MGTHRXN2_224
MGTHRXP1_224
MGTHRXN1_224
MGTREFCLK0P_224
MGTHRXP0_224
MGTHRXN0_224
MGTHRXP3_227
MGTHRXN3_227
MGTHRXP2_227
MGTHRXN2_227
MGTHRXP1_227
MGTHRXN1_227
MGTREFCLK0N_227
MGTHRXP0_227
MGTHRXN0_227
MGTHRXP3_226
MGTHRXN3_226
MGTHRXP2_226
MGTHRXN2_226
MGTHRXP1_226
MGTHRXN1_226
MGTREFCLK0N_226
MGTHRXP0_226
MGTHRXN0_226
JESD_SERDIN3_B_N
JESD_REFCLK_FPGA_A_NJESD_SERDOUT3_A_PJESD_SERDOUT2_A_PJESD_SERDOUT1_A_PJESD_SERDOUT0_A_PJESD_SERDOUT3_A_NJESD_SERDOUT2_A_NJESD_SERDOUT1_A_N
JESD_SERDIN2_B_N
JESD_SERDIN0_B_NJESD_SERDIN1_B_N
JESD_SERDIN0_A_NJESD_SERDIN1_A_NJESD_SERDIN2_A_N
JESD_SERDIN0_A_PJESD_SERDIN1_A_PJESD_SERDIN2_A_PJESD_SERDIN3_A_P
JESD_REFCLK_FPGA_A_P
JESD_SERDIN3_A_N
JESD_SERDIN0_B_PJESD_SERDIN1_B_PJESD_SERDIN2_B_PJESD_SERDIN3_B_P
AH10
T6N7
R7T5
AM6
T10T9
M6
J4K2L4M2
AE12AE11
AF10AF9
AE8AF6AG8AH6AE7AF5AG7AH5
AE4AF2AG4AH2AE3AF1AG3AH1
Y10Y9
AA12AA11
U8V6W8Y6U7V5W7Y5
U4V2W4Y2U3V1W3Y1
AB10AB9
AD10AD9
AA8AB6AC8AD6AA7AB5AC7AD5
AA4AB2AC4AD2AA3AB1AC3AD1
AG12AG11AH9AJ8AK6AL8
AJ7AK5AL7AM5
AJ4AK2AL4AM2AJ3AK1AL3AM1
M10M9
N12N11
A8B6C8D6A7B5C7D5
A4B2C4D2A3B1C3D1
P10P9
R12R11
E8F6G8H6E7F5G7H5
E4F2G4H2E3F1G3H1
U12U11
J8K6L8
J7K5L7M5
J3K1L3M1
V10V9
W12W11
N8P6R8
P5
N4P2R4T2N3P1R3T1
MGTREFCLK1P_227MGTREFCLK1N_227
MGTREFCLK0P_227MGTREFCLK0N_227
MGTHTXP3_227MGTHTXP2_227MGTHTXP1_227MGTHTXP0_227MGTHTXN3_227MGTHTXN2_227MGTHTXN1_227MGTHTXN0_227
MGTHRXP3_227MGTHRXP2_227MGTHRXP1_227MGTHRXP0_227MGTHRXN3_227MGTHRXN2_227MGTHRXN1_227MGTHRXN0_227
MGTREFCLK1P_226MGTREFCLK1N_226
MGTREFCLK0P_226MGTREFCLK0N_226
MGTHTXP3_226MGTHTXP2_226MGTHTXP1_226MGTHTXP0_226MGTHTXN3_226MGTHTXN2_226MGTHTXN1_226MGTHTXN0_226
MGTHRXP3_226MGTHRXP2_226MGTHRXP1_226MGTHRXP0_226MGTHRXN3_226MGTHRXN2_226MGTHRXN1_226MGTHRXN0_226
MGTREFCLK1P_225MGTREFCLK1N_225
MGTREFCLK0P_225MGTREFCLK0N_225
MGTHTXP3_225MGTHTXP2_225MGTHTXP1_225MGTHTXP0_225MGTHTXN3_225MGTHTXN2_225MGTHTXN1_225MGTHTXN0_225
MGTHRXP3_225MGTHRXP2_225MGTHRXP1_225MGTHRXP0_225MGTHRXN3_225MGTHRXN2_225MGTHRXN1_225MGTHRXN0_225
MGTREFCLK1P_224MGTREFCLK1N_224
MGTREFCLK0P_224MGTREFCLK0N_224
MGTHTXP3_224MGTHTXP2_224MGTHTXP1_224MGTHTXP0_224MGTHTXN3_224MGTHTXN2_224MGTHTXN1_224MGTHTXN0_224
MGTHRXP3_224MGTHRXP2_224MGTHRXP1_224MGTHRXP0_224MGTHRXN3_224MGTHRXN2_224MGTHRXN1_224MGTHRXN0_224
MGTREFCLK1P_231MGTREFCLK1N_231
MGTREFCLK0P_231MGTREFCLK0N_231
MGTHTXP3_231MGTHTXP2_231MGTHTXP1_231MGTHTXP0_231MGTHTXN3_231MGTHTXN2_231MGTHTXN1_231MGTHTXN0_231
MGTHRXP3_231MGTHRXP2_231MGTHRXP1_231MGTHRXP0_231MGTHRXN3_231MGTHRXN2_231MGTHRXN1_231MGTHRXN0_231
MGTREFCLK1P_230MGTREFCLK1N_230
MGTREFCLK0P_230MGTREFCLK0N_230
MGTHTXP3_230MGTHTXP2_230MGTHTXP1_230MGTHTXP0_230MGTHTXN3_230MGTHTXN2_230MGTHTXN1_230MGTHTXN0_230
MGTHRXP3_230MGTHRXP2_230MGTHRXP1_230MGTHRXP0_230MGTHRXN3_230MGTHRXN2_230MGTHRXN1_230MGTHRXN0_230
MGTREFCLK1P_229MGTREFCLK1N_229
MGTREFCLK0P_229MGTREFCLK0N_229
MGTHTXP3_229MGTHTXP2_229MGTHTXP1_229MGTHTXP0_229MGTHTXN3_229MGTHTXN2_229MGTHTXN1_229MGTHTXN0_229
MGTHRXP3_229MGTHRXP2_229MGTHRXP1_229MGTHRXP0_229MGTHRXN3_229MGTHRXN2_229MGTHRXN1_229MGTHRXN0_229
MGTREFCLK1P_228MGTREFCLK1N_228
MGTREFCLK0P_228MGTREFCLK0N_228
MGTHTXP3_228MGTHTXP2_228MGTHTXP1_228MGTHTXP0_228MGTHTXN3_228MGTHTXN2_228MGTHTXN1_228MGTHTXN0_228
MGTHRXP3_228MGTHRXP2_228MGTHRXP1_228MGTHRXP0_228MGTHRXN3_228MGTHRXN2_228MGTHRXN1_228MGTHRXN0_228
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 18: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/18.jpg)
VCCAUX/VCCAUX_IO DECOUPLING VCCINT/VCCINT_IO/VCCBRAM DECOUPLING
PLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGAROUTE 0V85_PL_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGA
ROUTE 0V85_PS_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGAVCCPSPLL DECOUPLINGPLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGA
VCCPSINTFP/LP DECOUPLING
ZYNQ ULTRASCALE POWER
VCCPSAUX DECOUPLING
18 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.47UF
0.47UF
600OHMS
600OHMS
120OHM
470UF470UF
100UF 4.7UF
4.7UF
4.7UF 4.7UF 4.7UF 4.7UF4.7UF 4.7UF
4.7UF
4.7UF 4.7UF
4.7UF
4.7UF 4.7UF 4.7UF
4.7UF4.7UF4.7UF
0.1UF
100UF 100UF
100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF
100UF
100UF 100UF100UF100UF100UF100UF
100UF
100UF 100UF 100UF 100UF100UF 100UF
470UF 470UF 470UF 470UF 470UF 470UF
XCZU11EG-1FFVF1517I
C243
C248
E9
E8
E7
C267
C281
C260C257
C241
U21
C244C238 C240 C250 C252
C237 C239 C242 C246 C249 C251 C253 C254 C255
C258 C261
C247
C245
C265C264C263C262C259C256
C270 C273 C276 C291C290C289C288C287
C286C284C278C275C272C269C266
C283C280C277C274C271C268
C285C282C279
1V8_VCCPSAUX
1V8_VCCPSAUX
VCC_PSBATT
1V8_VCCPSAUX
0V85_PSINTFP
0V85_PSINTLP
1V8
0V85_PSINTLP
1V8_VCCAUX
GND_ADC
0V85_PL
0V85_PS_SNS_N
0V85_PS_SNS_P0V85_PSINTFP0V85_PSINTLP
0V85_PL_SNS_P
VCC_ADC
VCC_PSPLL
1V8
1V2_MGTAVTT
VCC_PSPLL
1V8
0V85_PSINTLP
0V85_PSINTFP
VCC_PSPLL
0V85_PL_SNS_N
0V85_PL
0V85_PL
VCC_ADC
0V85_PL1V8_VCCAUX0V85_PSINTFP
0V85_PS
1V8_VCCAUX
V14
AB14
AD29
AB29
T16
AC29 R19R21
AC27AD30
AE25
AA27
AD26
P16
AE21
AD18
AF18
P14
R17
Y14
T14
Y24
Y22
Y18
Y16
W23
W21
W17
V24
V22
V18
V16
U23
U21
U19
U17
T24
T22
T20
T18
R23
R15P24P22P20P18
AF22AF20
AF16AF14
AE19AE17AE15AD22AD20
AD16AD14
AC21
AC19
AC17
AB22
AB20
AB18
AB16
AA21
AA17
W15U15
AC15
AA15
W25U25
R25
P25
Y26
V26
T26
P26
V20
AA26
AA25
AA23AC24AC23AB26AB25AB24AB23AE28AE27
AE24AE23AD27
AD25AD24AC26AA28
VCCI
NT_I
OVC
CINT
_IO
VCCI
NT_I
OVC
CINT
_IO
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NT
VCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CBRA
MVC
CBRA
MVC
CBRA
MVC
CBRA
MVC
CAUX
_IO
VCCA
UX_I
OVC
CAUX
_IO
VCCA
UX_I
OVC
CAUX
VCCA
UXVC
CAUX
VCCA
UXVC
CADC
VCC_
PSPL
LVC
C_PS
PLL
VCC_PSPLLVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTFP_DDRVCC_PSINTFP_DDRVCC_PSINTFP_DDRVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSDDR_PLLVCC_PSDDR_PLLVCC_PSBATTVCC_PSAUXVCC_PSAUXVCC_PSAUXVCC_PSAUX
GNDGND GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 19: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/19.jpg)
NEED TO BE CONNECTED TO GND IF NOT USED
DISABLE PULL-UP DURING CONFIG
BANK 227
BANK 226
GT POWER
USE INTERNAL REFERENCE
BANK 228BANK 224
BANK 225
PLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGAROUTE 0V85_PS_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGA
BANK 229
BANK 230
BANK 231
19 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
4.7UF 4.7UF0.22UF4.7UF0.47UF 0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF
0.47UF0.47UF0.47UF
DNI
0
0
0
DNI
1K
DNI
4.7UF 4.7UF 0.22UF
4.7UF
0.22UF 4.7UF 0.22UF4.7UF0.22UF
4.7UF 0.22UF
4.7UF 0.22UF 4.7UF
100UF 100UF
0.22UF
4.7UF
0.22UF 4.7UF
4.7UF0.22UF4.7UF0.22UF
0.22UF
4.7UF
100
0.1500
XCZU11EG-1FFVF1517I
DNI DNI100UF 100UF 100UF 100UF100UF 100UF 100UF
100UF
DNI DNI DNI
100UF100UF100UF100UF
100UF
100UF100UF100UF100UF100UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF 0.01UF
0.01UF 0.01UF 0.01UF
4.7UF
4.7UF 4.7UF 4.7UF
4.7UF 4.7UF
4.7UF 4.7UF
4.7UF
4.7UF
C780 C786 C790C724 C775
C774
C722
C721
C723
C773
C772
C762C759C752
R453
R452
R286
R285
R282
R283
C770C732 C742
C747
C748
C755
C756
C719 C727 C735
C718
C731
C746C715
C740
U21
C782C781C776C771C766
C712 C714 C720 C728 C736 C744 C751 C754 C761 C764
C763C760C753C750C743C713C711
C749
C741 C757 C769 C779 C785 C789
C794
C793
C758
C717
C767
C768
C777
C778 C784
C783
C788 C792
C787 C791
C730C716
C739C729
R284
C738C734C726
C765C745C737C733C725
R281
1V2_MGTAVTT MGTVCCAUX
VCC_ADC
0V85_PL
0V9_MGTAVCC
1V2_MGTAVTT
1V2_MGTAVTTMGTVCCAUX
0V9_MGTAVCC_SNS_N0V9_MGTAVCC_SNS_P
0V9_MGTAVCC 1V2_MGTAVTT
0V9_MGTAVCC
MGTVCCAUX
1V8_MGTRAVTT
0V9_MGTAVCC
1V2_MGTAVTT
0V9_MGTAVCC
0V9_MGTAVCC
GND_ADC
1V2_MGTAVTT
1V8_MGTRAVTT
MGTVCCAUX
0V9_MGTAVCC 1V2_MGTAVTT
0V9_MGTAVCC
MGTAVTTRCAL
1V8_MGTRAVTT
0V85_MGTRAVCC
MGTVCCAUX
1V8_VCCAUX
0V85_MGTRAVCC
1V2_MGTAVTT
1V2_MGTAVTT
1V2_MGTAVTT
1V2_MGTAVTT
0V9_MGTAVCC
MGTVCCAUX MGTVCCAUX
MGTVCCAUX
MGTVCCAUX
MGTVCCAUX
0V9_MGTAVCC
0V9_MGTAVCC
MGTAVTTRCAL
0V9_MGTAVCC GND_ADC
AK8
E6F8
P8N6
AE10
AA10
Y20W19
W20Y19AG15
U33
Y34V34
AA36W32
AB34AA32
AG14
AG26
AG25
AF27
AF26
AF25
AF23
AF12AD12AB12
Y12V12T12
AC12
AC11
Y8W6V8U6
AL6AJ6AG6AF8AE6AD8AC6AB8AA6
T8R6
L6J6G6
D8C6B8A6
AM8
AH8AG10
AC10
W10
U10
R10
P12N10M8K8H8
AA20AA19
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND GND GND
GNDGNDGND
GND
GND
GND
NCNCNCNCNCNCPS_MGTRAVTTPS_MGTRAVTTPS_MGTRAVTTPS_MGTRAVCCPS_MGTRAVCCPS_MGTRAVCC
MG
TAVT
TRCA
L_R
VREFPVREFN
VPVN
PS_MGTRREF_505POR_OVERRIDE
MGTVCCAUX_RSMGTVCCAUX_RSMGTVCCAUX_RSMGTVCCAUX_RNMGTVCCAUX_RNMGTVCCAUX_RN
MGTRREF_R
MGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVCC_RSMGTAVCC_RSMGTAVCC_RSMGTAVCC_RS
MG
TAVC
C_RS
MG
TAVC
C_RS
MG
TAVC
C_RS
MG
TAVC
C_RN
MG
TAVC
C_RN
MG
TAVC
C_RN
MGTAVCC_RNMGTAVCC_RNMGTAVCC_RNMGTAVCC_RNMGTAVCC_RNDXPDXNPUDC_B
GNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 20: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/20.jpg)
ZYNQ ULTRASCALE POWER
20 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
XCZU11EG-1FFVF1517I
U21B22
B17
B12
B9 B7 B4 B3 AW38
AW33
AW28
AW23
AW18
AW13
AW8
AW3
AV39
AV30
AV25
AV20
AV15
AV10
AV5
AV1
AU37
AU32
AU27
AU12
AU7
AU2
AT29
AT24
AT19
AT4
AR36
AR31
AR26
AR21
AR16
AR11
AR1
AP28
AP13
AN35
AN30
AN25
AN20
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2AN1AM37AM32AM27AM22AM17AM12AM9AM7AM4AM3AL39AL29AL14AL9AL5AL2AL1AK36AK31AK26AK21AK9AK7AK4AK3AJ38AJ33AJ23AJ18AJ13AJ11AJ10AJ9AJ5AJ2AJ1AH35AH30AH26AH25AH20AH15AH13AH12AH11AH7AH4AH3AG37AG32
AG27
AG17
AG13
AG9
AG5
AG2
AG1
AF39
AF34
AF28
AF24
AF21
AF19
AF17
AF15
AF13
AF11AF
7AF
4AF
3AE
36AE
31AE
26AE
22AE
20AE
18AE
16AE
14AE
13AE
9AE
5AE
2AE
1AD
38AD
33AD
28AD
23AD
21AD
19AD
17AD
15AD
13AD
11AD
7AD
4AD
3AC
39AC
38AC
37AC
36AC
35AC
34
AC33AC32AC31AC30AC25AC22AC20AC18AC16AC14AC13AC9AC5AC2AC1
AB39AB38AB35AB31AB30AB27AB21AB19AB17AB15AB13AB11AB7AB4AB3
AA37AA33AA31AA29AA24AA22AA18AA16AA14AA13AA9AA5AA2AA1A34A29A24A19A14A9A5A2 G
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
ND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 21: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/21.jpg)
ZYNQ ULTRASCALE POWER
21 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
XCZU11EG-1FFVF1517I
U21
GND_ADC
V19
Y38
Y35
Y31
Y27
Y25
Y23
Y21
Y17
Y15
Y13
Y11
Y7 Y4 Y3 W37
W36
W33
W31
W26
W24
W22
W18
W16
W14
W13
W9
W5
W2
W1
V39
V38
V35
V31
V30
V25
V23
V21
Y39
V17
V15
V13
V11
V7 V4 V3 U37
U36
U32
U31
U27
U26
U24
U22U20U18U16U14U13U9U5U2U1T39T38T37T36T35T34T33T32T31T29T25T23T21T19T17T15T13T11T7T4T3R36R31R26R24R22R20R18R16R14R13R9R5R2R1P23P21P19P17P15P13P11
P7P4P3N35
N30
N26
N25
N24
N20
N15
N13N9N5N2N1M
37M
32M
27M
22M
17M
13M
12M
11M7
M4
M3
L39
L29
L24
L19
L14
L11
L10L9L5L2L1K36
K31
K26
K21
K16
K11K9K7K4K3J33J9J5J2J1
H35H30H25H20H15H9H7H4H3
G37G27G22G17G12G9G5G2G1
F39F34F9F7F4F3
E31E26E21E16E9E5E2E1
D38D28D23D18D13D9D7D4D3
C35C15C10C9C5C2C1
B39B37B32B27 G
NDAD
CG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
ND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 22: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/22.jpg)
TALISE A
(AUXDAC_4)
(AUXDAC_9/FLASH CLK)
(AUXDAC_5)
(AUXDAC_6)
(AUXDAC_1/FLASH CS)
(AUXDAC_0/FLASH SO)
(AUXDAC_7)
(AUXDAC_8)
(AUXDAC_3/FLASH SI)
(AUXDAC_2)
USE LOW-PROFILE PADS FOR CAPACITORS
USE LOW-PROFILE PADS FOR CAPACITORS
JESD CAPS CLOSE TO FPGA
22 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ADRV9009BBCZ
37
R0201L
10K
82
0.1UF0.1UF
0.1UF0.1UF
20
88
4.7K
100
1K
R0201L
25
59
0
0
0
0
0
0
0
0
100
100
90
14.3K
81
10K10K
89
10K
DNI26
10K
27
10K
1UF
21
58
1UF
100PF
1UF
68
0.1UF
0.1UF9
8
11
15
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
U14
R142
C407
C401
C402
C410
C404
C405
C406
R520
R527
R144
R552
R146
C413
R139
R519
R518
R517
R516
R515
R514
R513
R551
R553
R143R141R140
R145
C416
C400
C399
C418C415
C417C414
C412
C411
C409
C408C403
RX1_IN_A_NRX1_IN_A_P
RX2_IN_A_NRX2_IN_A_P
ORX1_IN_A_NORX1_IN_A_P
ORX2_IN_A_NORX2_IN_A_P
SYNCOUTB0_A_P_ADRV
SYNCOUTB0_A_N_ADRV
TX1_OUT_A_N
TX2_OUT_A_PTX1_OUT_A_P
TX2_OUT_A_N
VDDA1P8_TX_A
VDDA1P3_RX_TX_A
GPIO_18_A
VDDA1P3_AUX_VCO_LDO_A
VDDA1P3_CLOCK_VCO_LDO_A
GPINT_A
VDDA1P3_AUX_SYNTH_A
RF_EXT_LO_A_PRF_EXT_LO_A_N
VDD_INTERFACE_A
GPIO_16_A
GPIO_17_A
SYNCINB0_A_P_ADRV
SYNCINB0_A_N_ADRV
GPIO_7_AGPIO_6_ASYNCINB1_A_P_ADRVSYNCINB1_A_N_ADRV
GPIO_9_AGPIO_14_A
GPIO_0_AGPIO_3_AGPIO_4_AGPIO_5_A
JESD_SYSREF_IN_A_NJESD_SYSREF_IN_A_P
GPIO_10_AGPIO_13_A
GPIO_1_AGPIO_2_A
GPIO_11_AGPIO_12_A
RF_SYNTH_VTUNE_A
VDDA1P3_RF_SYNTH_A
VDDA1P3_CLOCK_SYNTH_A
AUXADC_2_A
AUXADC_1_A
AUXADC_0_A
GPIO_3P3_11_A
GPIO_3P3_7_A
AUXADC_3_A
GPIO_3P3_4_AGPIO_3P3_1_A
GPIO_3P3_9_AVDDA3P3
VDDA1P3_RF_LO_A
GPIO_3P3_3_AGPIO_3P3_0_A
VDDA1P3_RX_RF_A
SYNCINB1_A_N_ADRV
SYNCOUTB1_A_N_ADRVSYNCOUTB1_A_P_ADRV
JESD_SERDIN3_A_NJESD_SERDIN3_A_PJESD_SERDIN2_A_N
JESD_SERDIN0_A_N
JESD_SERDOUT2_A_PJESD_SERDOUT2_A_NJESD_SERDOUT3_A_PJESD_SERDOUT3_A_N
GPIO_15_AGPIO_8_A
VDD1P3_DIG_A
SYNCINB0_A_P_ADRV
SYNCINB1_A_P_ADRV
SYNCINB1_A_N
SYNCINB0_A_P
SYNCINB1_A_P
SPI_CLK
SPI_MISOSPI_MOSI
SPI_CSN_ADRV9009_A
VDD_INTERFACE_A
VDD_INTERFACE_A
RESETB_A
TEST_A
AUX_SYNTH_OUT_A
REF_CLK_IN_A_P
GPIO_3P3_5_AGPIO_3P3_6_A
REF_CLK_IN_A_N
VDDA1P3_BB_AVDDA1P8_BB_A
SYNCINB0_A_NSYNCINB0_A_N_ADRV
SYNCOUTB1_A_PSYNCOUTB1_A_P_ADRV
SYNCOUTB1_A_NSYNCOUTB1_A_N_ADRV
SYNCOUTB0_A_PSYNCOUTB0_A_P_ADRV
SYNCOUTB0_A_NSYNCOUTB0_A_N_ADRV
RX1_ENABLE_ATX1_ENABLE_A
JESD_SERDOUT0_A_N
RX2_ENABLE_AAUX_SYNTH_VTUNE_AJESD_SERDIN0_A_P
JESD_SERDIN1_A_P
JESD_SERDOUT1_A_PJESD_SERDOUT1_A_N
VDDA1P3_DES_A
JESD_SERDIN2_A_P
TX2_ENABLE_A
VDDA1P3_RF_VCO_LDO_A
GPIO_3P3_2_AGPIO_3P3_10_AGPIO_3P3_8_A
JESD_SERDIN1_A_N
JESD_SERDOUT0_A_PVDDA1P3_SER_A
P7 P6P9 N12
N13
N8 N7 N4N5
K11
K1J14
K3
H8
J3J4
J1H14
H12
H4
J2
H7
H5
J5
H13
J13J12J11J10J9J8
G8
G7
F12
F11E8D10
D11D9D8
K9
K2B5
B3
L2
C12
C8
C10
C14
C6
B14
D1L1
0
L7P1
0
P3 P2 N14
N2 M9
M2
L1K14K13
H10H9
H6
H3H2
G14
G13
G12
G11
G10G
6
G4
G3
G2
G1
F14
F13
F10F9F8F7F6F5F2F1E9E6D12
D7D6D5D4D3
C11
C9
C4
B13B12B11B10
B9
B6
B4
B2
A14
A11
A8A7
A4
A1
L9 L8
E12E4
P8
C3
B1
C5
N9 N1
G5E5
C7
M1
M12
H1
M8
M6
J6
K4
L13
L14
M13
M14
L3L4
M3
M4
N3N6P4P5P11
P12
P13
P14
N10
N11
A6A5
M7
A10A9
M5
G9
B7B8
E7
A3A2
A13A12
M10
M11
L11
H11
K12
L12
L6L5
K5K6
E14
D14
C13
D13
E13E3E2
D2
C2
E1
C1
K7
J7
K8
K10
E11 F4F3
P1
E10
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSA
VSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSAVSSA
RX1_IN-RX1_IN+
RX2_IN-RX2_IN+
VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO
ORX1_IN-ORX1_IN+
ORX2_IN-ORX2_IN+
SERD
IN2+
SERD
IN2-
SERD
IN3+
SERD
IN3-
VDDA
1P3_
DES
VDDA
1P3_
SER
SERD
IN0+
SERD
IN0-
SERD
IN1+
SERD
IN1-
VDDA
1P3_
DES
VDDA
1P3_
SER
SYNC
OUT
B0+
SYNC
OUT
B0-
TX2_
ENAB
LE
TX1_
ENAB
LE
SYNC
OUT
B1+
SYNC
OUT
B1-
TX1_OUT-
TX2_OUT+TX1_OUT+
TX2_OUT-
VDDA
1P8_
TX
VDDA1P3_RX_TX
VSSA
GPIO_18
AUX_
SYNT
H_O
UT
VDDA
1P1_
AUX_
VCO
VDDA1P3_AUX_VCO_LDO
AUX_
SYNT
H_VT
UNE
VDDA
1P3_
CLO
CK_V
CO_L
DO
VDDD
1P3_
DIG
VDDD
1P3_
DIG
GP_INTERRUPT
VDDA
1P3_
AUX_
SYNT
H
RF_EXT_LO_I/O+RF_EXT_LO_I/O-
SERD
OUT
0+SE
RDO
UT0-
SERD
OUT
1+SE
RDO
UT1-
SERD
OUT
2+SE
RDO
UT2-
SERD
OUT
3+SE
RDO
UT3-
VDD_
INTE
RFAC
EG
PIO
_16
GPI
O_1
7
RX2_
ENAB
LE
RX1_
ENAB
LESY
NCIN
B0+
SYNC
INB0
-
VDDA
1P1_
CLO
CK_V
CO
GPI
O_8
GPI
O_1
5VS
SD
VSSDGPIO_7GPIO_6
SYNCINB1+SYNCINB1-
GPIO_9GPIO_14
CSBSCLK
GPIO_0GPIO_3GPIO_4GPIO_5
SYSREF_IN-SYSREF_IN+
GPIO_10GPIO_13
SDOSDIO
GPIO_1GPIO_2
TEST
RESETB
GPIO_11GPIO_12
RF_S
YNTH
_VTU
NE
VDDA
1P3_
RF_S
YNTH
VDDA
1P3_
CLO
CK_S
YNTH
AUXA
DC_2
AUXA
DC_1
AUXA
DC_0
GPI
O_3
p3_1
1G
PIO
_3p3
_7
AUXA
DC_3
REF_
CLK_
IN-
REF_
CLK_
IN+
VDDA
1P3_
BBVD
DA1P
8_BB
GPI
O_3
p3_6
GPI
O_3
p3_5
GPI
O_3
p3_2
GPI
O_3
p3_1
0G
PIO
_3p3
_8
GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3
VDDA1P3_RF_LOVDDA1P1_RF_VCO
GPIO_3p3_3GPIO_3p3_0
VDDA1P3_RX_RF
VSSA
GNDGND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 23: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/23.jpg)
TALISE B
JESD CAPS CLOSE TO FPGA
USE LOW-PROFILE PADS FOR CAPACITORS
USE LOW-PROFILE PADS FOR CAPACITORS
(AUXDAC_3/FLASH SI)
(AUXDAC_8)
(AUXDAC_9/FLASH CLK)
(AUXDAC_4)
(AUXDAC_5)
(AUXDAC_1/FLASH CS)
(AUXDAC_6)
(AUXDAC_2)
(AUXDAC_0/FLASH SO)
(AUXDAC_7)
23 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ADRV9009BBCZ
5
0
0
0
0
0
0
0
0
100
10K
4.7K
100100
10K
25 DNI
R0201L
R0201L
1K
23
14.3K
27
24
10K
21
10K
20
10K
7
10K
6
22
100PF
1UF
26
1UF
29
1UF
28
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
4
3
2
15
14
10
8
1
13
12
11
9
19
18
17
16
U38
R505
R498
R499
R500
R501
R502
R503
R504
R548
R549R550 R88 R89
R90
R83
R84 R85 R86 R87
R526
C318
C321
C304
C305
C306
C307C312
C311
C310
C309
C308
C317
C315
C316
C313
C314
C323C320
C319C322
RX1_IN_B_NRX1_IN_B_P
RX2_IN_B_NRX2_IN_B_P
ORX1_IN_B_NORX1_IN_B_P
ORX2_IN_B_NORX2_IN_B_P
SYNCOUTB0_B_P_ADRV
SYNCOUTB0_B_N_ADRV
TX1_OUT_B_N
TX2_OUT_B_PTX1_OUT_B_P
TX2_OUT_B_N
VDDA1P8_TX_B
VDDA1P3_RX_TX_B
GPIO_18_B
VDDA1P3_AUX_VCO_LDO_B
VDDA1P3_CLOCK_VCO_LDO_B
GPINT_B
VDDA1P3_AUX_SYNTH_B
RF_EXT_LO_B_PRF_EXT_LO_B_N
VDD_INTERFACE_B
GPIO_16_B
GPIO_17_B
SYNCINB0_B_P_ADRV
SYNCINB0_B_N_ADRV
GPIO_7_BGPIO_6_BSYNCINB1_B_P_ADRVSYNCINB1_B_N_ADRV
GPIO_9_BGPIO_14_B
GPIO_0_BGPIO_3_BGPIO_4_BGPIO_5_B
JESD_SYSREF_IN_B_NJESD_SYSREF_IN_B_P
GPIO_10_BGPIO_13_B
GPIO_1_BGPIO_2_B
GPIO_11_BGPIO_12_B
RF_SYNTH_VTUNE_B
VDDA1P3_RF_SYNTH_B
VDDA1P3_CLOCK_SYNTH_B
AUXADC_2_B
AUXADC_1_B
AUXADC_0_B
GPIO_3P3_11_B
GPIO_3P3_7_B
AUXADC_3_B
GPIO_3P3_4_BGPIO_3P3_1_B
GPIO_3P3_9_BVDDA3P3
VDDA1P3_RF_LO_B
GPIO_3P3_3_BGPIO_3P3_0_B
VDDA1P3_RX_RF_B
SYNCINB1_B_NSYNCINB1_B_N_ADRV
SYNCOUTB0_B_NSYNCOUTB0_B_N_ADRV
SYNCOUTB0_B_PSYNCOUTB0_B_P_ADRV
SYNCOUTB1_B_NSYNCOUTB1_B_N_ADRV
SYNCOUTB1_B_PSYNCOUTB1_B_P_ADRV
SYNCINB0_B_NSYNCINB0_B_N_ADRV
SYNCINB0_B_PSYNCINB0_B_P_ADRV
SYNCINB1_B_PSYNCINB1_B_P_ADRV
SPI_CLK
SPI_MISO
RESETB_B
SPI_MOSI
VDD_INTERFACE_B
VDD_INTERFACE_B
SPI_CSN_ADRV9009_B
SYNCOUTB1_B_N_ADRV
SYNCOUTB1_B_P_ADRV
GPIO_8_B
RX1_ENABLE_BTX1_ENABLE_B
GPIO_3P3_5_BGPIO_3P3_6_B
VDDA1P3_BB_BVDDA1P8_BB_B
VDD1P3_DIG_B
VDDA1P3_RF_VCO_LDO_B
AUX_SYNTH_VTUNE_B
VDDA1P3_DES_B
VDDA1P3_SER_B
TX2_ENABLE_B
GPIO_15_B
TEST_B
RX2_ENABLE_B
JESD_SERDIN2_B_N
JESD_SERDOUT0_B_N
JESD_SERDIN3_B_N
JESD_SERDIN2_B_P
JESD_SERDOUT0_B_P
JESD_SERDIN1_B_P
JESD_SERDIN0_B_PJESD_SERDIN0_B_N
JESD_SERDIN1_B_N
JESD_SERDIN3_B_P
JESD_SERDOUT2_B_N
JESD_SERDOUT3_B_NJESD_SERDOUT3_B_P
JESD_SERDOUT2_B_P
JESD_SERDOUT1_B_NJESD_SERDOUT1_B_P
REF_CLK_IN_B_PREF_CLK_IN_B_N
GPIO_3P3_2_BGPIO_3P3_10_BGPIO_3P3_8_B
AUX_SYNTH_OUT_B
K10K11
J9J10
M1
M2
B6B5
E10
P1
F3 F4 F11
E11
J5
K8
J8J7
K7
C1
D1
E1
C2
D2
E2 E3 E13
D13
C13
D14
E14
K6K5
L5L6
L12
K12
J12
H12H11
J11
L11
M11
M10
J3
A12A13
A2A3
C14
E7 E8
J4
B8B7
G9
M5
A9A10
M7
A5A6
K9N1
3N1
2N1
1N1
0
P14
P13
P12
P11
P7 P6 P5 P4 N6 N5 N4 N3 M4
M3
L4L3
M14
M13
L14
L13
K3K4
J6
M6
H14
J14
M8
J1
H1
M12
D10
C7
G8
C10
E5 G5
N1N9P9
C8
G7
C5C6
B1
C3
N8P8
E4 E12
C12
L8L9
A1
A4
A7A8
A11
A14
B2B3B4
B9B10B11B12B13B14
C4
C9
C11
D3D4D5D6D7
D8 D9 D11
D12 E6 E9 F1 F2 F5 F6 F7 F8 F9 F10
F12
F13
F14
G1
G2
G3
G4
G6
G10
G11
G12
G13
G14
H2H3H4H5H6H7H8H9H10
H13
J2
J13
K1K2
K13K14L1L2
M9
N2N7N14
P2P3P10
L7
L10
GND
GND
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSA
VSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSAVSSA
RX1_IN-RX1_IN+
RX2_IN-RX2_IN+
VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO
ORX1_IN-ORX1_IN+
ORX2_IN-ORX2_IN+
SERD
IN2+
SERD
IN2-
SERD
IN3+
SERD
IN3-
VDDA
1P3_
DES
VDDA
1P3_
SER
SERD
IN0+
SERD
IN0-
SERD
IN1+
SERD
IN1-
VDDA
1P3_
DES
VDDA
1P3_
SER
SYNC
OUT
B0+
SYNC
OUT
B0-
TX2_
ENAB
LE
TX1_
ENAB
LE
SYNC
OUT
B1+
SYNC
OUT
B1-
TX1_OUT-
TX2_OUT+TX1_OUT+
TX2_OUT-
VDDA
1P8_
TX
VDDA1P3_RX_TX
VSSA
GPIO_18
AUX_
SYNT
H_O
UT
VDDA
1P1_
AUX_
VCO
VDDA1P3_AUX_VCO_LDO
AUX_
SYNT
H_VT
UNE
VDDA
1P3_
CLO
CK_V
CO_L
DO
VDDD
1P3_
DIG
VDDD
1P3_
DIG
GP_INTERRUPT
VDDA
1P3_
AUX_
SYNT
H
RF_EXT_LO_I/O+RF_EXT_LO_I/O-
SERD
OUT
0+SE
RDO
UT0-
SERD
OUT
1+SE
RDO
UT1-
SERD
OUT
2+SE
RDO
UT2-
SERD
OUT
3+SE
RDO
UT3-
VDD_
INTE
RFAC
EG
PIO
_16
GPI
O_1
7
RX2_
ENAB
LE
RX1_
ENAB
LESY
NCIN
B0+
SYNC
INB0
-
VDDA
1P1_
CLO
CK_V
CO
GPI
O_8
GPI
O_1
5VS
SD
VSSDGPIO_7GPIO_6
SYNCINB1+SYNCINB1-
GPIO_9GPIO_14
CSBSCLK
GPIO_0GPIO_3GPIO_4GPIO_5
SYSREF_IN-SYSREF_IN+
GPIO_10GPIO_13
SDOSDIO
GPIO_1GPIO_2
TEST
RESETB
GPIO_11GPIO_12
RF_S
YNTH
_VTU
NE
VDDA
1P3_
RF_S
YNTH
VDDA
1P3_
CLO
CK_S
YNTH
AUXA
DC_2
AUXA
DC_1
AUXA
DC_0
GPI
O_3
p3_1
1G
PIO
_3p3
_7
AUXA
DC_3
REF_
CLK_
IN-
REF_
CLK_
IN+
VDDA
1P3_
BBVD
DA1P
8_BB
GPI
O_3
p3_6
GPI
O_3
p3_5
GPI
O_3
p3_2
GPI
O_3
p3_1
0G
PIO
_3p3
_8
GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3
VDDA1P3_RF_LOVDDA1P1_RF_VCO
GPIO_3p3_3GPIO_3p3_0
VDDA1P3_RX_RF
VSSA
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 24: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/24.jpg)
DECOUPLING TALISE A
0201 FOOTPRINT
POSSIBLE INDUCTOR
SHARE PADS
1.3VDC
OVERLAP PADS
24 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
1.8K OHM AT 100MEGHZ
86
10UF
105
0.01UF
94
10UF
60
1UF
87
0.1UF
1UF
98
0.01UF
10UF
83
1UF
1UF
63
0.01UF 0.01UF
10UF
96
0.1UF
55
0.01UF
49
10UF
0.01UF
10UF0.1UF
0.01UF
0.01UF100UF
0
0.1UF
0
107
30OHM
100UF
104
97
470UF
119
100UF470UF
72
0.01UF
1UF
91
0.01UF
80
1.8KOHM AT 100MEGHZ34
61
0.1UF
0.1UF
106
0.1UF
108
10UF
0.175
0
66
10UF
120
31
0.01UF 0.1UF
40
69
1UF
116
0
1UF
71
0.01UF
65
122
0.01UF
99101 100
DNI
112
111
0
95
0
79
0
113
0
84
121
0
0
118
114
0
0
52
0
33
470UF
102
115
42OHM AT 100MEGHZ
0.1UF 10UF
103
1UF 0.1UF
10UF
DNI
43
1UF 10UF
32
0.01UF 0.1UF
0.1UF 0.1UF 1UF
100UF
0.01UF
53
77
1UF
9385
73
62 38 35
117
109110
747870
67
64
44 42 41
464547
28 29 30
48
92
76
1UF
1UF
0.01UF
0.1UF
51
575654
1UF
1UF
36
100UF 100UF 100UF 100UF
39
0.1UF
100UF 100UF
50
1UF
10UF0.1UF
C913 C923
C950
C940
C922
C943
C904
C905
C910
C914
C919
C915
C960
C963
C912
C957 C964 C968C954
R373
C955C951
TP10
1
C958
TP96
C920
C901
C941
E30
C961
TP102
C937
C927 C934
R371R365
R366
C898
TP97
R361
C908
C938
C939C918
C929
R372
R363
C936
C944 C946
C906
C942
TP93
R374
R368
R369
R370
R362
R364
R367
TP91
C899
E29
C903
TP89
TP12
3
C1099
TP98
TP90
TP92
TP95
TP94
TP99
C911
C1098
C953
C932
E1
C907 C916 C925
C924
C930
C935
C902 C928
L16
E28
C948 C949
C909
C926C917
C931
C962
C966
C952
TP87
TP88
TP103
C933
C921 TP100
C967C959
C945 C947 C965
C956
C900
VDDA1P3_RX_RF_A
VDDA1P3_CLOCK_SYNTH_A
VDDA1P3_CLOCK_VCO_LDO_A
VDDA1P8_BB_A
VDDA1P8_TX_A
VDD1P3_DIG_A
VDDA1P3_RF_LO_A
VDDA1P8_AVDDA1P3_RX_TX_A
VDDA1P3_AUX_VCO_LDO_A
VDDA1P3_ANLG_SNS_A
VDDA1P3_ANLG_A
VDDA1P3_SER_A
VDDA1P3_AUX_SYNTH_A
VDDA1P3_RF_VCO_LDO_A
VDDA3P3
VDD_INTERFACE_A
VDDA1P3_DES_A
VDDA1P3_BB_A
1V8
VDDA1P3_RF_SYNTH_AVDD1P3_DIG_A
21
21
1 2
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 25: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/25.jpg)
DECOUPLING TALISE B
SHARE PADS
1.3VDC
POSSIBLE INDUCTOR
0201 FOOTPRINT
OVERLAP PADS
25 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0
0
0
0
0
0
0
0
0
0
0
0
470UF
0
10UF
0.1
1UF0.1UF0.01UF
10UF1UF0.01UF
10UF
DNI
0.1UF
1.8K OHM AT 100MEGHZ
100UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
100UF 100UF
100UF
100UF100UF100UF100UF
100UF100UF
470UF1.8KOHM AT 100MEGHZ
30OHM
DNI
42OHM AT 100MEGHZ
470UF
R378
R377
R376
R384
R375
R380
R379
R388
R387
R381
R383
R382
C970
R386
R385TP11
5
C969
TP11
8
TP105
TP11
0
C1015 C1017C1011
C994C975
TP10
9
L17
C984C972
TP12
0
TP11
7
TP11
3TP
116
TP11
4TP
112
TP11
1TP
108
TP10
7
TP122TP121
TP119
TP106
C988
C1028
C1101C1100
E32
E34
E33E31
C1031 C1035
C1036
C1027
C1030C1026
C1022 C1038C1034
C1039C1037
C1032
C1033C1029C1025
C1024C1023
C1021
C1020C1019C1018C1016C1014C1012
C993
C1006
C983C974
C1013
C1010
C985C976
C1007C1000C991
C1008C1001C992
C981
C982
C1009
C1005C998
C999
C1004C997
C989
C990C980
C979
C1002C995
C1003C996
C986C977
C987C978
C971
C973
VDDA1P3_ANLG_B
VDDA1P3_RX_RF_B
VDDA1P3_CLOCK_VCO_LDO_B
1V8VDD_INTERFACE_B
VDDA1P3_AUX_SYNTH_B
VDDA1P3_RF_SYNTH_B
VDD1P3_DIG_B
VDD1P3_DIG_B
VDDA1P8_BB_B
VDDA3P3
VDDA1P8_TX_BVDDA1P8_BVDDA1P3_RX_TX_B
VDDA1P3_DES_B
VDDA1P3_SER_B
VDDA1P3_RF_VCO_LDO_B
VDDA1P3_RF_LO_B
VDDA1P3_AUX_VCO_LDO_B
VDDA1P3_CLOCK_SYNTH_B
VDDA1P3_BB_B
VDDA1P3_ANLG_SNS_B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GNDGNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 26: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/26.jpg)
LO IN/OUT
RX, ORX, LO TALISE A
ORX1 ARX1 A
RX2 A ORX2 A
26 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
HHM1595A1
SCIS00512-F
0
DNI
DNI
DNI
TCM1-83X+
TCM1-83X+
DNI
DNI DNIDNI
DNI DNI
DNI10PF
DNI DNI
DNI10PF
DNIDNI
18PF
27PF
18PF
27PF10PF
18PF18PF
27PF27PF
DNI10PF
10 8
12 11
5
4
7
1
6
DNI
DNI
TCM1-83X+
100PF
100PFDNI
DNI
0
0
3
0
9
0
2
0
0 0
0
0
0 0
0
DNI
DNI
TCM1-83X+
C364
T3C329
MRXA
R92 J10
C347
C335
C334
C351
C324 C326
C330 C332
C328
C336C338 C340
C346
C342
C350
J1 J9
J2
C325 C327 C337C339 C341
C331
C333
C345
C343 T4
T1
C344
C202 C363
T13
C365
J13 R506
R94
R91 R93
R100
R97 R99
R95
R96
R98 R101
R102
C349
C348
T2
RX2_BAL_A_N
ORX2_IN_A_P
ORX2_BAL_A_NORX2_IN_A_N
ORX1_IN_A_N
ORX1_IN_A_PORX1_UNBAL_A
RX1_BAL_A_NRX1_IN_A_N
RX1_IN_A_P
RX2_IN_A_N
ORX2_UNBAL_ARX2_IN_A_P
RX2_BAL_A_P
RX1_BAL_A_P
RF_EXT_LO_A_P
RF_EXT_LO_A_N
RX1_UNBAL_A
RX2_UNBAL_A ORX2_BAL_A_P
ORX1_BAL_A_N
ORX1_BAL_A_P
1 34
6 2 5
4
53
2
6 1
16
2
3
4
5
16
2
3
4
1
2 3
1
2 3
16
2
3
4
5
5
GND
GNDGND
GND
GND
GND
GNDGNDGND
GND
GND
GNDGND
NCNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGND
GNDGND
GNDGNDNCBALBAL
UNBAL
NC NCGND
GND GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 27: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/27.jpg)
RX, ORX, LO TALISE B
LO IN/OUT
RX1 B ORX1 B
RX2 B ORX2 B
27 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
27PF
DNI
TCM1-83X+
18PF
DNI
027PF
DNI
DNI
TCM1-83X+TCM1-83X+
DNI
DNIDNI
DNI DNI
DNI DNI
DNI
DNI
DNI
DNI
DNI
DNI
10PFDNI
DNI10PF
18PF
18PF18PF
27PF27PF
DNI
DNI10PF
TCM1-83X+
100PF
DNI100PF
HHM1595A1
0
0
0 0
0
0
0
0
0
0
0
010PF
C108
9
C1093
T12R396
J15
C1114
T15
C107
3
T10C1071
C107
2
J8 J12
J11J7
C1091
C1090
T9 T11
C1066
C1067
C1068 C1076
C1077
C1078
C1079
C1080
C1081
C1082
C1083
C1092
C107
4C1
075
C1086
C1087
C108
8
C1070 C1084
C1085
C1115 C1117
C1116
R521
R395 R397
R399
R398
R400
R401
R402
R403
R405
R404
R406
C1069
ORX2_IN_B_PRX2_BAL_B_P
RX2_IN_B_P
RX1_BAL_B_NRX1_IN_B_N
RX1_IN_B_PRX1_BAL_B_P
RX2_IN_B_N
ORX1_UNBAL_B
ORX2_UNBAL_B
ORX1_IN_B_P
ORX1_IN_B_NORX1_BAL_B_N
ORX1_BAL_B_P
ORX2_IN_B_NORX2_BAL_B_N
ORX2_BAL_B_P
RF_EXT_LO_B_P
RF_EXT_LO_B_N
RX2_UNBAL_B
RX1_UNBAL_B
RX2_BAL_B_N
2 3
1
2 3
1
1 34
6 2 5
4
53
2
6 1
4
53
2
6 1
4
53
2
6 1
5
1
4
3
2
6
1
2 3
1
2 3
GND
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
GND
GNDGNDNCBALBAL
UNBAL
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 28: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/28.jpg)
TX2 A
TX1 A
TX CHANNELS TALISE A
28 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
SCIS00511
SCIS00511
18PF
51PF
TCM1-83X+
10PF
27PF
75PF
0
0
0
0
0
0
43NHDNI
DNI
0.1UF
DNI
43NH
75PF
51PF
10PF
0.1UF
0.1UF
0.1UF
DNI
DNI
27PF
DNIDNI
DNIDNI
DNI
DNIDNI
DNI18PF
DNI
TCM1-83X+
43NH
43NH
DNI
DNI
C583 MTX2A
MTX1A
C574
C573
R202
C585
C582
C590
C594
C584
J3
R203
R201
R200
R198
R199
C577
C572
L5
L6
C588
C579
C586
L8
L7
L4
L3
C589
C587
C581C571
C591
C578
C595C593
C575
T5
T6 J4
C592
C580
C576
L1
C570
L2
VDDA1P8_TX_A
TX2_BAL_A_P
TX2_BAL_A_N
TX1_BAL_A_N
TX1_BAL_A_P
TX2_OUT_A_P
TX2_OUT_A_N
TX1_OUT_A_P
TX1_OUT_A_N
RFO1_A
RFO2_A
VDDA1P8_TX_A
VDDA1P8_TX_A
VDDA1P8_TX_A
GND2GND1
GND3GND4
GND1GND2 GND3
GND4
4
5 3
2
61
2
61
4
3 15
3 2
1
3 2
GND
GNDGNDGND
GND
GND
GNDGND
GNDGNDGND
GND
NC
NC
GND
GND
GND
GND
GND
GND GNDGND
GNDGNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 29: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/29.jpg)
TX2 B
TX CHANNELS TALISE B
TX1 B
29 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
SCIS0051143NH
SCIS00511
DNI
DNI
DNI
DNI
43NH
43NH
43NH
TCM1-83X+
DNI
DNI
DNI
DNI
DNI
DNI
75PF
75PF
51PF
51PF
27PF
27PF
10PF
18PF
DNI
DNI
DNI
DNI
0.1UF
0.1UF
0.1UF
0.1UF
104
3 9
2
5
7
8
610PF
18PF
DNI
0
0
0
0
0
1
0
TCM1-83X+
DNI
MTX1B
MTX2B
J5
J6
T7
T8
C1042
C1044
C1043
C1045
C1063
C1064
C1046
C1048
C1047
C1060
C1061
C1040
C1041
C1050
C1057
C1054
C1058
C1059
L18
L20
L19
L21
L22
L24
L23
L25
C1055
C1053
C1052
C1065
C1062
C1056
C1049
C1051
R389
R391
R390
R392
R393
R394
VDDA1P8_TX_B
VDDA1P8_TX_B
RFO2_B
VDDA1P8_TX_B
VDDA1P8_TX_B
RFO1_B
TX1_OUT_B_P
TX1_OUT_B_N
TX2_OUT_B_N
TX2_OUT_B_P
TX1_BAL_B_N
TX2_BAL_B_N
TX1_BAL_B_P
TX2_BAL_B_P
GND1GND2 GND3
GND4
GND1GND2 GND3
GND4
2
3
4
5
61
4
5 3
2
61
1
23
1
23
GND
NC
NCGND
GNDGND
GND
GNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGND
GND
GND
GND
GNDGNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 30: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/30.jpg)
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
LVPECL
LVPECL
PLACE CAPACITORS CLOSE TO FPGA
LVPECL
LVPECL
LVPECL
PLACE TERMINATION CLOSE TO TALISE
REF CLK
LVDS OR CML
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
PLACE CAPACITORS CLOSE TO FPGA
LVDS OR CML
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
LVDS HIGHPOWER OR CML 50OHM ZOUT
PLACE TERMINATIONS CLOSE TO TALISE
LVPECLPLACE TERMINATION CLOSE TO TALISE
PLACE TERMINATIONS CLOSE TO TALISE
PLACE O OHM RESISTORS CLOSE TO HMC7044
LVDS HIGHPOWER OR CML 50OHM ZOUT
HMC7044 JESD CLOCK GENERATOR
LAYOUT NOTES:
PLACE NEAR OSCILLATOR
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
PLACE PULL-UP RESISTORS CLOSE TO HMC7044
MATCH LENGTH ON ALL CLOCKS FROM HMC7044 TO AC CAP OR 0 OHM RESISTORSPLACE DECOUPLING CPAS CLOSE TO FPGA/TALISEPLACE 0 OHM RESISTORS CLOSE TO FPGA
30 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
HMC7044LP10BE
100
DNI
DNI 49.9
150150
39.2
39.2
DNI
0
150150
39.2
DNI
DNI150 150
0.1UF
100
R0201L
100
0.01UF
R0201L
DNI 680
R0201L
56.2
39.2
DNI
0.1UF
0
39.2
0.1UF
R0402L
R0201L
DNI
122.88MEGHZCVHD-950X-122.880
100PF
DNI
DNI
0
0
120OHM
10K
82PF
2.2UF4700PF
4.7UF 4.7UF 4.7UF
100
120OHM
0
0
DNI
0
0
0
100
0
4.7K4.7K
11K
10K
100
100
100
100
0.1UF
1UF 4.7UF
24
0.1UF 2200PF
4700PF
DNI
160PF
4.7UF
10UF
0.1UF
0
0
0
0
0
100PF
0
1UF 1UF
R0201L
100DNI
0.1UFDNI
24.9
DNI
24.9
0
R0402L
0.1UF
49.9
R0402L
0.1UF
49.9
0.1UF
49.9
120OHM
DNI DNI
DNI
0.1UF
0.1UF
0.1UF
100
0.1UF
R0201L0.1UF
430
100
1UF
56.2
DNI
56.2
56.2DNI 680
39.2
39.20
150150
100DNI
0
39.2
0.01UF
0.01UF
0
0.1UF
680
39.2
56.2
56.2
39.2
680
150
0.1UF
56.2150
0
39.2
56.2
56.2680
39.2
MABA-007159-000000
R0402L
DNI
0.01UF
56.2
56.2
150 150
DNI
680
56.2
0.1UF120OHM
38.4MEGHZ
E20
Y8
R576
R591R588R473
R593
R468R472
R574
R586
R573 R579
C358 C368 C370
R580
R597
R598R592
R599
R600
R603
R604
R589 R602
R605
R590 R596
R601
R455 R595
R594
R123
R577R571
C388
C387
R478
R121
R477
C382
R583
C381
C378
J14R511
C371
R463
R464
C355
E11
Y6
R103
R104
R109
R117
R423 R112
R115
C373
C352 C353
TP3
C374
R116
R118
R529
R459
R111
TP2
R105
R107
R108
C372
C356
C357 C359
TP1
U11
C354
E10
R114
R106
R460
R461
R462
C366
R507
T14
C377
R509
C369
C569 C1123
R567
R568
C1129
C1128
R113
R570
C1125
R569E35
C379
C376
R110
C385
R120
C386
R528
R119
C380
C375
R122
R476
R475R584
R578R572
R508
R512
C821
C384
R585
R471R467
C1127
R587
R581
R474R470
R510
R469
C383
C1126
C367
R582
R575
C1118
TCXO_GND
VDDA3P3_CLK
TCXO_CLK_N
VCC8_OUT
VCC4_OUT
CORE_CLK_A_P
VCC8_OUT
JESD_REFCLK_FPGA_A_P
VCC2_OUT
VCC2_OUT
REF_CLK_IN_B_N
REF_CLK_IN_B_P
JESD_SYSREF_IN_A_P
VCC9_OUT
VCXO_GND
CPOUT1
RESET_HMC7044
CLKIN3_HMC7044_P
TCXO_CLK_N
CLKIN3_HMC7044_N
TCXO_CLK_P
CLKIN2_HMC7044_P
VCC1_VCO
VCC2_OUT
OSCIN_EXT
VCXO_GND
SPI_CSN_HMC7044
CPOUT1
1V8
CLKIN0_HMC7044_P
VCC5_PLL1
VCC4_OUT
VCC7_PLL2
VCC6_OSCOUT
SYNC_HMC7044
SYNC_HMC7044_FPGA
GPIO_2_HMC7044
GPIO_4_HMC7044
SPI_CLKSPI_MOSI
VCC9_OUT
VCC8_OUT
VCC3_SYSREF
GPIO_1_HMC7044
GPIO_3_HMC7044
VDDA3P3_VCXO
CLKIN2_HMC7044_N
CLKIN0_HMC7044_N
CLKIN1_HMC7044_P
CLKIN1_HMC7044_N
TCXO_CLK_P
VCC2_OUT
OSCIN_EXT TCXO_GND
REF_CLK_IN_A_P
REF_CLK_IN_A_N
VCC9_OUT
OSCOUT1_N
OSCOUT1_P
VCC9_OUT
JESD_SYSREF_IN_A_N
JESD_SYSREF_IN_B_N
JESD_SYSREF_IN_B_P
JESD_REFCLK_FPGA_A_N
VCC4_OUT
VCC4_OUT
CLKIN2_HMC7044_N
VCC8_OUT
CLKIN2_HMC7044_P
JESD_SYSREF_FPGA_B_PJESD_SYSREF_FPGA_B_N
JESD_REFCLK_FPGA_B_P
CORE_CLK_B_PCORE_CLK_B_N
JESD_SYSREF_FPGA_A_P
JESD_REFCLK_FPGA_B_N
CORE_CLK_A_N
VCC4_OUT
JESD_SYSREF_FPGA_A_N
VCC8_OUT
1
6059
5453
42
34
24
11
14
2
37
67
39
63
3826
6
20
22
13
3
35
5
PAD
49
9
5231
66
56
28
25
16
21
33
43
68
62
41216564
55
8
4
3
48
7
12
1819
46
47
1
32
4445
50
5751
40
1710
36
23
29
61
58
4
15
27
30
2
4
3
GND
GND
GND
GND
GND
GND
GND
GND/NCOUT
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDOUTCONTROL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
SECPRI
PAD
VCC9
_OUT
CLKOUT12_NCLKOUT12
SCLKOUT13_NSCLKOUT13
GPIO4GPIO3 SCLKOUT11_N
SCLKOUT11CLKOUT10_N
CLKOUT10
VCC8
_OUT
CLKOUT8_NCLKOUT8
SCLKOUT9_NSCLKOUT9
GPIO2
VCC7
_PLL
2
CPOUT2
LDOBYP7
OSCIN_NOSCIN
LDOBYP6
OSCOUT1_N
OSCOUT1
CLKIN2_N/OSCOUT0_NCLKIN2/OSCOUT0
VCC6
_OSC
OUT
CLKIN0_N/RFSYNCIN_NCLKIN0/RFSYNCIN
VCC5
_PLL
1
CLKIN1_N/FIN_NCLKIN1/FIN
RSV
CLKIN3_NCLKIN3
CPOUT1
GPIO1
SCLKOUT7_NSCLKOUT7
CLKOUT6_NCLKOUT6
VCC4
_OUT
CLKOUT4_NCLKOUT4
SCLKOUT5_NSCLKOUT5
VCC3
_SYS
REF
SDATASCLKSLEN
VCC2
_OUT
CLKOUT2_NCLKOUT2
SCLKOUT3_NSCLKOUT3
LDOBYP5LDOBYP4
VCC1
_VCO
LDOBYP3LDOBYP2
BGABYP1
SYNCRESET
SCLKOUT1_NSCLKOUT1
CLKOUT0_NCLKOUT0
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 31: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/31.jpg)
DECOUPLING HMC7044
31 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.1UF 1UF
120OHM
0.1UF
4.7UF0.1UF1000PF
120OHM
4.7UF
120OHM
4.7UF
4.7UF
4.7UF
0.1UF1000PF120OHM
0.1UF1000PF
0.1UF1000PF120OHM
1UF
4.7UF
4.7UF
0.1UF0.01UF
1000PF
0.1UF1000PF120OHM
120OHM0.1UF1000PF
1000PF120OHM C552 C558
C549
E16
E14 TP44
E12
C556
E13
C555
C566
C567
C568
C562
TP47
C559
TP48
E17
E18
C563C560
TP49
C564C561
E19
C553
C554
C557
C547C541
C548C542
C543
TP42
TP43
C550C544
TP45E15
C551C545
C546
TP46VCC8_OUT
VCC4_OUT
VCC9_OUT
VDDA3P3_VCO VCC1_VCO
VCC5_PLL1
VCC6_OSCOUT
VCC7_PLL2
VDDA3P3_CLKVCC2_OUT
VCC3_SYSREF
VDDA3P3_CLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 32: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/32.jpg)
1.5 - 3.75V RANGE
INPUT POWER MONITORING
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT PUSH-PULL
OUTPUT PUSH-PULL
OUTPUT PUSH-PULL
PG_ALL HAS ALREADY A PULL-UP ON PAGE 6
OPEN-DRAIN SIGNALS. PULL-UPS ARE ON THE SOM.
ADDRESS 0XB0
ADDRESS 0X68
INPUT, INTERNAL PULL-UP
INPUT
INPUT, INTERNAL PULL-UP
OUTPUT PUSH-PULL
PROGRAM INTERBAL TPOR DELAY 65MS
1MS DELAY BETWEEB EN_VIN_SW AND EN_0V85_PL
ADDRESS 0X48
32 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0.1UF
BAT54XV2T1G
BAT54XV2T1G
TMP36GRTZ
100
0.1UF
29
0.0033UF
0.1UF
10UF
100UF
ADM1266-R
0.1UF0.1UF
0.1UF
BSS138LT1GBSS138LT1GBSS138LT1G
DNI
4.7K
DNI
LTST-C191KRKT
2.2K 2.2K
100
100
100
0.01
0.1UF
BSZ065N03LS
2.2KADM1177-1ARMZ
R0402L
470
0.1UF2.2K
100
100
100
LTST-C194KGKT
PCA9517DP,118
100
470
12.7K
100
LTST-C191KSKT
4.7K
4.7K
DNI
100
100
4.7K 4.7K 4.7K 4.7K
R0402L
10UF
0
00
100
470
R0402L
2.2UF
4.7K
PCA9517DP,118
0.1UF
100
10UF
0.1UF
100
100
DNI
0.1UF
100
Q6
C1097
R532
R545
C398
C1132
C1113
U47
C395
R536
C1121 C1122
U13
C390
R129R127R125R124
Q10Q9
U46
R541
R542
R131
R533
R535R534
R537R538
TP16
R137
TP6
TP14
TP15
TP18
C392
TP12
TP9
R480
DS2
U12
R138
C397
R135
TP5TP4
R134
TP7
TP8
TP10
TP19
C396
TP13
TP11
DS3
R132
DS4
C389
R424
C1096
R546 R547
TP25
TP26
R481
Q8
C393
R133
R426R427
R479
R425U39
R543
C394
D2
C565C391
R540R539
R544
R136
D1
R130
SDA_ADM1266_3V3
SCL_ADM1266_3V3
0V85_PS0V85_MGTRAVCC1V8_MGTRAVTT
EN_VIN_SWEN_0V85_PL
EN_1V8
VTEMPERATURE
3V3_ADM1266
EN_1V2_DDR4EN_3V3_2V5EN_MGTAVTT
I2C0_SDA
1V8
PG_3V3_2V5
PG_SOMPG_ALLPWR_FAULT1PWR_FAULT2
PG_DDR4
PG_ALLPG_SOMPS_DONE
EN_0V85_PS
EN_RF
EN_MGTAVCC
VIN
PG_DDR4
1V8
3V3
PG_SOM
PG_ALL
EN_VIN_SW
EN_0V85_PS
EN_0V85_PL
EN_1V8
EN_MGTAVCC
3V3
3V3
12V0
3V3
I2C0_SDA
I2C0_SCL
EN_RF
EN_MGTAVTT
3V3
EN_3V3_2V5
EN_1V2_DDR4
EN_VIN_SW
PG_3V3_2V5
PG_DDR4
VIN
12V0
I2C0_SCL
1V8
VIN
1V8
12V0
VDDA3P3_CLK
0V85_PL
PG_3V3_2V5PWR_FAULT2PWR_FAULT1
PG_SOMPG_ALL
1V8
3V3_ADM1266
3V3_ADM1266
VTEMPERATURE
VDD1P3_DIG_A
3V3
0V9_MGTAVCC1V2_MGTAVTT
VDD1P3_DIG_BVDDA1P3_ANLG_AVDDA1P3_ANLG_B
VDDA1P8_BVDDA1P8_A
5 4321
678
1
2
3
4
5
24 1211
15
49
123
4
5
678910
1314
17
18192021
22
23
252627
2829303132
333435
36
4142434647
48
505152535455565758
596061626364
PAD
16
37383940
4445
2
3
1
2
3
1
2
3
1
3
2
5
6
7
4
18
3
3
10
8746
2 9
5
1
1
4
7
6
5
2
8
GND
VCCB VCCA
GND
SCLB
SDAB
EN
SCLA
SDAA
GND GND
S
GD
GND
GND
GATESS
ADRSDASCLTIMER
GNDONSENSEVCC
GNDGND
GND
GNDSHUTDOWN_N
NC
+VSVOUT
GND
GND
GND
GND
VCCBVCCA
GND
SCLB
SDAB
EN
SCLA
SDAA
GND
GND
GND
GND
GND
GND
GPIO9GPIO8
GPIO7GPIO6GPIO5GPIO4
FWD/XTAL1REV/XTAL2
EPAD
VP8VP9VP10VP11VP12VP13
PDIO6PDIO7PIDO8PDIO9
PDIO10PDIO11PDIO12PDIO13PDIO14PDIO15PDIO16
SCLSDASYNCID_SCLID_SDA
DVDD
_CAP
GPIO3GPIO2GPIO1
PDIO1PDIO2PDIO3PDIO4PDIO5
VP1VP2VP3VP4
AVDD
_CAP
GND
VH1
VH2
VH3
VH4
ADDR
DAC9DAC8DAC7DAC6DAC5DAC4DAC3DAC2DAC1
REFG
ND
REFOUT
VP5VP6VP7
GNDGNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 33: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/33.jpg)
0.85V, 40A
0V85 PL
60DEG PHASE
400KHZ
FORCED CONTINUOUS MODE
33 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0 0
0
0
22UF 22UF
22UF
22UF22UF22UF22UF 22UF
DNI
10K
10K
15K
DNI
37.4K
30.1K
22PF
DNI
100PF
4.7UF
100UF
2200PF2.2
LTM4636-1IY#PBF
0.1UF
100UF
12K
100UF 100UF 100UF 100UF 100UF 100UF 100UF
R554 R186
R179
R185
C452
C460
C459C458C457C450 C454C451
R177
R181
R178
R184
R176
R183
R182
C467
C453
C455
C461
C463
C456R180
TP27 TP28
C466
TP29
C462
R187
C464 C465 C468 C469
U15
C470 C471 C472
TP30
CLKOUT_400K_1
12V0
12V0
INTVCC_LTM4636
EN_0V85_PL
PVCC_LTM4636
0V85_PL_FB
0V85_PL_FB
PVCC_LTM4636 INTVCC_LTM4636
0V85_PL_SNS_P
0V85_PL_SNS_N
0V85_PL
J11
G12
M3
H4
C12D6
H8
H10
H11
H12
F5H2H9
D7 D8 D9 E6 E7
H3
G11G9
F1F2
G8G7
E11
F3F11D10
E12
E10
E5D5E2E4
L11
G5K11
M7M8
M6
L7L8M4M5
L6
K6K7K8L4L5
J5J6J7K4K5
J4H6H5
E8 E9 F7 F8 F10
F12
G1
G2
G6
G10 H1 J1 J2 J3 J8 J9 J1
0
J12 K1 K2 K3 K9 K10
K12 L1 L2 L3 L9 L10
L12
M1
M2
M9
M10
M11
M12 F4 G4
H7G3E3
D3D4
E1
D12D11D2D1
C11C10C9C8C7C6C5C4C3C2C1B12B11B10B9B8B7B6B5B4B3B2B1A12A11A10A9A8A7A6A5A4
F9 F6
A3A2A1
GND
GND
GNDGND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
SW_2
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
SW_1
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVIN
GND
GND
GND
GND
GND
GND
GMONTMON
PWN
VINVIN
TEST1
MODE/PLLIN
TEST3
GND
TEMP+TEMP-
GND
BIASRUNPPHMODE
GND
FREQ
SGND
CLKOUT
GND
GND
GND
OTP_SET
GND
PVCC
GND
GND
INTVCC
TEST2
SGND
HIZREG
SNSP1SNSP2
OVP_SET
CROWBAROVP_TRIP
GND
GND
GND
GND
COMPA
VFB
TRACK/SS
RUNC
PGOOD
VOUTVOUT
OVER_TEMP
GND
GND
GND
GND
COMPB
VOUTS1+VOUTS1-
VOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 34: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/34.jpg)
0V85 PS, 1V8
INTERNAL PULL-UP
400KHZ
60DEG PHASE
1.8V, 4A
0.85V, 6A
34 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
0
12
26
68PF
68PF
15
22UF
40
22UF
41
22UF
39
22UF
37 36
22UF
38
22UF 22UF
42
11
143K
30.1K
25
17
DNI
23
100K
DNI
17
DNI
DNI
14
44
2200PF10
2200PF
LTM4628IY#PBF
0.1UF0.1UF
24
9
2.2
2.2
13
100UF
43
100UF 100UF
22 19
21
100UF 100UF
31
28
33DNI
16
4.7UF
1
45
100UF
35
100UF
30
100UF
29
100UF
46
DNI
100UF
34
20
27
R194
C482
C481
C485C483C473 C474 C475 C478 C484
C476
R191
R555
R190
C497
R193
C477
C479
C480
C498
C486
R189
R188
C488 C490 C492 C494 C496
TP32
U16
C487 C489 C491 C493
TP31
C495
TP33
R192
0V85_PS_SNS_P
1V8
12V0
0V85_PS
CLKOUT_400K_2
EN_0V85_PSEN_1V8
CLKOUT_400K_1
0V85_PS_SNS_N
12V0
1V8
0V85_PS
E9E3 E1
2
G9
D5
G11
F9G2
F5F4
E8E7E6D7
C6
M11M10M9M8M7M6M5M4M3M2
L11L10L9L8L7L6L5L4L3L2
K11K10K9K4
A6 B6A7 D1B7 D2 D4D3 D9 D11
D10 E1D12 E2 E4 E11
E10 F2F1
K3
J11K2
J10J9J4J3J2
F10F3 F11
G1
F12
G12
G10G3 H2H1 H3 H5H4 H7H6 H9 H11
H10 J1
H12 J5 J12J8 K5K1 K6 K8K7 L12L1K12
M12M1 D6C7 F6 G7
G6F7
G4
J6
G8
G5
D8E5
F8
C5C8
C12
C9
C11C10
B12B11
B9B8
B10
A12A11
A9
C4
A8
A10
C3
C1C2
B4B5
B3
H8 J7
B1B2
A4A5
A3A2A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVIN
GND
GND
GND
GND
VINVINVIN
GND
GND
VINVINVIN
GND
EXTVCC
TEMP
GND
VINVINVIN
GND
GND
GND
GND
GND
ITNVCC
GND
GND
GND
GND
GND
GND
GND
GND
SW2
GND
PGOOD1PGOOD2
SGND
SGND
CLKOUT
PHASMD
GND
SW1
GND
GND
GND
GND
RUN2
DIFFOUT
SGND
SGND
RUN1MODE_PLLIN
GND
GND
GND
GND
GND
GND
DIFFNDIFFPCOMP2COMP1
TRACK1
GND
GND
GND
GND
GND
GND
GND
GND
TRACK2VFB2
SGND
VFB1
GND
GND
GND
GND
VOUT2VOUT2VOUT2VOUT2
VOUTS2
SGND
FSET
VOUTS1
VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 35: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/35.jpg)
0.85V, 1A
1.8V, 1A
MGTRAVCC, MGTRAVTT
35 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
22UF
17
10UF
1DNI
2
10UF
16
10UF
30.1K
143K
10PF
10PF14
20
47UF
4
47UF
DNI
47UF
47UF
LTM4622IY#PBF
3
8
5
1315
6
DNI
11
DNI
22
DNI
21
DNI7
DNI
0.1UF
47UF
47UF
0.1UF
9
12
2.2UF
C636 C637 C641C638
R216
C640
R215
C639
C648
C644 C647
TP57
TP58
C645C642
R218
U20
C650
C646C643
C651
R217
C649
C652
1V8_MGTRAVTT
0V85_MGTRAVCC
1V8_MGTRAVTT
0V85_MGTRAVCC
EN_MGTAVTT
12V0
INTVCC_LTM4622_1
EN_MGTAVCC
INTVCC_LTM4622_1
A3E3
A2
E5A5
E4A4
C4
B5 C1 C2 D5
C3
D4B4
D2B2
C5
B3
E2
D1E1
B1D3 A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN1
VOUT1
GND
PGOOD1
VIN1
RUN1
VOUT1
SYNC/MODE
FREQ
INTVCC
GND
GND
GND
PGOOD2
VIN2
RUN2
VOUT2
COMP2
FB2
TRACK/SS2
VIN2
VOUT2
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 36: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/36.jpg)
60DEG PHASE
INTERNAL PULL-UP
1.2V, 6A
0.9V, 6A
MGTAVCC, MGTAVTT
400KHZ
36 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
35
DNI
100UF 470UF
470UF
17
68PF
23
68PF
25
4
22UF 22UF
9 2
22UF22UF
3 6
22UF 22UF
7
22UF
8
DNI
DNI
29
LTM4628IY#PBF
36DNI
100UF
R0402L
121K
21
11
60.4K
R0402L
2200PF13
100UF 100UF
2737
32
100UF100UF
33
100UF
16
2200PF2.2
2.212
14
31
26
0.1UF
19
34
15
4.7UF
5
10 17
30
0.1UF
DNI
DNI
24
22
20
100K
18
100UF100UF
1
28
100UF
C1130
C1131C628
C631 C633
TP54
C618
C619
C611 C612 C615C610 C620 C621 C622
R556
R213
C632
R209
R211
R212
C613
C626C624
C629
TP53
C616
C617R210
C625
C634
C623
U19
TP55 TP56
C635C614
R214
C627
C630
0V9_MGTAVCC
1V2_MGTAVTT
12V0
12V0
0V9_MGTAVCC_SNS_P0V9_MGTAVCC_SNS_N
CLKOUT_400K_2
EN_MGTAVCCEN_MGTAVTT
1V2_MGTAVTT
0V9_MGTAVCC
H7 J1
J6
G4
G8G9
E5
G6K8
F9G2
F5
D7
M1 C7M
12
C8C5
F8
L11
B3
A10
G11
F4
E6E7E8
C6
M10M11
M9
A7A6 B6 D1B7 D3D2 D4 D10D9
M7M6M5M4
M2
L10L9L8L7L6L5L4L3L2
K11K10K9K4K3K2
J11J10J9J4
J2J3
D12
D11 E1 E3E2 E11
E10E4 F1E12 F2 F10F3 F12
F11
G1
G10G3 H1G
12 H2 H4H3 H6H5 H10H9 H12
H11 J8J5 J12 K5K1 K7K6 L1K12
L12 D6 F7F6 G7
D8
G5
C12C11C10C9B12B11B10B9B8A12A11
A9A8
C4C3C2
B5B4
H8 J7
B2
A4A3
A1A2
M3
D5
M8
A5B1
E9
C1
GND
GND
GNDGND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVIN
GND
GND
GND
GND
VINVINVIN
GND
GND
VINVINVIN
GND
EXTVCC
TEMP
GND
VINVINVIN
GND
GND
GND
GND
GND
ITNVCC
GND
GND
GND
GND
GND
GND
GND
GND
SW2
GND
PGOOD1PGOOD2
SGND
SGND
CLKOUT
PHASMD
GND
SW1
GND
GND
GND
GND
RUN2
DIFFOUT
SGND
SGND
RUN1MODE_PLLIN
GND
GND
GND
GND
GND
GND
DIFFNDIFFPCOMP2COMP1
TRACK1
GND
GND
GND
GND
GND
GND
GND
GND
TRACK2VFB2
SGND
VFB1
GND
GND
GND
GND
VOUT2VOUT2VOUT2VOUT2
VOUTS2
SGND
FSET
VOUTS1
VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
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REPLACE 0.1%
3.3V, 0.75A
2.5V, 0.75A
3V3, 2V5 VPP_DDR
37 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
LTM4622IY#PBF
10UF
21DNI
8
10UF10UF
10PF
19.1K
13.3K
10PF
DNI
2.2UF
216
6
100K
20
DNI22
649K
12
DNI
19
DNI
15
11
13
4
7
5
0.1UF 0.1UF
47UF 47UF
DNI
47UF 47UF
DNIC596 C600C597
R206
C599
R205
C598
R204
C609
R207
R208
C604C601
TP52
TP51
C608C607
C605C602
C606C603U40
2V5_VP_DDR4
PG_3V3_2V5
2V5_VP_DDR4
3V3
3V3
EN_3V3_2V5
12V0
INTVCC_LTM4622_2
12V0
INTVCC_LTM4622_2
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5 C1 C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5COMP1
FB1
TRACK/SS1
VIN1
VOUT1
GND
PGOOD1
VIN1
RUN1
VOUT1
SYNC/MODE
FREQ
INTVCC
GND
GND
GND
PGOOD2
VIN2
RUN2
VOUT2
COMP2
FB2
TRACK/SS2
VIN2
VOUT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 38: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/38.jpg)
0.6V, 3A
1.2V, 3A
1.2V, 3A
DDR4 SUPPLIES
0.6V, 3A
38 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
22UF
36
32
22UF22UF
8
22UF
5
22UF
2
22UF
9
10UF
26
10UF
10UF10UF
1UF
0.1UF
4.7UF
100UF
100UF
15
4.7UF
100K
LTM4632IY#PBF
LTM4632IY#PBF
100UF
100UF
100UF
100UF
100UF
0.1UF
1UF
1UF
4.7UF
4.7UF4.7UF
4.7UF
DNIDNI 4700PF
4700PFDNIDNI
37
19 20
17
2 313
2322 18
8
5
24
6
1
25
DNI21
100UF
4.7UF
100UF
412
4.7UF
1614
1UF
60.4K
0.1UF
100UF
7
R0402L
60.4K
0.1UF
100PF
100PF
C503
C504C500 C502
C501C499 C505 C509
C510C507
C1119 C515
C514 C523
C535C528
TP37
C539
C513
C1120
U17
C527 C533
C536
C522
C516C511 C521
C537
C540C538C532C526
C517
C518
C530
C524
C519
C520C512
TP35
R195
R196
TP40 TP41
C531
TP38
C525
C529
TP34
TP36
C534
R197
C508
U18
C506
TP39
1V2_PS_DDR4
1V2_PS_DDR4
VREF_PS_DDR4
12V0
1V2_PL_DDR4
PG_DDR4
12V0
VTT_PS_DDR4
1V2_PS_DDR4
EN_1V2_DDR4
PG_DDR4
VTT_PL_DDR4
VREF_PL_DDR4
12V0
1V2_PL_DDR4
1V2_PL_DDR4
EN_1V2_DDR4
E4A4
E3
A1E1
E5A5
B5 C4
C3
D4B4
D2B2
C5
A2B3D3E2
D1
B1
A3
E5A5
B5
C4D5
C3
D4B4
D2B2
C5
E3
A4
D3E1A1B1
A3
D1
E4
B3
E2
A2
C1 C2
D5C2C1
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
GND
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
VDDQIN
VTTR
VIN
VOUT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
GND
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
VDDQIN
VTTR
VIN
VOUT2
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 39: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/39.jpg)
1.65V, 3A
3.8V, 2.5A
1.3V, 3A
2.65V, 1A
6.34K | 31.6K | 12.7K10.7K | 38.3K | 23.2K R350 | R348 | R349
WITHOUT LDOSWITH LDOS
RF SUPPLIES
CLKOUT ON SYNC/MODE
39 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
2
40
0.1
47UF120OHM
29
47UF47UF
0.1
470OHM
47UF47UF47UF
47UF
470OHM31.6K
0.1UF 10.7K
20
10K
23
42
22
47UF
37
47UF47UF
47UF
5267
0
0
54
0
0
63
0
0.01UF
51
62
0.01UF
0.01UF
24
0.0027UF
69
0.0027UF
25
0.01UF
470OHM
49
10UF
1
10UF
68
10UF
27
10UF
ADP5054ACPZ
10.2K
0.1
48
23.2K
56
38.3K
10.7K
DNI37.4K
27.4K DNI
55
46
6.34K
33
47K DNI
DNI32
47K
DNI
43
20K
61
20K
16
10K
66
10K
26
DNI
7147K
64
100K
65
DNI
70100K
73
47K
72
DNI
100K
59
604K
60
100K
74
DNI
47
10K
10K
53
10K
44
19
2.2UH
2.2UH
17
21
0.1UF
6.8UH
SIA906EDJ-T1-GE3
28
8
5
38
34
39
1UF
13
1UF
12
0.0033UF
58
0.0033UF
15
6
3
11
0.1UF
0.47
6.8UH
10
0.1UF
47UF
22UF
57
47UF
775
30 31
35
36
50
4
18
E24
R356
C895
TP86
C891
R358
E25
C893
R357
E27
C887
R337
R340
R350
R344 C880
C886
TP64
R331R327
R346
R347
R345
C883
C881
C872
C871
C882
E26
C868
C869
C866
C867
C896
R349
R348
R354
R355
R353
R341
R351
R335
R334
R333
R332
R322
R324 R328
R323
R329R325
R339
R330R326
R336
R352
R343
R342
R338
L13
L12
L15
TP84
L14
C894
C888
C889
C890
C870
C875
C874
C873
C897
C876
C878
U45
R359
C877
TP82
TP85
TP83
TP66TP65
C885
C879
TP63
C884
C892
Q1
VDDA3P8
CLK_ADP5054
VDD1P3_DIG_A
VDDA2P65_A
VDDA1P65_ANLG_A
VREG_ADP5054_A
VDDA1P3_ANLG_A
VREG_ADP5054_A
EN_RF
VDD1P3_DIG_A
12V0
EN_RF
EN_RF
VREG_ADP5054_A
23 2726
PAD1
45
37
47
3
29
6
4
25
14
17
3
PAD2
2 51
4
32
28
1
12
18
13
40
20
15
3139
21
48
41
19
46
16
30
2
1011
36
38
22
24
6
7
42
333435
5
89
44
43
PAD
GND
EPAD
EN3
COMP3
FB3
VREG SYNC/MODE
VDD RT
FB1
COMP1
EN1
PVIN1PVIN1PVIN1
SW1SW1SW1
BST1
DL1
PGND
DL2
BST2
SW2SW2SW2
PVIN2PVIN2PVIN2
EN2
COMP2
FB2
CFG12
PWRGD
FB4COMP4
EN4
CFG34
BST4
PGND4PGND4
SW4SW4
PVIN4
PVIN3
SW3SW3
PGND3PGND3
BST3
D2
D1
S2G2
D2
S1G1
D1
GNDGND
GNDGND
GNDGNDGND
GND GND GND GNDGND
GNDGNDGNDGND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Page 40: CONTROL CODE DEVICE FUNCTION CONNECTOR PG2 SOM … · 2020-03-06 · PG3 SOM INTERFACE 1 41 : Pitch-pitch StyleVendor Style](https://reader034.fdocuments.net/reader034/viewer/2022042805/5f67fb2f7a2de9649c35a691/html5/thumbnails/40.jpg)
2.65V, 1A
1500MA
R314 | R313
6.34K | 12.7K10.7K | 23.2K
WITHOUT LDOSWITH LDOS
RF SUPPLIES
CLKIN ON SYNC/MODE
1.3V, 3A
1.65V, 3A
40 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
SIA906EDJ-T1-GE3
0.1
23.2K
47UF
51
120OHM
57
47UF 65
53
6.8UH
0.47
47UF
47UF
47UF
3
58
9
5
46
7
64 66
61
69
68
72 73
4
47UF
10.1UF
0.1UF
39
1UF
1UF
38
29
37
56
0.1UF
52
22UF
48
2.2UH
54
50
2.2UH44
10.2K
10K
25
DNI
45
10K
DNI
20
DNI
15
6.34K
49
20K
28
21
47K 100K
22
47K
17 18
100K
24
DNI
20K
40
19
10K
10K
33
DNI59
47K
47K60
DNI
34
10K
14
DNI27.4K
DNI
62
10.7K
200K
23
499K
2
55
10.7K
13
ADP5054ACPZ
0.0033UF
0.0033UF
10UF
32
10UF
10
10UF
11
6
10UF
8
470OHM
0.0027UF
12
41
0.0027UF
0.01UF
31
27
0.01UF
36
0.01UF
0
30
0
26
0
35
0
16
47UF
63
47UF
0.147UF
4747UF
31.6K470OHM
R313
E21
C860
E23
C851
L11
R321
C857
C856
Q7
TP60
TP59
TP61 TP62
U44
R319
C865
TP80
TP81
TP79C850
C848
C843
C847
C846
C858
C862
C849
C859
L9
L10
R305
R309
R318
R291
R290
R316
R303
R293 R297
R292 R296
R299
R302
R301
R300
R308
R307
R306
R317
R315
R294 R298
R314
C842
C841
C840
C839
E22
C845
C844
C854
C853
C852
R312
R311
R310
R295
C863C855
R320 C864
C861
R304
VDDA1P65_ANLG_B
VREG_ADP5054_B
EN_RF
VDD1P3_DIG_B
EN_RF
EN_RF
VREG_ADP5054_B
12V0
VDDA1P3_ANLG_B
VDD1P3_DIG_B
VREG_ADP5054_B
CLK_ADP5054
VDDA2P65_B
PAD1
3
PAD2
2 51
4
6
GND GNDGNDGNDGND
GND
GND
GNDGND
GND
GND
GNDGND
GND
GND
GND
EPAD
EN3
COMP3
FB3
VREG SYNC/MODE
VDD RT
FB1
COMP1
EN1
PVIN1PVIN1PVIN1
SW1SW1SW1
BST1
DL1
PGND
DL2
BST2
SW2SW2SW2
PVIN2PVIN2PVIN2
EN2
COMP2
FB2
CFG12
PWRGD
FB4COMP4
EN4
CFG34
BST4
PGND4PGND4
SW4SW4
PVIN4
PVIN3
SW3SW3
PGND3PGND3
BST3
GNDGND
GND
D2
D1
S2G2
D2
S1G1
D1
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
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RF SUPPLIES - LDO
3.3V, 0.4A
1.8V, 0.6A
1.3V, 3A
3.3V, 0.4A
3.3V, 2A
3.3V, 0.4A
1.3V, 3A
1.8V, 0.6A
41 41
<DESIGN_VIEW>
: Product(s): ADRV9009HW TYPE : Customer Evaluation Z
1:1
C02_048949
C. GOGA
ADP1763ACPZ-1.3
ADP7158ACPZ-3.3-R7
ADM7154ACPZ-1.8
0.1UF 1UF10UF
R0603L
DNI
DNI
1UF0.1UF
ADM7154ACPZ-3.3
1UF
DNI
DNI
10UF
DNI
0
0
0
0
0
0
0
4.7UF 4.7UF
0.01UF1UF
10UF 1UF
10UF 1UF
10UF 1UF
10UF
10UF
ADP124ACPZ-3.3
22UF
ADM7154ACPZ-3.3
10UF
1
0.01UF DNI
10UF
1UF
DNI
1UF
10UF 1UF
22UF
0.1UF
7ADM7154ACPZ-1.8
8.66K
8.66K
1UF0.1UF
0.1UF1UF
10UF
22UF 22UF
10UF
ADP1763ACPZ-1.3
1UF
22UF 22UF
2
10UF
2
3
10UF
5
10UF
6
1UF
1
1UF
3
5
6
C801
C810
TP70
C814
C833
JP3
M3 M4M2 M6M5M1TP74TP73TP72
R497
R495
R494
R496
C838
C361
R492
R491
R488
U22
R490
R493
R489
R530
R531
JP8
TP71
C797
JP7
JP6
JP5
TP50
TP130
C820 C823
C819 C822
C827
TP75
C824
JP2
JP4
C816
C832
TP76
C828
C798
TP67
C804
C796
U23
C806
R287
C800
C805
JP1
TP68
C811
C812C803
R288
U26
C830
C829
C834
C362
U24
U28
TP77
C835
U25
C837
TP78
C825
C831 C836
U27
C817
C809 C815
C818
U43
C807
C813
C802 C808
TP69
C795
C826
C799
VDDA1P3_ANLG_B_N
VDDA3P8VDDA3P3
VDDA3P3_VCO_N
VDDA3P3_VCO_P
VDDA3P8
VDDA1P3_ANLG_B_P
VDDA3P3_VCXO
VDDA2P65_A
VDDA1P3_ANLG_B
VDDA3P3_VCXO_N
VDDA1P8_A_P
VDDA1P8_A_N
VDDA1P8_A
VDDA3P3_VCXO
VDDA2P65_B
VDDA3P8
VDDA3P8
VDDA3P8
VDDA3P8
VDDA3P8
VDDA1P65_ANLG_A
VDDA1P8_B
VDDA1P3_ANLG_A_N
VDDA3P3
VDDA1P3_ANLG_A
VDDA3P3_CLK
VDDA1P3_ANLG_SNS_A
VDDA1P65_ANLG_B
VDDA2P65_A
VDDA3P3_VCO
VDDA1P65_ANLG_B
VDDA1P3_ANLG_SNS_B
VDDA1P3_ANLG_A_P
VDDA2P65_B
VDDA3P3_P
VDDA3P3_N
VDDA3P3_VCXO_P
VDDA3P3_CLK_P
VDDA3P3_CLK_N
VDDA3P3_VCO
VDDA1P65_ANLG_A
VDDA3P8
VDDA3P3_CLK
VDDA1P3_ANLG_B
VDDA1P8_B_P
VDDA1P8_B_N
VDDA1P8_B
VDDA1P8_A
VDDA1P3_ANLG_A
15
13
2
PAD
12
3
4
5
67
8
910
PAD
123
4
56
78
PAD
1
7
1
137
PAD
10
12
13
3 2
16
7
4
5
PAD4 6
8 23
1
2
16
7 PAD
5
14
8
1 2 3 4
9
11
6
15
4
7
5
14
8
1 2 3 4
9101112
6
PAD
68
8
3576
4
5
85
PAD
6
GND GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
PAD
EN
PG
SS
SENSEVOUTVOUTVOUTVOUT
VADJ
GND
VREG
REFCAP
VIN
VIN
VIN
VIN
GND GND
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GNDGND
GND
GND
EP
VINVIN
NC
EN
GND
VOUT_SENSEVOUTVOUT
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
GND
GND
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
EP
VINVIN
VREG
REFREF_SENSE
EN
BYP
VOUT_SENSE
VOUTVOUT
GND
GNDGNDGND
GND
GND
GND
GND
GND
GND
PAD
EN
PG
SS
SENSEVOUTVOUTVOUTVOUT
VADJ
GND
VREG
REFCAP
VIN
VIN
VIN
VIN
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
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