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Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-1
Chapter # 3: Multi-Level Combinational Logic3.3 and 3.4 -- Time Response and
Hazards / Glitches
Timing Issues
Chapter # 5: Arithmetic Circuits5.2 -- Networks for Binary Addition
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-2
Networks for Binary Addition1. Half Adder -- Review
With twos complement numbers, addition is sufficient
Ai 0 0 1 1
Bi 0 1 0 1
Sum 0 1 1 0
Carry 0 0 0 1
AiBi
0 1
0
1
0 1
1 0
Sum = Ai Bi + Ai Bi
= Ai + Bi
AiBi
0 1
0
1
0 0
10
Carry = Ai Bi
Half-adder Schematic
Carry
Sum A i
B i
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-3
Networks for Binary Addition
2. Full Adder -- Review
+
A3 B3
S3
+
A2 B2
S2
+
A1 B1
S1
+
A0 B0
S0C1C2C3
Cascaded Multi-bit Adder
usually interested in adding more than two bits
this motivates the need for the full adder
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-4
Networks for Binary Addition
Full Adder
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
CI 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
CO 0 0 0 1 0 1 1 1
A BCI
0
1
00 01 11 10
0
1
1
0
1
0
0
1
A BCI
0
1
00 01 11 10
0
0
0
1
0
1
1
1
S
CO
S = CI A B
CO = B CI + A CI + A B = CI (A + B) + A B
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-5
Networks for Binary Addition
Full Adder/Half Adder
A
AA
B
BB CI
CIS CO
Alternative Implementation: 5 Gates -- cascading half adders
Half Adder
A
B
Half Adder
A + B
CI
A + B + CIS S
COCOCI (A + B)A B
S
CO
A B + CI (A xor B) = A B + B CI + A CI
Standard Approach: 6 Gates
+
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-6
Networks for Binary Addition
3. Adder/Subtractor
A - B = A + (-B) = A + B + 1
A B
CO
S
+ CI
A B
CO
S
+ CI
A B
CO
S
+ CI
A B
CO
S
+ CI
0 1
Add/Subtract
A 3 B 3 B 3
0 1
A 2 B 2 B 2
0 1
A 1 B 1 B 1
0 1
A 0 B 0 B 0
Sel Sel Sel Sel
S 3 S 2 S 1 S 0
Overflow
Control = 0 ==> AddControl = 1 ==> Subtract
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-7
• For the adder circuit, Ai and Bi are summed in parallel. Bu for Si to be correct, the adder requires serial propagation of the carry outputs from the right most lowest-order stage to the left-most highest order stage. The rippling of the carry from one stage to another determines the adder’s ultimate delay.
Networks for Binary Addition
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-8
Networks for Binary Addition4. Carry Lookahead Circuits
A
A
B
B
CI CO
@0@0
@0@0
@N
@1
@1
@N+1
@N+2
Critical delay: the propagation of carry from low to high order stages
latearrivingsignal
two gate delaysto compute CO
Assume the adder stages are implemented as the ‘S’ and ‘CO’ circuits onprevious slide and all gates have the same delay. For the ‘S’ circuit,
At time 0, Ai, Bi, and CI are presented to the adder. Within 2 gatedelays, one delay for each XOR gate, S0 will be valid
For ‘C0’ circuit,Ai=Bi=1, the carryout is computed in two gate delay and independentof the carry-in ==> C0 always = 1Ai=Bi=0, the carryout is computed in two gate delay and independentof the carry-in ==> C0 always = 0AiBi, the calculation of the carry out takes three gate delays (C0depends on the CI)
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-9
Networks for Binary Addition
Carry Lookahead Circuits
Critical delay: the propagation of carry from low to high order stages
4 stageadder
final sum andcarry
A 0
B 0
C 0
S 0 @2
A 1
B 1
C 1 @2
S 1 @3
A 2
B 2
C 2 @4
S 2 @5
A 3
B 3
C 3 @6
S 3 @7
C 4 @8
0
1
2
3
Addition for worst case:
1111 + 00012 2
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-10
Networks for Binary AdditionCarry Lookahead Circuits
Critical delay: the propagation of carry from low to high order stages
1111 + 0001worst case
addition
T0: Inputs to the adder are valid
T2: Stage 0 carry out (C1)
T4: Stage 1 carry out (C2)
T6: Stage 2 carry out (C3)
T8: Stage 3 carry out (C4)
T0 T2 T4 T6 T8
S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-11
• 8 gate delay seems acceptable for a 4-bit adder
• Cascaded delays become intolerable for adders of greater widths, such as 32 or 64 bits
• A 32 stage adder (32 bits) take 64 gate delays to final stage carryout
• Led to carry look ahead schemes
• Ways to calculate the carry inputs in parallel rather than in series. So that it will never take more than 2 gate delays to compute any of the carry outputs.
Networks for Binary AdditionCarry Lookahead Circuits
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-12
Networks for Binary Addition
Carry Lookahead Logic -- General
Carry Generate Gi = Ai Bi must generate carry when A = B = 1
Carry Propagate Pi = Ai xor Bi carry in will equal carry out here. This[asses propagates the carry across thestage
Si = Ai xor Bi xor Ci = Pi xor Ci
Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + Ci (Ai + Bi)
= Ai Bi + Ci (Ai xor Bi)
= Gi + Ci Pi
Sum and Carry can be reexpressed in terms of generate/propagate:
We introduce 2 new functions,
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-13
Networks for Binary Addition
Carry Lookahead Logic
Reexpress the carry logic as follows:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
Each of the carry equations can be implemented in a two-level logic network
Variables are the adder inputs and carry in to stage 0 (C0)!
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-14
Networks for Binary Addition
Carry Lookahead Implementation
Adder with Propagate and Generate Outputs
Pi @ 1 gate delay
Ci Si @ 2 gate delays
BiAi
Gi @ 1 gate delay
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-15
Networks for Binary Addition
Carry Lookahead Implementation
Increasingly complex logic
C0C0
C0
C0P0P0
P0
P0
G0G0
G0
G0
C1
P1
P1
P1
P1
P1
P1 G1
G1
G1
C2P2
P2
P2
P2
P2
P2
G2
G2
C3
P3
P3
P3
P3
G3
C4
When Pi and Gi are available, the subsequent C1, C2, C3, C4 are computedafter two more gate delays (3 gate delays total).The sum bits can be computed in just one more gate delay.
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-16
Networks for Binary Addition
Carry Lookahead Logic
5. Cascaded Carry Lookahead
Carry lookaheadlogic generatesindividual carries
sums computedmuch faster
A 0
B 0
C 0
S 0 @2
A 1
B 1
C 1 @3
S 1 @4
A 2
B 2
C 2 @3
S 2 @4
A 3
B 3
C 3 @3
S 3 @4
C 4 @3
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-17
Networks for Binary Addition
Carry Lookahead Logic
Cascaded Carry Lookahead
4 bit adders with internal carry lookahead
second level carry lookahead unit, extends lookahead to 16 bits
4-bit Adder
4 4
4
A [15-12] B [15-12] C 12 C 16
S [15-12]
P G 4-bit Adder
4 4
4
A [1 1-8] B [1 1-8] C 8
S [1 1-8]
P G 4-bit Adder
4 4
4
A [7-4] B [7-4] C 4
S [7-4]
P G 4-bit Adder
4 4
4
A [3-0] B [3-0] C 0
S [3-0]
P G
Lookahead Carry Unit C 0
P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C 3 C 2 C 1
C 0
P 3-0 G 3-0
C 4
@3 @2
@0
@4
@4 @3 @2 @5
@7
@3 @2 @5
@8 @8
@3 @2
@5
@5 @3
@0
C 16
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-18
Networks for Binary Addition6. Carry Select Adder
Redundant hardware to make carry calculation go faster
compute the high order sums in parallel
one addition assumes carry in = 0
the other assumes carry in = 1
4-Bit Adder [3:0]
C 0 C 4
4-Bit Adder [7:4]
0 C 8
1 C 8
4 ¥ 2:1 Mux
0 1 0 1 0 1
4-Bit Adder [7:4]
C 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0
0 1
C 4
Adder High
Adder Low
C8 is selectedfrom adder highwhen C4=1and Is theAND of the carries of adder lowand high when C4=0.
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-19
3.3 Time Response in Combinational Networks• emphasis on timing behavior of circuits
• waveforms to visualize what is happening
• simulation to create these waveforms
• momentary change of signals at the outputs: hazards can be useful— pulse shaping circuits can be a problem — glitches: incorrect circuit operation
Terms:
gate delay— time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case!
rise time— time for output to transition from low to high voltage
fall time— time for output to transition from high to low voltage
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-20
Time Response in Combinational NetworksGate Delays for Typical TTL Families
Various families of TTL exhibit tradeoffs between delay and power.Faster a component, the more power it consumes.
Delays depend on whether a gate is going from low to high or high to low.
TTLcomponent
Maximum Typical
tpHL(ns)
tbLH(ns)
tpHL(ns)
tpLH(ns)
7400 15 22 7 11
74H00 10 10 6.2 5.9
74L00 60 60 31 35
74LS00 15 15 10 0
74S00 5 4.5 3 3
74LS02 15 15 10 10
74LS86A 22 30 13 20
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-21
Time Response in Combinational NetworksPulse Shaping Circuit -- It generates a periodic sequence of pulses.
A' • A = 0
F is not always 0!
3 gate delays (corresponding to the 3 inverters)
D remains high forthree gate delays after
A changes from low to high
A changeat its inputcauses a shortduration pulse atthe output
Each gate has propagation delayof 10 time units
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-22
Time Response in Combinational Networks
Hazards/Glitches and How to Avoid Them
Glitch -- unwanted pulse at the output of a combinational logic network.
Hazard -- a circuit with the potential for a glitch is said to have a hazard.Occur because delay paths through the circuit experience different propagation delays
Danger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock)
Usual solutions: wait until signals are stable (by using a clock)
never, never, never use circuits with asynchronous inputs
design hazard-free circuits
Suggest that first two approaches be used, but we'll tell you about hazard-free design since some components unavoidably have asynchronous inputs.
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-23
Time Response in Combinational NetworksHazards/Glitches and How to Avoid Them
Kinds of Hazards
Input change causes output to go from 1 to 0 to 1when it should have remained at 1.
Input change causes output to go from 0 to 1 to 0when it should have remained at 0.
Output signal has the potential to change more thanonce when it is expected to make a single transitionfrom 0 to 1 OR from 1 to 0 .
Static 0-hazard
Dynamic hazards
Static 1-hazard
1 1
0
1
0 0
1
0 0
1
1 1
0 0
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-24
Time Response in Combinational CircuitsGlitch Example
F = A' D + A C'
input change within product term-- G1
G1
G2
G3
A
\C
\A
D
F
G1
G2
G3
A\C
\AD
F
1
1
1
1
1
0
0
1
1
1
1
0
0
0
ABCD = 1100 ABCD = 1101
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 0 0
0 0 0 0
00
01
11
10 C
CD
D
B
Lets look at what happens when input changes from 1100 -> 1101
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-25
G1
G2
G3
A\C
\AD
F
G1
G2
G3
A\C
\AD
F
0
1
0
0
1
0
0
1
1
1
1
1
0
0
ABCD = 1101 ABCD = 0101 (A is still 0)
G1
G2
G3
A\C
\AD
F
0
1
0
1
1
1
1
ABCD = 0101 (A is 1)
Time Response in Combinational Circuits
Glitch Example
input change that spans product termsoutput changes from 1 to 0 to 1
Examine K-Map:
When the intial and final inputs are covered by the sameprime implicant, no glitch is possible.
When the input change spans prime implicants, a glitch can happen.
gate delay
F = A glitch happened
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-26
Time Response in Combinational NetworksGlitch Example -- Eliminate static hazards
General Strategy: add redundant prime implicant terms
F = A' D + A C' becomes A' D + A C' + C' D
This eliminates 1-hazard. How about 0-hazard?
Re-express F in PoS form:
F = (A' + C')(A + D)
Glitch present!
Add term: (C' + D)
This expression is equivalentto the hazard-free SoP form of F
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 0 0
0 0 0 0
00
01
11
10 C
CD
D
B
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-27
Time Response in Combinational NetworksGlitch Example -- Eliminate static hazards
Start with expression that is free of static 1-hazards
F = A C' + A' D + C' D
F' = (A C' + A' D + C' D)'
= (A' + C) (A + D') (C + D')
= A C + A C D' + C D' + A' C D' + A' D'
= A C + C D' + A' D'
covers all the adjacent 0's in the K-map
free of static-1 and static-0 hazards!
F = (A’ + C’) (C’ + D) (A + D)
Work with complement:
Alternative approach to eliminate 0-hazards
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-28
Time Response in Combinational Networks
General Strategy for Static Hazard Elimination
Static 1-Hazards
Examine the K-map to make sure that all adjacent elements of theon-set are covered by a prime implicant.
If not, add redundant prime implicants until all elements of the on-set are covered
Static 0-Hazards
Reexpress function in POS form
Verify that adjacent elements of the off-set are covered by a common prime implicant in the PoS form.
If necessary, add more prime implicants to cover any uncoveredadjacencies.
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-29
Time Response in Combinational NetworksDetecting Static Hazards in Multi-Level Circuits
Map the multi-level function into a two-level form called transient output function
variables and complements are treated as independent variables
cannot use X + X' = 1 or X • X' = 0 for simplifications
F = A B C + (A + D) (A' + C')
F1 = A B C + A A' + A C' + A' D + C' D
Example:
2-level form
ABCD: 1111 to 1110, covered by term ABC, so no 1-hazard present
some static hazards are present!
ABCD: 1110 to 1100, term ABC goes low while term AC' goes high
1111 to 01111111 to 1101
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 1 0
0 0 1 0
00
01
11
10 C
CD
D
B
Examine K-map for static 1-hazards
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-30
100
A B C D F F 2
Time Response in Combinational Networks
Static 1-hazards
Solution:
Add redundant terms to insure all adjacent transitions are covered by terms
F2 = A C' + A' D + C' D + A B + B D
1's hazards in Fcorrected in F2
1111 to 0111, 1111 to 1101
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-31
Time Response in Combinational NetworksStatic 0-Hazards
Similar to previous case, but work with the complement of F
If terms of the transient output function cover all 0 transitions, then no 0-hazards are present
F = [A B C + (A + D) (A' + C')]'
= (A' + B' + C') (A' D' + A C)
= A' D' + A' B’ D' + A' C’ D' + A B' C
= A' D' + A B' C
0-hazard on transition from1010 to 0010
+ B' C D'
F3 = (A + D) (A' + B + C') (B + C' + D)
0-hazard free
equivalent to F2 on last slide
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 1 0
0 0 1 0
00
01
11
10 C
CD
D
B
Add redundantterm
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-32
100
A B C D F F 3
Time Response in Combinational NetworksStatic 0-Hazards
0-HazardCorrected in F3
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-33
Time Response in Combinational NetworksDesigning Networks for Hazard-free operation
Simply place transient output function in a form that guarantees that all adjacent ones are covered by a term
no term of the transient output function contains both a variable and its complement
F(A,B,C,D) = m(1,3,5,7,8,9,12,13,14,15)
F = A B + A' D + B D + A C' + C' D
= (A' + B + C') D + A (B + C')
(factored by distributive law, which does notintroduce hazards since it does not depend onthe complementarity laws for its validity)
A AB
00 01 11 10
0 0 1 1
1 1 1 1
1 1 1 0
0 0 1 0
00
01
11
10 C
CD
D
B
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-34
Time Response in Combinational NetworksDynamic Hazards -- happens because of multiple paths in the underlying
multilevel network, each with its own assymetric delayExample with Dynamic Hazard
Three different paths from B or B' to output
ABC = 000, F = 1 to ABC = 010, F = 0 different delays along the paths: G1 slow, G4 very slow
Handling dynamic hazards very complex. Beyond our scope
G1
G2
G3
G5
G4
\A B
\B
\B \C
F
A
0 1
1
1 0
1
0 1
1 0
1 0 1
1 0 0
1 0
1 0 1 0
Slow
V ery slow
fast
fast
fast
A multilevel network free of static hazards may still have dynamic hazards.So if a hazard-free network is needed, it is best to design a two-level statichazard-free network.
Contemporary Logic DesignMulti-Level Logic
© R.H. Katz Transparency No. 11-35
HW #11 -- Sections 5.2, 3.3, 3.4